From nobody Sun Feb 8 23:59:02 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1527777139594355.90768016569086; Thu, 31 May 2018 07:32:19 -0700 (PDT) Received: from localhost ([::1]:44430 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fOOcc-000726-Hn for importer@patchew.org; Thu, 31 May 2018 10:32:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41643) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fOOUv-0000sh-Ac for qemu-devel@nongnu.org; Thu, 31 May 2018 10:24:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fOOUu-0006XZ-6n for qemu-devel@nongnu.org; Thu, 31 May 2018 10:24:13 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:42284) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fOOUt-0006SF-UT for qemu-devel@nongnu.org; Thu, 31 May 2018 10:24:12 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fOOUj-0002ox-40 for qemu-devel@nongnu.org; Thu, 31 May 2018 15:24:01 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 31 May 2018 15:23:35 +0100 Message-Id: <20180531142357.904-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180531142357.904-1-peter.maydell@linaro.org> References: <20180531142357.904-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 03/25] hw/intc/arm_gicv3: Fix APxR register dispatching X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Jan Kiszka There was a nasty flip in identifying which register group an access is targeting. The issue caused spuriously raised priorities of the guest when handing CPUs over in the Jailhouse hypervisor. Cc: qemu-stable@nongnu.org Signed-off-by: Jan Kiszka Message-id: 28b927d3-da58-bce4-cc13-bfec7f9b1cb9@siemens.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_cpuif.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index cb9a3a542d..5c89be1af0 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -427,7 +427,7 @@ static uint64_t icv_ap_read(CPUARMState *env, const ARM= CPRegInfo *ri) { GICv3CPUState *cs =3D icc_cs_from_env(env); int regno =3D ri->opc2 & 3; - int grp =3D ri->crm & 1 ? GICV3_G0 : GICV3_G1NS; + int grp =3D (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; uint64_t value =3D cs->ich_apr[grp][regno]; =20 trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), va= lue); @@ -439,7 +439,7 @@ static void icv_ap_write(CPUARMState *env, const ARMCPR= egInfo *ri, { GICv3CPUState *cs =3D icc_cs_from_env(env); int regno =3D ri->opc2 & 3; - int grp =3D ri->crm & 1 ? GICV3_G0 : GICV3_G1NS; + int grp =3D (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; =20 trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), v= alue); =20 @@ -1461,7 +1461,7 @@ static uint64_t icc_ap_read(CPUARMState *env, const A= RMCPRegInfo *ri) uint64_t value; =20 int regno =3D ri->opc2 & 3; - int grp =3D ri->crm & 1 ? GICV3_G0 : GICV3_G1; + int grp =3D (ri->crm & 1) ? GICV3_G1 : GICV3_G0; =20 if (icv_access(env, grp =3D=3D GICV3_G0 ? HCR_FMO : HCR_IMO)) { return icv_ap_read(env, ri); @@ -1483,7 +1483,7 @@ static void icc_ap_write(CPUARMState *env, const ARMC= PRegInfo *ri, GICv3CPUState *cs =3D icc_cs_from_env(env); =20 int regno =3D ri->opc2 & 3; - int grp =3D ri->crm & 1 ? GICV3_G0 : GICV3_G1; + int grp =3D (ri->crm & 1) ? GICV3_G1 : GICV3_G0; =20 if (icv_access(env, grp =3D=3D GICV3_G0 ? HCR_FMO : HCR_IMO)) { icv_ap_write(env, ri, value); @@ -2292,7 +2292,7 @@ static uint64_t ich_ap_read(CPUARMState *env, const A= RMCPRegInfo *ri) { GICv3CPUState *cs =3D icc_cs_from_env(env); int regno =3D ri->opc2 & 3; - int grp =3D ri->crm & 1 ? GICV3_G0 : GICV3_G1NS; + int grp =3D (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; uint64_t value; =20 value =3D cs->ich_apr[grp][regno]; @@ -2305,7 +2305,7 @@ static void ich_ap_write(CPUARMState *env, const ARMC= PRegInfo *ri, { GICv3CPUState *cs =3D icc_cs_from_env(env); int regno =3D ri->opc2 & 3; - int grp =3D ri->crm & 1 ? GICV3_G0 : GICV3_G1NS; + int grp =3D (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; =20 trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), v= alue); =20 --=20 2.17.1