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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id b84-v6sm28179157pfm.123.2018.05.30.11.01.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 30 May 2018 11:01:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=20EZoQ8QPU8yFGAo8rpV97QFYZBSCVksGfxx17wN4pk=; b=XPvSo7W2DlD5+yKtl8Jnpj7xvmGrY4TtqP+dXnfcuf06PSUvX4HHH6JmziQVs3kslG ypxMwprfCD5kRWzBO05jxCbXT1+BuSJBPIPq4RllBXOfYrB3Qbo3WbwsLhso/yEd6n3L NXdN6V4qBYInRF3UA1udX98i9cVXyOAbZuySY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=20EZoQ8QPU8yFGAo8rpV97QFYZBSCVksGfxx17wN4pk=; b=ZOJy095RDKc3BxpeODPBF+duvHjiNzMosdV08Y554VVr+PzAYYyDp4nFLuvhI4e4dX j/8X1OxH06s6OQ7WC2kFEHg8NbcasQjQ48wfxDlC1PfpEl4SZVcMYiKDbcuhuqHuIFSZ f8QQSuiyWoXpvF6LwxQArhKOlAdlSUtqRs35iniIFzVvJP6Y4Y86DMiLQ7M7IdIf0d0K QJsLQwwqo2cxjyt/o8MF9ybtug/LbDfupujYHJwlib7Bzckv0HJyl20XNP1RkxMh2Wgh brMZ5OIkwASmDvBcMHL5lSN+7j4++h8U5x/0L68UQ20jg37n46UDmSK35XAgdQfsPpZ6 Y3uw== X-Gm-Message-State: ALKqPwdu40R2ESWrZpWAzzD3mWr3MTreGYHpvzisMmNQ/OdAZn+55q1j 3BrkV+p9vE6xgmmhpJ0W+4hlMuwOG18= X-Google-Smtp-Source: ADUXVKJKkwf67iUarqqx5XBTdbrFZ5I3b550XFdFEJy0OtxdInutJ6zqq70acSrNxD1TBfUE3A/kjA== X-Received: by 2002:a17:902:64cf:: with SMTP id y15-v6mr3840781pli.53.1527703287507; Wed, 30 May 2018 11:01:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 30 May 2018 11:01:05 -0700 Message-Id: <20180530180120.13355-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180530180120.13355-1-richard.henderson@linaro.org> References: <20180530180120.13355-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v3b 03/18] target/arm: Implement SVE Permute - Predicates Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 6 + target/arm/sve_helper.c | 290 +++++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 120 +++++++++++++++ target/arm/sve.decode | 18 +++ 4 files changed, 434 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 0c9aad575e..ff958fcebd 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -439,6 +439,12 @@ DEF_HELPER_FLAGS_3(sve_uunpk_h, TCG_CALL_NO_RWG, void,= ptr, ptr, i32) DEF_HELPER_FLAGS_3(sve_uunpk_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(sve_uunpk_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_4(sve_zip_p, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_uzp_p, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_trn_p, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_rev_p, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_punpk_p, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 58c0fda333..f4d49d4aff 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -1674,3 +1674,293 @@ DO_UNPK(sve_uunpk_s, uint32_t, uint16_t, H4, H2) DO_UNPK(sve_uunpk_d, uint64_t, uint32_t, , H4) =20 #undef DO_UNPK + +/* Mask of bits included in the even numbered predicates of width esz. + * We also use this for expand_bits/compress_bits, and so extend the + * same pattern out to 16-bit units. + */ +static const uint64_t even_bit_esz_masks[5] =3D { + 0x5555555555555555ull, + 0x3333333333333333ull, + 0x0f0f0f0f0f0f0f0full, + 0x00ff00ff00ff00ffull, + 0x0000ffff0000ffffull, +}; + +/* Zero-extend units of 2**N bits to units of 2**(N+1) bits. + * For N=3D=3D0, this corresponds to the operation that in qemu/bitops.h + * we call half_shuffle64; this algorithm is from Hacker's Delight, + * section 7-2 Shuffling Bits. + */ +static uint64_t expand_bits(uint64_t x, int n) +{ + int i; + + x &=3D 0xffffffffu; + for (i =3D 4; i >=3D n; i--) { + int sh =3D 1 << i; + x =3D ((x << sh) | x) & even_bit_esz_masks[i]; + } + return x; +} + +/* Compress units of 2**(N+1) bits to units of 2**N bits. + * For N=3D=3D0, this corresponds to the operation that in qemu/bitops.h + * we call half_unshuffle64; this algorithm is from Hacker's Delight, + * section 7-2 Shuffling Bits, where it is called an inverse half shuffle. + */ +static uint64_t compress_bits(uint64_t x, int n) +{ + int i; + + for (i =3D n; i <=3D 4; i++) { + int sh =3D 1 << i; + x &=3D even_bit_esz_masks[i]; + x =3D (x >> sh) | x; + } + return x & 0xffffffffu; +} + +void HELPER(sve_zip_p)(void *vd, void *vn, void *vm, uint32_t pred_desc) +{ + intptr_t oprsz =3D extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; + int esz =3D extract32(pred_desc, SIMD_DATA_SHIFT, 2); + intptr_t high =3D extract32(pred_desc, SIMD_DATA_SHIFT + 2, 1); + uint64_t *d =3D vd; + intptr_t i; + + if (oprsz <=3D 8) { + uint64_t nn =3D *(uint64_t *)vn; + uint64_t mm =3D *(uint64_t *)vm; + int half =3D 4 * oprsz; + + nn =3D extract64(nn, high * half, half); + mm =3D extract64(mm, high * half, half); + nn =3D expand_bits(nn, esz); + mm =3D expand_bits(mm, esz); + d[0] =3D nn + (mm << (1 << esz)); + } else { + ARMPredicateReg tmp_n, tmp_m; + + /* We produce output faster than we consume input. + Therefore we must be mindful of possible overlap. */ + if ((vn - vd) < (uintptr_t)oprsz) { + vn =3D memcpy(&tmp_n, vn, oprsz); + } + if ((vm - vd) < (uintptr_t)oprsz) { + vm =3D memcpy(&tmp_m, vm, oprsz); + } + if (high) { + high =3D oprsz >> 1; + } + + if ((high & 3) =3D=3D 0) { + uint32_t *n =3D vn, *m =3D vm; + high >>=3D 2; + + for (i =3D 0; i < DIV_ROUND_UP(oprsz, 8); i++) { + uint64_t nn =3D n[H4(high + i)]; + uint64_t mm =3D m[H4(high + i)]; + + nn =3D expand_bits(nn, esz); + mm =3D expand_bits(mm, esz); + d[i] =3D nn + (mm << (1 << esz)); + } + } else { + uint8_t *n =3D vn, *m =3D vm; + uint16_t *d16 =3D vd; + + for (i =3D 0; i < oprsz / 2; i++) { + uint16_t nn =3D n[H1(high + i)]; + uint16_t mm =3D m[H1(high + i)]; + + nn =3D expand_bits(nn, esz); + mm =3D expand_bits(mm, esz); + d16[H2(i)] =3D nn + (mm << (1 << esz)); + } + } + } +} + +void HELPER(sve_uzp_p)(void *vd, void *vn, void *vm, uint32_t pred_desc) +{ + intptr_t oprsz =3D extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; + int esz =3D extract32(pred_desc, SIMD_DATA_SHIFT, 2); + int odd =3D extract32(pred_desc, SIMD_DATA_SHIFT + 2, 1) << esz; + uint64_t *d =3D vd, *n =3D vn, *m =3D vm; + uint64_t l, h; + intptr_t i; + + if (oprsz <=3D 8) { + l =3D compress_bits(n[0] >> odd, esz); + h =3D compress_bits(m[0] >> odd, esz); + d[0] =3D extract64(l + (h << (4 * oprsz)), 0, 8 * oprsz); + } else { + ARMPredicateReg tmp_m; + intptr_t oprsz_16 =3D oprsz / 16; + + if ((vm - vd) < (uintptr_t)oprsz) { + m =3D memcpy(&tmp_m, vm, oprsz); + } + + for (i =3D 0; i < oprsz_16; i++) { + l =3D n[2 * i + 0]; + h =3D n[2 * i + 1]; + l =3D compress_bits(l >> odd, esz); + h =3D compress_bits(h >> odd, esz); + d[i] =3D l + (h << 32); + } + + /* For VL which is not a power of 2, the results from M do not + align nicely with the uint64_t for D. Put the aligned results + from M into TMP_M and then copy it into place afterward. */ + if (oprsz & 15) { + d[i] =3D compress_bits(n[2 * i] >> odd, esz); + + for (i =3D 0; i < oprsz_16; i++) { + l =3D m[2 * i + 0]; + h =3D m[2 * i + 1]; + l =3D compress_bits(l >> odd, esz); + h =3D compress_bits(h >> odd, esz); + tmp_m.p[i] =3D l + (h << 32); + } + tmp_m.p[i] =3D compress_bits(m[2 * i] >> odd, esz); + + swap_memmove(vd + oprsz / 2, &tmp_m, oprsz / 2); + } else { + for (i =3D 0; i < oprsz_16; i++) { + l =3D m[2 * i + 0]; + h =3D m[2 * i + 1]; + l =3D compress_bits(l >> odd, esz); + h =3D compress_bits(h >> odd, esz); + d[oprsz_16 + i] =3D l + (h << 32); + } + } + } +} + +void HELPER(sve_trn_p)(void *vd, void *vn, void *vm, uint32_t pred_desc) +{ + intptr_t oprsz =3D extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; + uintptr_t esz =3D extract32(pred_desc, SIMD_DATA_SHIFT, 2); + bool odd =3D extract32(pred_desc, SIMD_DATA_SHIFT + 2, 1); + uint64_t *d =3D vd, *n =3D vn, *m =3D vm; + uint64_t mask; + int shr, shl; + intptr_t i; + + shl =3D 1 << esz; + shr =3D 0; + mask =3D even_bit_esz_masks[esz]; + if (odd) { + mask <<=3D shl; + shr =3D shl; + shl =3D 0; + } + + for (i =3D 0; i < DIV_ROUND_UP(oprsz, 8); i++) { + uint64_t nn =3D (n[i] & mask) >> shr; + uint64_t mm =3D (m[i] & mask) << shl; + d[i] =3D nn + mm; + } +} + +/* Reverse units of 2**N bits. */ +static uint64_t reverse_bits_64(uint64_t x, int n) +{ + int i, sh; + + x =3D bswap64(x); + for (i =3D 2, sh =3D 4; i >=3D n; i--, sh >>=3D 1) { + uint64_t mask =3D even_bit_esz_masks[i]; + x =3D ((x & mask) << sh) | ((x >> sh) & mask); + } + return x; +} + +static uint8_t reverse_bits_8(uint8_t x, int n) +{ + static const uint8_t mask[3] =3D { 0x55, 0x33, 0x0f }; + int i, sh; + + for (i =3D 2, sh =3D 4; i >=3D n; i--, sh >>=3D 1) { + x =3D ((x & mask[i]) << sh) | ((x >> sh) & mask[i]); + } + return x; +} + +void HELPER(sve_rev_p)(void *vd, void *vn, uint32_t pred_desc) +{ + intptr_t oprsz =3D extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; + int esz =3D extract32(pred_desc, SIMD_DATA_SHIFT, 2); + intptr_t i, oprsz_2 =3D oprsz / 2; + + if (oprsz <=3D 8) { + uint64_t l =3D *(uint64_t *)vn; + l =3D reverse_bits_64(l << (64 - 8 * oprsz), esz); + *(uint64_t *)vd =3D l; + } else if ((oprsz & 15) =3D=3D 0) { + for (i =3D 0; i < oprsz_2; i +=3D 8) { + intptr_t ih =3D oprsz - 8 - i; + uint64_t l =3D reverse_bits_64(*(uint64_t *)(vn + i), esz); + uint64_t h =3D reverse_bits_64(*(uint64_t *)(vn + ih), esz); + *(uint64_t *)(vd + i) =3D h; + *(uint64_t *)(vd + ih) =3D l; + } + } else { + for (i =3D 0; i < oprsz_2; i +=3D 1) { + intptr_t il =3D H1(i); + intptr_t ih =3D H1(oprsz - 1 - i); + uint8_t l =3D reverse_bits_8(*(uint8_t *)(vn + il), esz); + uint8_t h =3D reverse_bits_8(*(uint8_t *)(vn + ih), esz); + *(uint8_t *)(vd + il) =3D h; + *(uint8_t *)(vd + ih) =3D l; + } + } +} + +void HELPER(sve_punpk_p)(void *vd, void *vn, uint32_t pred_desc) +{ + intptr_t oprsz =3D extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; + intptr_t high =3D extract32(pred_desc, SIMD_DATA_SHIFT + 2, 1); + uint64_t *d =3D vd; + intptr_t i; + + if (oprsz <=3D 8) { + uint64_t nn =3D *(uint64_t *)vn; + int half =3D 4 * oprsz; + + nn =3D extract64(nn, high * half, half); + nn =3D expand_bits(nn, 0); + d[0] =3D nn; + } else { + ARMPredicateReg tmp_n; + + /* We produce output faster than we consume input. + Therefore we must be mindful of possible overlap. */ + if ((vn - vd) < (uintptr_t)oprsz) { + vn =3D memcpy(&tmp_n, vn, oprsz); + } + if (high) { + high =3D oprsz >> 1; + } + + if ((high & 3) =3D=3D 0) { + uint32_t *n =3D vn; + high >>=3D 2; + + for (i =3D 0; i < DIV_ROUND_UP(oprsz, 8); i++) { + uint64_t nn =3D n[H4(high + i)]; + d[i] =3D expand_bits(nn, 0); + } + } else { + uint16_t *d16 =3D vd; + uint8_t *n =3D vn; + + for (i =3D 0; i < oprsz / 2; i++) { + uint16_t nn =3D n[H1(high + i)]; + d16[H2(i)] =3D expand_bits(nn, 0); + } + } + } +} diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 388cce9924..0160d06915 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -2089,6 +2089,126 @@ static bool trans_UNPK(DisasContext *s, arg_UNPK *a= , uint32_t insn) return true; } =20 +/* + *** SVE Permute - Predicates Group + */ + +static bool do_perm_pred3(DisasContext *s, arg_rrr_esz *a, bool high_odd, + gen_helper_gvec_3 *fn) +{ + if (!sve_access_check(s)) { + return true; + } + + unsigned vsz =3D pred_full_reg_size(s); + + /* Predicate sizes may be smaller and cannot use simd_desc. + We cannot round up, as we do elsewhere, because we need + the exact size for ZIP2 and REV. We retain the style for + the other helpers for consistency. */ + TCGv_ptr t_d =3D tcg_temp_new_ptr(); + TCGv_ptr t_n =3D tcg_temp_new_ptr(); + TCGv_ptr t_m =3D tcg_temp_new_ptr(); + TCGv_i32 t_desc; + int desc; + + desc =3D vsz - 2; + desc =3D deposit32(desc, SIMD_DATA_SHIFT, 2, a->esz); + desc =3D deposit32(desc, SIMD_DATA_SHIFT + 2, 2, high_odd); + + tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd)); + tcg_gen_addi_ptr(t_n, cpu_env, pred_full_reg_offset(s, a->rn)); + tcg_gen_addi_ptr(t_m, cpu_env, pred_full_reg_offset(s, a->rm)); + t_desc =3D tcg_const_i32(desc); + + fn(t_d, t_n, t_m, t_desc); + + tcg_temp_free_ptr(t_d); + tcg_temp_free_ptr(t_n); + tcg_temp_free_ptr(t_m); + tcg_temp_free_i32(t_desc); + return true; +} + +static bool do_perm_pred2(DisasContext *s, arg_rr_esz *a, bool high_odd, + gen_helper_gvec_2 *fn) +{ + if (!sve_access_check(s)) { + return true; + } + + unsigned vsz =3D pred_full_reg_size(s); + TCGv_ptr t_d =3D tcg_temp_new_ptr(); + TCGv_ptr t_n =3D tcg_temp_new_ptr(); + TCGv_i32 t_desc; + int desc; + + tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd)); + tcg_gen_addi_ptr(t_n, cpu_env, pred_full_reg_offset(s, a->rn)); + + /* Predicate sizes may be smaller and cannot use simd_desc. + We cannot round up, as we do elsewhere, because we need + the exact size for ZIP2 and REV. We retain the style for + the other helpers for consistency. */ + + desc =3D vsz - 2; + desc =3D deposit32(desc, SIMD_DATA_SHIFT, 2, a->esz); + desc =3D deposit32(desc, SIMD_DATA_SHIFT + 2, 2, high_odd); + t_desc =3D tcg_const_i32(desc); + + fn(t_d, t_n, t_desc); + + tcg_temp_free_i32(t_desc); + tcg_temp_free_ptr(t_d); + tcg_temp_free_ptr(t_n); + return true; +} + +static bool trans_ZIP1_p(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + return do_perm_pred3(s, a, 0, gen_helper_sve_zip_p); +} + +static bool trans_ZIP2_p(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + return do_perm_pred3(s, a, 1, gen_helper_sve_zip_p); +} + +static bool trans_UZP1_p(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + return do_perm_pred3(s, a, 0, gen_helper_sve_uzp_p); +} + +static bool trans_UZP2_p(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + return do_perm_pred3(s, a, 1, gen_helper_sve_uzp_p); +} + +static bool trans_TRN1_p(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + return do_perm_pred3(s, a, 0, gen_helper_sve_trn_p); +} + +static bool trans_TRN2_p(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + return do_perm_pred3(s, a, 1, gen_helper_sve_trn_p); +} + +static bool trans_REV_p(DisasContext *s, arg_rr_esz *a, uint32_t insn) +{ + return do_perm_pred2(s, a, 0, gen_helper_sve_rev_p); +} + +static bool trans_PUNPKLO(DisasContext *s, arg_PUNPKLO *a, uint32_t insn) +{ + return do_perm_pred2(s, a, 0, gen_helper_sve_punpk_p); +} + +static bool trans_PUNPKHI(DisasContext *s, arg_PUNPKHI *a, uint32_t insn) +{ + return do_perm_pred2(s, a, 1, gen_helper_sve_punpk_p); +} + /* *** SVE Memory - 32-bit Gather and Unsized Contiguous Group */ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 7ffd7962c8..26fe1608c4 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -86,6 +86,7 @@ =20 # Three operand, vector element size @rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz +@pd_pn_pm ........ esz:2 .. rm:4 ....... rn:4 . rd:4 &rrr_esz @rdn_rm ........ esz:2 ...... ...... rm:5 rd:5 \ &rrr_esz rn=3D%reg_movprfx =20 @@ -396,6 +397,23 @@ TBL 00000101 .. 1 ..... 001100 ..... .....= @rd_rn_rm # SVE unpack vector elements UNPK 00000101 esz:2 1100 u:1 h:1 001110 rn:5 rd:5 =20 +### SVE Permute - Predicates Group + +# SVE permute predicate elements +ZIP1_p 00000101 .. 10 .... 010 000 0 .... 0 .... @pd_pn_pm +ZIP2_p 00000101 .. 10 .... 010 001 0 .... 0 .... @pd_pn_pm +UZP1_p 00000101 .. 10 .... 010 010 0 .... 0 .... @pd_pn_pm +UZP2_p 00000101 .. 10 .... 010 011 0 .... 0 .... @pd_pn_pm +TRN1_p 00000101 .. 10 .... 010 100 0 .... 0 .... @pd_pn_pm +TRN2_p 00000101 .. 10 .... 010 101 0 .... 0 .... @pd_pn_pm + +# SVE reverse predicate elements +REV_p 00000101 .. 11 0100 010 000 0 .... 0 .... @pd_pn + +# SVE unpack predicate elements +PUNPKLO 00000101 00 11 0000 010 000 0 .... 0 .... @pd_pn_e0 +PUNPKHI 00000101 00 11 0001 010 000 0 .... 0 .... @pd_pn_e0 + ### SVE Predicate Logical Operations Group =20 # SVE predicate logical operations --=20 2.17.0