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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id b84-v6sm28179157pfm.123.2018.05.30.11.01.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 30 May 2018 11:01:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aA/5S2B3GjqKGo0kl9R3P8OKdMyH3ZHUd87Da/paKlg=; b=afMY4qfZxvqQvTpb00F2BJkqB7b30V/b04qbLBZWR9LXoy+2Nst7zVwfZZGJHwJ/c0 MyMkjzd6kInkOg+4KrIuoji+IFBfLQQRPy1DUSzys3aJ0g0FDah6bobVkyvgbuz+JLdI wejRE0BlSxfqi70lqEJG7WkswmrTZZDnSz9cc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aA/5S2B3GjqKGo0kl9R3P8OKdMyH3ZHUd87Da/paKlg=; b=IVRg8/rFF4h0J3q1ZwDTHNC2Z3PwNPHVb7uBA4Lcj9rXny+tl4ISyuMNMM2IpmG0gI lxP+IuLBXb9DWdsyzMwboZjvjlk4dkcu7vjkrin8kD/AvkCI4TyWi5UpLCxlydpRRYiA D6efxTGI5rqW9iZ7qVZn2XPiMYDHi/fP/Z8zcUiSpz9B0QmCGApxqr+W0fz/TpQd02is g4EG2sNow8Zi4wWi/UgF/hLAs1XVhVhAEuwaNOEsEnLZlfNLw2KMtL2U7QAZnCgYSTgh 6FujpmkMdYksIRxThemRthlLMrvmPuIpfn4YGmN5dHs09VyBCiGztAUv5LrWNmizUkh2 jvsA== X-Gm-Message-State: ALKqPwc8XzbsF0KgA7qgNmiu+ZO45rLqYJ/efB8hyJcX2Hy7h1cuFGMo 6TNitdQj7wSjE0pTBRYneTsRrRyDRx8= X-Google-Smtp-Source: ADUXVKIyv91PSqLJ1urKfAELsJ1HfEPu4TuFrx81fq0XfbvuP2gdTniSpZjMd9BpeqaXUwbugeQUyw== X-Received: by 2002:a62:5841:: with SMTP id m62-v6mr3657555pfb.116.1527703306707; Wed, 30 May 2018 11:01:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 30 May 2018 11:01:17 -0700 Message-Id: <20180530180120.13355-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180530180120.13355-1-richard.henderson@linaro.org> References: <20180530180120.13355-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22a Subject: [Qemu-devel] [PATCH v3b 15/18] target/arm: Implement SVE Integer Compare - Scalars Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 2 + target/arm/sve_helper.c | 31 +++++++++++ target/arm/translate-sve.c | 102 +++++++++++++++++++++++++++++++++++++ target/arm/sve.decode | 8 +++ 4 files changed, 143 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index dd4f8f754d..1863106d0f 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -678,3 +678,5 @@ DEF_HELPER_FLAGS_4(sve_brkn, TCG_CALL_NO_RWG, void, ptr= , ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_brkns, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) =20 DEF_HELPER_FLAGS_3(sve_cntp, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(sve_while, TCG_CALL_NO_RWG, i32, ptr, i32, i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 8d1631ea3c..a65a06cc9e 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -2736,3 +2736,34 @@ uint64_t HELPER(sve_cntp)(void *vn, void *vg, uint32= _t pred_desc) } return sum; } + +uint32_t HELPER(sve_while)(void *vd, uint32_t count, uint32_t pred_desc) +{ + uintptr_t oprsz =3D extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; + intptr_t esz =3D extract32(pred_desc, SIMD_DATA_SHIFT, 2); + uint64_t esz_mask =3D pred_esz_masks[esz]; + ARMPredicateReg *d =3D vd; + uint32_t flags; + intptr_t i; + + /* Begin with a zero predicate register. */ + flags =3D do_zero(d, oprsz); + if (count =3D=3D 0) { + return flags; + } + + /* Scale from predicate element count to bits. */ + count <<=3D esz; + /* Bound to the bits in the predicate. */ + count =3D MIN(count, oprsz * 8); + + /* Set all of the requested bits. */ + for (i =3D 0; i < count / 64; ++i) { + d->p[i] =3D esz_mask; + } + if (count & 63) { + d->p[i] =3D ~(-1ull << (count & 63)) & esz_mask; + } + + return predtest_ones(d, oprsz, esz_mask); +} diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index e4815e4912..75eb36f110 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -3081,6 +3081,108 @@ static bool trans_SINCDECP_z(DisasContext *s, arg_i= ncdec2_pred *a, return true; } =20 +/* + *** SVE Integer Compare Scalars Group + */ + +static bool trans_CTERM(DisasContext *s, arg_CTERM *a, uint32_t insn) +{ + if (!sve_access_check(s)) { + return true; + } + + TCGCond cond =3D (a->ne ? TCG_COND_NE : TCG_COND_EQ); + TCGv_i64 rn =3D read_cpu_reg(s, a->rn, a->sf); + TCGv_i64 rm =3D read_cpu_reg(s, a->rm, a->sf); + TCGv_i64 cmp =3D tcg_temp_new_i64(); + + tcg_gen_setcond_i64(cond, cmp, rn, rm); + tcg_gen_extrl_i64_i32(cpu_NF, cmp); + tcg_temp_free_i64(cmp); + + /* VF =3D !NF & !CF. */ + tcg_gen_xori_i32(cpu_VF, cpu_NF, 1); + tcg_gen_andc_i32(cpu_VF, cpu_VF, cpu_CF); + + /* Both NF and VF actually look at bit 31. */ + tcg_gen_neg_i32(cpu_NF, cpu_NF); + tcg_gen_neg_i32(cpu_VF, cpu_VF); + return true; +} + +static bool trans_WHILE(DisasContext *s, arg_WHILE *a, uint32_t insn) +{ + if (!sve_access_check(s)) { + return true; + } + + TCGv_i64 op0 =3D read_cpu_reg(s, a->rn, 1); + TCGv_i64 op1 =3D read_cpu_reg(s, a->rm, 1); + TCGv_i64 t0 =3D tcg_temp_new_i64(); + TCGv_i64 t1 =3D tcg_temp_new_i64(); + TCGv_i32 t2, t3; + TCGv_ptr ptr; + unsigned desc, vsz =3D vec_full_reg_size(s); + TCGCond cond; + + if (!a->sf) { + if (a->u) { + tcg_gen_ext32u_i64(op0, op0); + tcg_gen_ext32u_i64(op1, op1); + } else { + tcg_gen_ext32s_i64(op0, op0); + tcg_gen_ext32s_i64(op1, op1); + } + } + + /* For the helper, compress the different conditions into a computation + * of how many iterations for which the condition is true. + * + * This is slightly complicated by 0 <=3D UINT64_MAX, which is nominal= ly + * 2**64 iterations, overflowing to 0. Of course, predicate registers + * aren't that large, so any value >=3D predicate size is sufficient. + */ + tcg_gen_sub_i64(t0, op1, op0); + + /* t0 =3D MIN(op1 - op0, vsz). */ + if (a->eq) { + /* Equality means one more iteration. */ + tcg_gen_movi_i64(t1, vsz - 1); + tcg_gen_movcond_i64(TCG_COND_LTU, t0, t0, t1, t0, t1); + tcg_gen_addi_i64(t0, t0, 1); + } else { + tcg_gen_movi_i64(t1, vsz); + tcg_gen_movcond_i64(TCG_COND_LTU, t0, t0, t1, t0, t1); + } + + /* t0 =3D (condition true ? t0 : 0). */ + cond =3D (a->u + ? (a->eq ? TCG_COND_LEU : TCG_COND_LTU) + : (a->eq ? TCG_COND_LE : TCG_COND_LT)); + tcg_gen_movi_i64(t1, 0); + tcg_gen_movcond_i64(cond, t0, op0, op1, t0, t1); + + t2 =3D tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(t2, t0); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + + desc =3D (vsz / 8) - 2; + desc =3D deposit32(desc, SIMD_DATA_SHIFT, 2, a->esz); + t3 =3D tcg_const_i32(desc); + + ptr =3D tcg_temp_new_ptr(); + tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd)); + + gen_helper_sve_while(t2, ptr, t2, t3); + do_pred_flags(t2); + + tcg_temp_free_ptr(ptr); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); + return true; +} + /* *** SVE Memory - 32-bit Gather and Unsized Contiguous Group */ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 62d51c252b..4b718060a9 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -606,6 +606,14 @@ SINCDECP_r_64 00100101 .. 1010 d:1 u:1 10001 10 ....= ..... @incdec_pred # SVE saturating inc/dec vector by predicate count SINCDECP_z 00100101 .. 1010 d:1 u:1 10000 00 .... ..... @incdec2_p= red =20 +### SVE Integer Compare - Scalars Group + +# SVE conditionally terminate scalars +CTERM 00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1 0000 + +# SVE integer compare scalar count and limit +WHILE 00100101 esz:2 1 rm:5 000 sf:1 u:1 1 rn:5 eq:1 rd:4 + ### SVE Memory - 32-bit Gather and Unsized Contiguous Group =20 # SVE load predicate register --=20 2.17.0