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X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v2] aspeed_scu: Implement RNG register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ASPEED SoCs contain a single register that returns random data when read. This models that register so that guests can use it. The random number data register has a corresponding control register, data returns a different number regardless of the state of the enabled bit, so the model follows this behaviour. Signed-off-by: Joel Stanley Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- v2: - Remove call to qcrypto_random_init as this is done in main() --- hw/misc/aspeed_scu.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 5e6d5744eeca..29e58527793b 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -16,6 +16,7 @@ #include "qapi/visitor.h" #include "qemu/bitops.h" #include "qemu/log.h" +#include "crypto/random.h" #include "trace.h" =20 #define TO_REG(offset) ((offset) >> 2) @@ -154,6 +155,18 @@ static const uint32_t ast2500_a1_resets[ASPEED_SCU_NR_= REGS] =3D { [BMC_DEV_ID] =3D 0x00002402U }; =20 +static uint32_t aspeed_scu_get_random(void) +{ + Error *err =3D NULL; + uint32_t num; + + if (qcrypto_random_bytes((uint8_t *)&num, sizeof(num), &err)) { + error_report_err(err); + } + + return num; +} + static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size) { AspeedSCUState *s =3D ASPEED_SCU(opaque); @@ -167,6 +180,9 @@ static uint64_t aspeed_scu_read(void *opaque, hwaddr of= fset, unsigned size) } =20 switch (reg) { + case RNG_DATA: + s->regs[RNG_DATA] =3D aspeed_scu_get_random(); + break; case WAKEUP_EN: qemu_log_mask(LOG_GUEST_ERROR, "%s: Read of write-only offset 0x%" HWADDR_PRIx "\n", --=20 2.17.0