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[50.233.235.3]) by smtp.gmail.com with ESMTPSA id b89-v6sm66680075pfd.85.2018.05.27.07.13.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 27 May 2018 07:13:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NRIJ9Lwc5CFHxEmzWGEY918Q+UpbMyHa2iijO6bsHM4=; b=g7H63wcu7cBs5uJIKVv9jfNw2fJ6R3HCJqUpBmuZ3vyFnKbTF2yq8u9P+WeHXF3k+B 9RMxZcX4F8mSTFEJt+DCgw9rUITdY8BgD+P8yJ7mMUc8zSE4h1/BeXs/D6hVqJ0KQH8o CMBm9BngUGLIs5Xtj+MenANPTXE/9n+ZAMtUg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NRIJ9Lwc5CFHxEmzWGEY918Q+UpbMyHa2iijO6bsHM4=; b=T56rKkqcbBYSenGiUE49uDehTSWb4u4ktddHbhZm026OI78lAdVRBwO+5aC7hl1FiN aJduRbqUh7x4SUtIH+gXkKtzxmPNt1Ip7KFx4FfptZSL+Vl6eAd0+vcF9c6Aa0hV7mdO n1sbBBEzlzCeepb7LKUJK4WzBs6j+Hz6SE8MtHkbUNt4dkVKsmv4a+WApdKlEwaruuXB pz5Y3UhecykWrmwOr16NbmMFOCRWIUk6LCmSu1flk4GmkoWf98xH+2l9RxqDycKB7OwT 0qcHiFPBSL0NdCSqh3PvrBcZlJUny3rreTCDThL6yfK78FlH+Ijp/PaRN2XbbhoS4Tph Y9vA== X-Gm-Message-State: ALKqPwe5Jx8r1c31zUDXmWoN751NclL9ZcVQZuo4wGVHLX4Q6YkgY0L6 tlLq6ClgF6n21M6GxTSP2GE194daXemVag== X-Google-Smtp-Source: AB8JxZrwNZAyIts04u52XVBD7mCf0axI8l4PU/t8QIQfdN23QzqHmtgnHoswSpFITtdmL3p2pfpBkA== X-Received: by 2002:a17:902:3a5:: with SMTP id d34-v6mr10202945pld.103.1527430425014; Sun, 27 May 2018 07:13:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 27 May 2018 09:13:15 -0500 Message-Id: <20180527141324.11937-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180527141324.11937-1-richard.henderson@linaro.org> References: <20180527141324.11937-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH 11/20] target/openrisc: Reduce tlb to a single dimension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" While we had defines for *_WAY, we didn't define more than 1. Reduce the complexity by eliminating this unused dimension. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/openrisc/cpu.h | 6 ++---- target/openrisc/machine.c | 6 ++---- target/openrisc/mmu.c | 30 ++++++++++++++++-------------- target/openrisc/sys_helper.c | 20 ++++++++++---------- 4 files changed, 30 insertions(+), 32 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 13107058cb..947ca00d8d 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -222,10 +222,8 @@ enum { =20 /* TLB size */ enum { - DTLB_WAYS =3D 1, DTLB_SIZE =3D 64, DTLB_MASK =3D (DTLB_SIZE-1), - ITLB_WAYS =3D 1, ITLB_SIZE =3D 64, ITLB_MASK =3D (ITLB_SIZE-1), }; @@ -256,8 +254,8 @@ typedef struct OpenRISCTLBEntry { =20 #ifndef CONFIG_USER_ONLY typedef struct CPUOpenRISCTLBContext { - OpenRISCTLBEntry itlb[ITLB_WAYS][ITLB_SIZE]; - OpenRISCTLBEntry dtlb[DTLB_WAYS][DTLB_SIZE]; + OpenRISCTLBEntry itlb[ITLB_SIZE]; + OpenRISCTLBEntry dtlb[DTLB_SIZE]; =20 int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu, hwaddr *physical, diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index 73e0abcfd7..b795b56dc6 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -42,11 +42,9 @@ static const VMStateDescription vmstate_cpu_tlb =3D { .minimum_version_id =3D 1, .minimum_version_id_old =3D 1, .fields =3D (VMStateField[]) { - VMSTATE_STRUCT_2DARRAY(itlb, CPUOpenRISCTLBContext, - ITLB_WAYS, ITLB_SIZE, 0, + VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, ITLB_SIZE, 0, vmstate_tlb_entry, OpenRISCTLBEntry), - VMSTATE_STRUCT_2DARRAY(dtlb, CPUOpenRISCTLBContext, - DTLB_WAYS, DTLB_SIZE, 0, + VMSTATE_STRUCT_ARRAY(dtlb, CPUOpenRISCTLBContext, DTLB_SIZE, 0, vmstate_tlb_entry, OpenRISCTLBEntry), VMSTATE_END_OF_LIST() } diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 9b4b5cf04f..23edd8c78c 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -43,19 +43,21 @@ static int get_phys_code(OpenRISCCPU *cpu, hwaddr *phys= ical, int *prot, int vpn =3D address >> TARGET_PAGE_BITS; int idx =3D vpn & ITLB_MASK; int right =3D 0; + uint32_t mr =3D cpu->env.tlb.itlb[idx].mr; + uint32_t tr =3D cpu->env.tlb.itlb[idx].tr; =20 - if ((cpu->env.tlb.itlb[0][idx].mr >> TARGET_PAGE_BITS) !=3D vpn) { + if ((mr >> TARGET_PAGE_BITS) !=3D vpn) { return TLBRET_NOMATCH; } - if (!(cpu->env.tlb.itlb[0][idx].mr & 1)) { + if (!(mr & 1)) { return TLBRET_INVALID; } if (supervisor) { - if (cpu->env.tlb.itlb[0][idx].tr & SXE) { + if (tr & SXE) { right |=3D PAGE_EXEC; } } else { - if (cpu->env.tlb.itlb[0][idx].tr & UXE) { + if (tr & UXE) { right |=3D PAGE_EXEC; } } @@ -63,8 +65,7 @@ static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physic= al, int *prot, return TLBRET_BADADDR; } =20 - *physical =3D (cpu->env.tlb.itlb[0][idx].tr & TARGET_PAGE_MASK) | - (address & (TARGET_PAGE_SIZE-1)); + *physical =3D (tr & TARGET_PAGE_MASK) | (address & (TARGET_PAGE_SIZE-1= )); *prot =3D right; return TLBRET_MATCH; } @@ -75,25 +76,27 @@ static int get_phys_data(OpenRISCCPU *cpu, hwaddr *phys= ical, int *prot, int vpn =3D address >> TARGET_PAGE_BITS; int idx =3D vpn & DTLB_MASK; int right =3D 0; + uint32_t mr =3D cpu->env.tlb.dtlb[idx].mr; + uint32_t tr =3D cpu->env.tlb.dtlb[idx].tr; =20 - if ((cpu->env.tlb.dtlb[0][idx].mr >> TARGET_PAGE_BITS) !=3D vpn) { + if ((mr >> TARGET_PAGE_BITS) !=3D vpn) { return TLBRET_NOMATCH; } - if (!(cpu->env.tlb.dtlb[0][idx].mr & 1)) { + if (!(mr & 1)) { return TLBRET_INVALID; } if (supervisor) { - if (cpu->env.tlb.dtlb[0][idx].tr & SRE) { + if (tr & SRE) { right |=3D PAGE_READ; } - if (cpu->env.tlb.dtlb[0][idx].tr & SWE) { + if (tr & SWE) { right |=3D PAGE_WRITE; } } else { - if (cpu->env.tlb.dtlb[0][idx].tr & URE) { + if (tr & URE) { right |=3D PAGE_READ; } - if (cpu->env.tlb.dtlb[0][idx].tr & UWE) { + if (tr & UWE) { right |=3D PAGE_WRITE; } } @@ -105,8 +108,7 @@ static int get_phys_data(OpenRISCCPU *cpu, hwaddr *phys= ical, int *prot, return TLBRET_BADADDR; } =20 - *physical =3D (cpu->env.tlb.dtlb[0][idx].tr & TARGET_PAGE_MASK) | - (address & (TARGET_PAGE_SIZE-1)); + *physical =3D (tr & TARGET_PAGE_MASK) | (address & (TARGET_PAGE_SIZE-1= )); *prot =3D right; return TLBRET_MATCH; } diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index a1285894ad..8ad7a7d898 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -85,14 +85,14 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong = spr, target_ulong rb) case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 = */ idx =3D spr - TO_SPR(1, 512); if (!(rb & 1)) { - tlb_flush_page(cs, env->tlb.dtlb[0][idx].mr & TARGET_PAGE_MASK= ); + tlb_flush_page(cs, env->tlb.dtlb[idx].mr & TARGET_PAGE_MASK); } - env->tlb.dtlb[0][idx].mr =3D rb; + env->tlb.dtlb[idx].mr =3D rb; break; =20 case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 = */ idx =3D spr - TO_SPR(1, 640); - env->tlb.dtlb[0][idx].tr =3D rb; + env->tlb.dtlb[idx].tr =3D rb; break; case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ @@ -104,14 +104,14 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulon= g spr, target_ulong rb) case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-12= 7 */ idx =3D spr - TO_SPR(2, 512); if (!(rb & 1)) { - tlb_flush_page(cs, env->tlb.itlb[0][idx].mr & TARGET_PAGE_MASK= ); + tlb_flush_page(cs, env->tlb.itlb[idx].mr & TARGET_PAGE_MASK); } - env->tlb.itlb[0][idx].mr =3D rb; + env->tlb.itlb[idx].mr =3D rb; break; =20 case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 = */ idx =3D spr - TO_SPR(2, 640); - env->tlb.itlb[0][idx].tr =3D rb; + env->tlb.itlb[idx].tr =3D rb; break; case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ @@ -243,11 +243,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, tar= get_ulong rd, =20 case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 = */ idx =3D spr - TO_SPR(1, 512); - return env->tlb.dtlb[0][idx].mr; + return env->tlb.dtlb[idx].mr; =20 case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 = */ idx =3D spr - TO_SPR(1, 640); - return env->tlb.dtlb[0][idx].tr; + return env->tlb.dtlb[idx].tr; =20 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ @@ -259,11 +259,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, tar= get_ulong rd, =20 case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 = */ idx =3D spr - TO_SPR(2, 512); - return env->tlb.itlb[0][idx].mr; + return env->tlb.itlb[idx].mr; =20 case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 = */ idx =3D spr - TO_SPR(2, 640); - return env->tlb.itlb[0][idx].tr; + return env->tlb.itlb[idx].tr; =20 case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ --=20 2.17.0