From nobody Tue Dec 16 11:48:22 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1527293112703616.4092107558565; Fri, 25 May 2018 17:05:12 -0700 (PDT) Received: from localhost ([::1]:47134 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fMMhs-0005Gv-0i for importer@patchew.org; Fri, 25 May 2018 20:05:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52502) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fMMYM-0006Nz-R2 for qemu-devel@nongnu.org; Fri, 25 May 2018 19:55:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fMMYJ-0007zD-Ts for qemu-devel@nongnu.org; Fri, 25 May 2018 19:55:22 -0400 Received: from mx3-rdu2.redhat.com ([66.187.233.73]:49342 helo=mx1.redhat.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fMMYD-0007iJ-Cs; Fri, 25 May 2018 19:55:13 -0400 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 4B69B40BC04B; Fri, 25 May 2018 23:55:12 +0000 (UTC) Received: from probe.bos.redhat.com (dhcp-17-177.bos.redhat.com [10.18.17.177]) by smtp.corp.redhat.com (Postfix) with ESMTP id 0C694111AF18; Fri, 25 May 2018 23:55:12 +0000 (UTC) From: John Snow To: qemu-devel@nongnu.org, qemu-block@nongnu.org Date: Fri, 25 May 2018 19:54:54 -0400 Message-Id: <20180525235509.11282-2-jsnow@redhat.com> In-Reply-To: <20180525235509.11282-1-jsnow@redhat.com> References: <20180525235509.11282-1-jsnow@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Fri, 25 May 2018 23:55:12 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Fri, 25 May 2018 23:55:12 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'jsnow@redhat.com' RCPT:'' X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.187.233.73 Subject: [Qemu-devel] [PATCH 01/16] ahci: add port register enumeration X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: John Snow Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Instead of tracking offsets, lets count the registers. Signed-off-by: John Snow --- hw/ide/ahci.c | 25 +++++++++++++++++++++++++ hw/ide/ahci_internal.h | 29 +++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index e22d7be05f..48130c6439 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -46,6 +46,31 @@ static bool ahci_map_fis_address(AHCIDevice *ad); static void ahci_unmap_clb_address(AHCIDevice *ad); static void ahci_unmap_fis_address(AHCIDevice *ad); =20 +__attribute__((__unused__)) /* TODO */ +static const char *AHCIPortReg_lookup[AHCI_PORT_REG__COUNT] =3D { + [AHCI_PORT_REG_LST_ADDR] =3D "PxCLB", + [AHCI_PORT_REG_LST_ADDR_HI] =3D "PxCLBU", + [AHCI_PORT_REG_FIS_ADDR] =3D "PxFB", + [AHCI_PORT_REG_FIS_ADDR_HI] =3D "PxFBU", + [AHCI_PORT_REG_IRQ_STAT] =3D "PxIS", + [AHCI_PORT_REG_IRQ_MASK] =3D "PXIE", + [AHCI_PORT_REG_CMD] =3D "PxCMD", + [7] =3D "Reserved", + [AHCI_PORT_REG_TFDATA] =3D "PxTFD", + [AHCI_PORT_REG_SIG] =3D "PxSIG", + [AHCI_PORT_REG_SCR_STAT] =3D "PxSSTS", + [AHCI_PORT_REG_SCR_CTL] =3D "PxSCTL", + [AHCI_PORT_REG_SCR_ERR] =3D "PxSERR", + [AHCI_PORT_REG_SCR_ACT] =3D "PxSACT", + [AHCI_PORT_REG_CMD_ISSUE] =3D "PxCI", + [AHCI_PORT_REG_SCR_NOTIF] =3D "PxSNTF", + [AHCI_PORT_REG_FIS_CTL] =3D "PxFBS", + [AHCI_PORT_REG_DEV_SLEEP] =3D "PxDEVSLP", + [18 ... 27] =3D "Reserved", + [AHCI_PORT_REG_VENDOR_1 ... + AHCI_PORT_REG_VENDOR_4] =3D "PxVS", +}; + static const char *AHCIPortIRQ_lookup[AHCI_PORT_IRQ__COUNT] =3D { [AHCI_PORT_IRQ_BIT_DHRS] =3D "DHRS", [AHCI_PORT_IRQ_BIT_PSS] =3D "PSS", diff --git a/hw/ide/ahci_internal.h b/hw/ide/ahci_internal.h index 1a25d6c039..eb7e1eefc0 100644 --- a/hw/ide/ahci_internal.h +++ b/hw/ide/ahci_internal.h @@ -74,6 +74,34 @@ #define HOST_CAP_NCQ (1 << 30) /* Native Command Queueing */ #define HOST_CAP_64 (1U << 31) /* PCI DAC (64-bit DMA) suppo= rt */ =20 +/* registers for each SATA port */ +enum AHCIPortReg { + AHCI_PORT_REG_LST_ADDR =3D 0, /* PxCLB: command list DMA addr */ + AHCI_PORT_REG_LST_ADDR_HI =3D 1, /* PxCLBU: command list DMA addr hi */ + AHCI_PORT_REG_FIS_ADDR =3D 2, /* PxFB: FIS rx buf addr */ + AHCI_PORT_REG_FIS_ADDR_HI =3D 3, /* PxFBU: FIX rx buf addr hi */ + AHCI_PORT_REG_IRQ_STAT =3D 4, /* PxIS: interrupt status */ + AHCI_PORT_REG_IRQ_MASK =3D 5, /* PxIE: interrupt enable/disable mas= k */ + AHCI_PORT_REG_CMD =3D 6, /* PxCMD: port command */ + /* RESERVED */ + AHCI_PORT_REG_TFDATA =3D 8, /* PxTFD: taskfile data */ + AHCI_PORT_REG_SIG =3D 9, /* PxSIG: device TF signature */ + AHCI_PORT_REG_SCR_STAT =3D 10, /* PxSSTS: SATA phy register: SStatu= s */ + AHCI_PORT_REG_SCR_CTL =3D 11, /* PxSCTL: SATA phy register: SContr= ol */ + AHCI_PORT_REG_SCR_ERR =3D 12, /* PxSERR: SATA phy register: SError= */ + AHCI_PORT_REG_SCR_ACT =3D 13, /* PxSACT: SATA phy register: SActiv= e */ + AHCI_PORT_REG_CMD_ISSUE =3D 14, /* PxCI: command issue */ + AHCI_PORT_REG_SCR_NOTIF =3D 15, /* PxSNTF: SATA phy register: SNotif= ication */ + AHCI_PORT_REG_FIS_CTL =3D 16, /* PxFBS: Port multiplier switching = ctl */ + AHCI_PORT_REG_DEV_SLEEP =3D 17, /* PxDEVSLP: device sleep control */ + /* RESERVED */ + AHCI_PORT_REG_VENDOR_1 =3D 28, /* PxVS: Vendor Specific */ + AHCI_PORT_REG_VENDOR_2 =3D 29, + AHCI_PORT_REG_VENDOR_3 =3D 30, + AHCI_PORT_REG_VENDOR_4 =3D 31, + AHCI_PORT_REG__COUNT =3D 32 +}; + /* registers for each SATA port */ #define PORT_LST_ADDR 0x00 /* command list DMA addr */ #define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */ @@ -82,6 +110,7 @@ #define PORT_IRQ_STAT 0x10 /* interrupt status */ #define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */ #define PORT_CMD 0x18 /* port command */ + #define PORT_TFDATA 0x20 /* taskfile data */ #define PORT_SIG 0x24 /* device TF signature */ #define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */ --=20 2.14.3