From nobody Fri May 3 01:09:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1527010718503724.7136826124773; Tue, 22 May 2018 10:38:38 -0700 (PDT) Received: from localhost ([::1]:57062 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fLBEy-0005u5-Sb for importer@patchew.org; Tue, 22 May 2018 13:38:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34979) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fLBDx-0005aM-U3 for qemu-devel@nongnu.org; Tue, 22 May 2018 13:37:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fLBDw-0006cP-W3 for qemu-devel@nongnu.org; Tue, 22 May 2018 13:37:25 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:42126) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fLBDu-0006Zf-JK; Tue, 22 May 2018 13:37:22 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fLBDm-00018u-Lx; Tue, 22 May 2018 18:37:14 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 22 May 2018 18:37:13 +0100 Message-Id: <20180522173713.26282-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH] Correct CPACR reset value for v7 cores X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 In commit f0aff255700 we made cpacr_write() enforce that some CPACR bits are RAZ/WI and some are RAO/WI for ARMv7 cores. Unfortunately we forgot to also update the register's reset value. The effect was that (a) a guest that read CPACR on reset would not see ones in the RAO bits, and (b) if you did a migration before the guest did a write to the CPACR then the migration would fail because the destination would enforce the RAO bits and then complain that they didn't match the zero value from the source. Implement reset for the CPACR using a custom reset function that just calls cpacr_write(), to avoid having to duplicate the logic for which bits are RAO. This bug would affect migration for TCG CPUs which are ARMv7 with VFP but without one of Neon or VFPv3. Reported-by: C=C3=A9dric Le Goater Signed-off-by: Peter Maydell Tested-by: C=C3=A9dric Le Goater --- This is sufficient that a save-and-reload while the romulus-bmc machine is in the bootloader will work. On the other hand if I do a save-and-reload after the kernel has started booting then we get the classic "guest hang after reload", so some state is still not being transferred somewhere (probably in a device in the machine model?) --- target/arm/helper.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index c0f739972e..6023bf6046 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -863,6 +863,14 @@ static void cpacr_write(CPUARMState *env, const ARMCPR= egInfo *ri, env->cp15.cpacr_el1 =3D value; } =20 +static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* Call cpacr_write() so that we reset with the correct RAO bits set + * for our CPU features. + */ + cpacr_write(env, ri, 0); +} + static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *r= i, bool isread) { @@ -920,7 +928,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { { .name =3D "CPACR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 1, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, .accessfn =3D cpac= r_access, .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.cpac= r_el1), - .resetvalue =3D 0, .writefn =3D cpacr_write }, + .resetfn =3D cpacr_reset, .writefn =3D cpacr_write }, REGINFO_SENTINEL }; =20 --=20 2.17.0