From nobody Mon Feb 9 03:29:18 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526920659656836.092111619461; Mon, 21 May 2018 09:37:39 -0700 (PDT) Received: from localhost ([::1]:51559 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fKnoY-0003RK-To for importer@patchew.org; Mon, 21 May 2018 12:37:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48021) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fKnjM-0007od-EH for qemu-devel@nongnu.org; Mon, 21 May 2018 12:32:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fKnjI-00087Q-EQ for qemu-devel@nongnu.org; Mon, 21 May 2018 12:32:16 -0400 Received: from mga14.intel.com ([192.55.52.115]:48359) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fKnjI-00085w-4y for qemu-devel@nongnu.org; Mon, 21 May 2018 12:32:12 -0400 Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 May 2018 09:32:10 -0700 Received: from theros.lm.intel.com ([10.232.112.164]) by FMSMGA003.fm.intel.com with ESMTP; 21 May 2018 09:32:10 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,426,1520924400"; d="scan'208";a="50961711" From: Ross Zwisler To: Igor Mammedov , qemu-devel@nongnu.org Date: Mon, 21 May 2018 10:32:02 -0600 Message-Id: <20180521163203.26590-4-ross.zwisler@linux.intel.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180521163203.26590-1-ross.zwisler@linux.intel.com> References: <20180521163203.26590-1-ross.zwisler@linux.intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.115 Subject: [Qemu-devel] [qemu PATCH v4 3/4] nvdimm, acpi: support NFIT platform capabilities X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Haozhong Zhang , Eduardo Habkost , linux-nvdimm , "Michael S . Tsirkin" , Stefan Hajnoczi , Ross Zwisler , "Elliott, Robert \(Persistent Memory\)" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add a machine command line option to allow the user to control the Platform Capabilities Structure in the virtualized NFIT. This Platform Capabilities Structure was added in ACPI 6.2 Errata A. Signed-off-by: Ross Zwisler --- docs/nvdimm.txt | 27 +++++++++++++++++++++++++++ hw/acpi/nvdimm.c | 45 +++++++++++++++++++++++++++++++++++++++++---- hw/i386/pc.c | 31 +++++++++++++++++++++++++++++++ include/hw/i386/pc.h | 1 + include/hw/mem/nvdimm.h | 5 +++++ 5 files changed, 105 insertions(+), 4 deletions(-) diff --git a/docs/nvdimm.txt b/docs/nvdimm.txt index e903d8bb09..8b48fb4633 100644 --- a/docs/nvdimm.txt +++ b/docs/nvdimm.txt @@ -153,3 +153,30 @@ guest NVDIMM region mapping structure. This unarmed f= lag indicates guest software that this vNVDIMM device contains a region that cannot accept persistent writes. In result, for example, the guest Linux NVDIMM driver, marks such vNVDIMM device as read-only. + +Platform Capabilities +--------------------- + +ACPI 6.2 Errata A added support for a new Platform Capabilities Structure +which allows the platform to communicate what features it supports related= to +NVDIMM data durability. Users can provide a capabilities value to a guest= via +the optional "nvdimm-cap" machine command line option: + + -machine pc,accel=3Dkvm,nvdimm,nvdimm-cap=3D2 + +This "nvdimm-cap" field is an integer, and is the combined value of the +various capability bits defined in table 5-137 of the ACPI 6.2 Errata A sp= ec. + +Here is a quick summary of the three bits that are defined as of that spec: + +Bit[0] - CPU Cache Flush to NVDIMM Durability on Power Loss Capable. +Bit[1] - Memory Controller Flush to NVDIMM Durability on Power Loss Capabl= e. + Note: If bit 0 is set to 1 then this bit shall be set to 1 as wel= l. +Bit[2] - Byte Addressable Persistent Memory Hardware Mirroring Capable. + +So, a "nvdimm-cap" value of 2 would mean that the platform supports Memory +Controller Flush on Power Loss, a value of 3 would mean that the platform +supports CPU Cache Flush and Memory Controller Flush on Power Loss, etc. + +For a complete list of the flags available and for more detailed descripti= ons, +please consult the ACPI spec. diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c index 59d6e4254c..87e4280c71 100644 --- a/hw/acpi/nvdimm.c +++ b/hw/acpi/nvdimm.c @@ -169,6 +169,21 @@ struct NvdimmNfitControlRegion { } QEMU_PACKED; typedef struct NvdimmNfitControlRegion NvdimmNfitControlRegion; =20 +/* + * NVDIMM Platform Capabilities Structure + * + * Defined in section 5.2.25.9 of ACPI 6.2 Errata A, September 2017 + */ +struct NvdimmNfitPlatformCaps { + uint16_t type; + uint16_t length; + uint8_t highest_cap; + uint8_t reserved[3]; + uint32_t capabilities; + uint8_t reserved2[4]; +} QEMU_PACKED; +typedef struct NvdimmNfitPlatformCaps NvdimmNfitPlatformCaps; + /* * Module serial number is a unique number for each device. We use the * slot id of NVDIMM device to generate this number so that each device @@ -351,7 +366,23 @@ static void nvdimm_build_structure_dcr(GArray *structu= res, DeviceState *dev) JEDEC Annex L Release 3. */); } =20 -static GArray *nvdimm_build_device_structure(void) +/* + * ACPI 6.2 Errata A: 5.2.25.9 NVDIMM Platform Capabilities Structure + */ +static void +nvdimm_build_structure_caps(GArray *structures, uint32_t capabilities) +{ + NvdimmNfitPlatformCaps *nfit_caps; + + nfit_caps =3D acpi_data_push(structures, sizeof(*nfit_caps)); + + nfit_caps->type =3D cpu_to_le16(7 /* NVDIMM Platform Capabilities */); + nfit_caps->length =3D cpu_to_le16(sizeof(*nfit_caps)); + nfit_caps->highest_cap =3D 31 - clz32(capabilities); + nfit_caps->capabilities =3D cpu_to_le32(capabilities); +} + +static GArray *nvdimm_build_device_structure(AcpiNVDIMMState *state) { GSList *device_list =3D nvdimm_get_device_list(); GArray *structures =3D g_array_new(false, true /* clear */, 1); @@ -373,6 +404,10 @@ static GArray *nvdimm_build_device_structure(void) } g_slist_free(device_list); =20 + if (state->capabilities) { + nvdimm_build_structure_caps(structures, state->capabilities); + } + return structures; } =20 @@ -381,16 +416,18 @@ static void nvdimm_init_fit_buffer(NvdimmFitBuffer *f= it_buf) fit_buf->fit =3D g_array_new(false, true /* clear */, 1); } =20 -static void nvdimm_build_fit_buffer(NvdimmFitBuffer *fit_buf) +static void nvdimm_build_fit_buffer(AcpiNVDIMMState *state) { + NvdimmFitBuffer *fit_buf =3D &state->fit_buf; + g_array_free(fit_buf->fit, true); - fit_buf->fit =3D nvdimm_build_device_structure(); + fit_buf->fit =3D nvdimm_build_device_structure(state); fit_buf->dirty =3D true; } =20 void nvdimm_plug(AcpiNVDIMMState *state) { - nvdimm_build_fit_buffer(&state->fit_buf); + nvdimm_build_fit_buffer(state); } =20 static void nvdimm_build_nfit(AcpiNVDIMMState *state, GArray *table_offset= s, diff --git a/hw/i386/pc.c b/hw/i386/pc.c index d768930d02..1b2684c549 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -2182,6 +2182,33 @@ static void pc_machine_set_nvdimm(Object *obj, bool = value, Error **errp) pcms->acpi_nvdimm_state.is_enabled =3D value; } =20 +static void pc_machine_get_nvdimm_capabilities(Object *obj, Visitor *v, + const char *name, void *opa= que, + Error **errp) +{ + PCMachineState *pcms =3D PC_MACHINE(obj); + uint32_t value =3D pcms->acpi_nvdimm_state.capabilities; + + visit_type_uint32(v, name, &value, errp); +} + +static void pc_machine_set_nvdimm_capabilities(Object *obj, Visitor *v, + const char *name, void *opa= que, + Error **errp) +{ + PCMachineState *pcms =3D PC_MACHINE(obj); + Error *error =3D NULL; + uint32_t value; + + visit_type_uint32(v, name, &value, &error); + if (error) { + error_propagate(errp, error); + return; + } + + pcms->acpi_nvdimm_state.capabilities =3D value; +} + static bool pc_machine_get_smbus(Object *obj, Error **errp) { PCMachineState *pcms =3D PC_MACHINE(obj); @@ -2395,6 +2422,10 @@ static void pc_machine_class_init(ObjectClass *oc, v= oid *data) object_class_property_add_bool(oc, PC_MACHINE_NVDIMM, pc_machine_get_nvdimm, pc_machine_set_nvdimm, &error_abort); =20 + object_class_property_add(oc, PC_MACHINE_NVDIMM_CAP, "uint32", + pc_machine_get_nvdimm_capabilities, + pc_machine_set_nvdimm_capabilities, NULL, NULL, &error_abort); + object_class_property_add_bool(oc, PC_MACHINE_SMBUS, pc_machine_get_smbus, pc_machine_set_smbus, &error_abort); =20 diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 2a98e3ad68..e9b22f929c 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -76,6 +76,7 @@ struct PCMachineState { #define PC_MACHINE_VMPORT "vmport" #define PC_MACHINE_SMM "smm" #define PC_MACHINE_NVDIMM "nvdimm" +#define PC_MACHINE_NVDIMM_CAP "nvdimm-cap" #define PC_MACHINE_SMBUS "smbus" #define PC_MACHINE_SATA "sata" #define PC_MACHINE_PIT "pit" diff --git a/include/hw/mem/nvdimm.h b/include/hw/mem/nvdimm.h index 74c60332e1..3c82751bab 100644 --- a/include/hw/mem/nvdimm.h +++ b/include/hw/mem/nvdimm.h @@ -134,6 +134,11 @@ struct AcpiNVDIMMState { =20 /* the IO region used by OSPM to transfer control to QEMU. */ MemoryRegion io_mr; + + /* + * Platform capabilities, section 5.2.25.9 of ACPI 6.2 Errata A + */ + int32_t capabilities; }; typedef struct AcpiNVDIMMState AcpiNVDIMMState; =20 --=20 2.14.3