From nobody Mon Apr 7 14:42:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526664651229100.51689471548502; Fri, 18 May 2018 10:30:51 -0700 (PDT) Received: from localhost ([::1]:40155 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJjDM-0002EK-KA for importer@patchew.org; Fri, 18 May 2018 13:30:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35936) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJj3B-0000aA-W7 for qemu-devel@nongnu.org; Fri, 18 May 2018 13:20:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJj38-0007PH-LD for qemu-devel@nongnu.org; Fri, 18 May 2018 13:20:17 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:41780) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fJj38-0007Oi-1Z for qemu-devel@nongnu.org; Fri, 18 May 2018 13:20:14 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fJj37-0004lG-2H for qemu-devel@nongnu.org; Fri, 18 May 2018 18:20:13 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 18 May 2018 18:19:41 +0100 Message-Id: <20180518172009.14416-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180518172009.14416-1-peter.maydell@linaro.org> References: <20180518172009.14416-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 04/32] xlnx-zdma: Add a model of the Xilinx ZynqMP generic DMA X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Francisco Iglesias Add a model of the generic DMA found on Xilinx ZynqMP. Signed-off-by: Francisco Iglesias Signed-off-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Message-id: 20180503214201.29082-2-frasse.iglesias@gmail.com Signed-off-by: Peter Maydell --- hw/dma/Makefile.objs | 1 + include/hw/dma/xlnx-zdma.h | 84 ++++ hw/dma/xlnx-zdma.c | 832 +++++++++++++++++++++++++++++++++++++ 3 files changed, 917 insertions(+) create mode 100644 include/hw/dma/xlnx-zdma.h create mode 100644 hw/dma/xlnx-zdma.c diff --git a/hw/dma/Makefile.objs b/hw/dma/Makefile.objs index c2afecbf73..79affecc39 100644 --- a/hw/dma/Makefile.objs +++ b/hw/dma/Makefile.objs @@ -10,6 +10,7 @@ common-obj-$(CONFIG_ETRAXFS) +=3D etraxfs_dma.o common-obj-$(CONFIG_STP2000) +=3D sparc32_dma.o obj-$(CONFIG_XLNX_ZYNQMP) +=3D xlnx_dpdma.o obj-$(CONFIG_XLNX_ZYNQMP_ARM) +=3D xlnx_dpdma.o +common-obj-$(CONFIG_XLNX_ZYNQMP_ARM) +=3D xlnx-zdma.o =20 obj-$(CONFIG_OMAP) +=3D omap_dma.o soc_dma.o obj-$(CONFIG_PXA2XX) +=3D pxa2xx_dma.o diff --git a/include/hw/dma/xlnx-zdma.h b/include/hw/dma/xlnx-zdma.h new file mode 100644 index 0000000000..0b240b4c3c --- /dev/null +++ b/include/hw/dma/xlnx-zdma.h @@ -0,0 +1,84 @@ +/* + * QEMU model of the ZynqMP generic DMA + * + * Copyright (c) 2014 Xilinx Inc. + * Copyright (c) 2018 FEIMTECH AB + * + * Written by Edgar E. Iglesias , + * Francisco Iglesias + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef XLNX_ZDMA_H +#define XLNX_ZDMA_H + +#include "hw/sysbus.h" +#include "hw/register.h" +#include "sysemu/dma.h" + +#define ZDMA_R_MAX (0x204 / 4) + +typedef enum { + DISABLED =3D 0, + ENABLED =3D 1, + PAUSED =3D 2, +} XlnxZDMAState; + +typedef union { + struct { + uint64_t addr; + uint32_t size; + uint32_t attr; + }; + uint32_t words[4]; +} XlnxZDMADescr; + +typedef struct XlnxZDMA { + SysBusDevice parent_obj; + MemoryRegion iomem; + MemTxAttrs attr; + MemoryRegion *dma_mr; + AddressSpace *dma_as; + qemu_irq irq_zdma_ch_imr; + + struct { + uint32_t bus_width; + } cfg; + + XlnxZDMAState state; + bool error; + + XlnxZDMADescr dsc_src; + XlnxZDMADescr dsc_dst; + + uint32_t regs[ZDMA_R_MAX]; + RegisterInfo regs_info[ZDMA_R_MAX]; + + /* We don't model the common bufs. Must be at least 16 bytes + to model write only mode. */ + uint8_t buf[2048]; +} XlnxZDMA; + +#define TYPE_XLNX_ZDMA "xlnx.zdma" + +#define XLNX_ZDMA(obj) \ + OBJECT_CHECK(XlnxZDMA, (obj), TYPE_XLNX_ZDMA) + +#endif /* XLNX_ZDMA_H */ diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c new file mode 100644 index 0000000000..14d86c254b --- /dev/null +++ b/hw/dma/xlnx-zdma.c @@ -0,0 +1,832 @@ +/* + * QEMU model of the ZynqMP generic DMA + * + * Copyright (c) 2014 Xilinx Inc. + * Copyright (c) 2018 FEIMTECH AB + * + * Written by Edgar E. Iglesias , + * Francisco Iglesias + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/dma/xlnx-zdma.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qapi/error.h" + +#ifndef XLNX_ZDMA_ERR_DEBUG +#define XLNX_ZDMA_ERR_DEBUG 0 +#endif + +REG32(ZDMA_ERR_CTRL, 0x0) + FIELD(ZDMA_ERR_CTRL, APB_ERR_RES, 0, 1) +REG32(ZDMA_CH_ISR, 0x100) + FIELD(ZDMA_CH_ISR, DMA_PAUSE, 11, 1) + FIELD(ZDMA_CH_ISR, DMA_DONE, 10, 1) + FIELD(ZDMA_CH_ISR, AXI_WR_DATA, 9, 1) + FIELD(ZDMA_CH_ISR, AXI_RD_DATA, 8, 1) + FIELD(ZDMA_CH_ISR, AXI_RD_DST_DSCR, 7, 1) + FIELD(ZDMA_CH_ISR, AXI_RD_SRC_DSCR, 6, 1) + FIELD(ZDMA_CH_ISR, IRQ_DST_ACCT_ERR, 5, 1) + FIELD(ZDMA_CH_ISR, IRQ_SRC_ACCT_ERR, 4, 1) + FIELD(ZDMA_CH_ISR, BYTE_CNT_OVRFL, 3, 1) + FIELD(ZDMA_CH_ISR, DST_DSCR_DONE, 2, 1) + FIELD(ZDMA_CH_ISR, SRC_DSCR_DONE, 1, 1) + FIELD(ZDMA_CH_ISR, INV_APB, 0, 1) +REG32(ZDMA_CH_IMR, 0x104) + FIELD(ZDMA_CH_IMR, DMA_PAUSE, 11, 1) + FIELD(ZDMA_CH_IMR, DMA_DONE, 10, 1) + FIELD(ZDMA_CH_IMR, AXI_WR_DATA, 9, 1) + FIELD(ZDMA_CH_IMR, AXI_RD_DATA, 8, 1) + FIELD(ZDMA_CH_IMR, AXI_RD_DST_DSCR, 7, 1) + FIELD(ZDMA_CH_IMR, AXI_RD_SRC_DSCR, 6, 1) + FIELD(ZDMA_CH_IMR, IRQ_DST_ACCT_ERR, 5, 1) + FIELD(ZDMA_CH_IMR, IRQ_SRC_ACCT_ERR, 4, 1) + FIELD(ZDMA_CH_IMR, BYTE_CNT_OVRFL, 3, 1) + FIELD(ZDMA_CH_IMR, DST_DSCR_DONE, 2, 1) + FIELD(ZDMA_CH_IMR, SRC_DSCR_DONE, 1, 1) + FIELD(ZDMA_CH_IMR, INV_APB, 0, 1) +REG32(ZDMA_CH_IEN, 0x108) + FIELD(ZDMA_CH_IEN, DMA_PAUSE, 11, 1) + FIELD(ZDMA_CH_IEN, DMA_DONE, 10, 1) + FIELD(ZDMA_CH_IEN, AXI_WR_DATA, 9, 1) + FIELD(ZDMA_CH_IEN, AXI_RD_DATA, 8, 1) + FIELD(ZDMA_CH_IEN, AXI_RD_DST_DSCR, 7, 1) + FIELD(ZDMA_CH_IEN, AXI_RD_SRC_DSCR, 6, 1) + FIELD(ZDMA_CH_IEN, IRQ_DST_ACCT_ERR, 5, 1) + FIELD(ZDMA_CH_IEN, IRQ_SRC_ACCT_ERR, 4, 1) + FIELD(ZDMA_CH_IEN, BYTE_CNT_OVRFL, 3, 1) + FIELD(ZDMA_CH_IEN, DST_DSCR_DONE, 2, 1) + FIELD(ZDMA_CH_IEN, SRC_DSCR_DONE, 1, 1) + FIELD(ZDMA_CH_IEN, INV_APB, 0, 1) +REG32(ZDMA_CH_IDS, 0x10c) + FIELD(ZDMA_CH_IDS, DMA_PAUSE, 11, 1) + FIELD(ZDMA_CH_IDS, DMA_DONE, 10, 1) + FIELD(ZDMA_CH_IDS, AXI_WR_DATA, 9, 1) + FIELD(ZDMA_CH_IDS, AXI_RD_DATA, 8, 1) + FIELD(ZDMA_CH_IDS, AXI_RD_DST_DSCR, 7, 1) + FIELD(ZDMA_CH_IDS, AXI_RD_SRC_DSCR, 6, 1) + FIELD(ZDMA_CH_IDS, IRQ_DST_ACCT_ERR, 5, 1) + FIELD(ZDMA_CH_IDS, IRQ_SRC_ACCT_ERR, 4, 1) + FIELD(ZDMA_CH_IDS, BYTE_CNT_OVRFL, 3, 1) + FIELD(ZDMA_CH_IDS, DST_DSCR_DONE, 2, 1) + FIELD(ZDMA_CH_IDS, SRC_DSCR_DONE, 1, 1) + FIELD(ZDMA_CH_IDS, INV_APB, 0, 1) +REG32(ZDMA_CH_CTRL0, 0x110) + FIELD(ZDMA_CH_CTRL0, OVR_FETCH, 7, 1) + FIELD(ZDMA_CH_CTRL0, POINT_TYPE, 6, 1) + FIELD(ZDMA_CH_CTRL0, MODE, 4, 2) + FIELD(ZDMA_CH_CTRL0, RATE_CTRL, 3, 1) + FIELD(ZDMA_CH_CTRL0, CONT_ADDR, 2, 1) + FIELD(ZDMA_CH_CTRL0, CONT, 1, 1) +REG32(ZDMA_CH_CTRL1, 0x114) + FIELD(ZDMA_CH_CTRL1, DST_ISSUE, 5, 5) + FIELD(ZDMA_CH_CTRL1, SRC_ISSUE, 0, 5) +REG32(ZDMA_CH_FCI, 0x118) + FIELD(ZDMA_CH_FCI, PROG_CELL_CNT, 2, 2) + FIELD(ZDMA_CH_FCI, SIDE, 1, 1) + FIELD(ZDMA_CH_FCI, EN, 0, 1) +REG32(ZDMA_CH_STATUS, 0x11c) + FIELD(ZDMA_CH_STATUS, STATE, 0, 2) +REG32(ZDMA_CH_DATA_ATTR, 0x120) + FIELD(ZDMA_CH_DATA_ATTR, ARBURST, 26, 2) + FIELD(ZDMA_CH_DATA_ATTR, ARCACHE, 22, 4) + FIELD(ZDMA_CH_DATA_ATTR, ARQOS, 18, 4) + FIELD(ZDMA_CH_DATA_ATTR, ARLEN, 14, 4) + FIELD(ZDMA_CH_DATA_ATTR, AWBURST, 12, 2) + FIELD(ZDMA_CH_DATA_ATTR, AWCACHE, 8, 4) + FIELD(ZDMA_CH_DATA_ATTR, AWQOS, 4, 4) + FIELD(ZDMA_CH_DATA_ATTR, AWLEN, 0, 4) +REG32(ZDMA_CH_DSCR_ATTR, 0x124) + FIELD(ZDMA_CH_DSCR_ATTR, AXCOHRNT, 8, 1) + FIELD(ZDMA_CH_DSCR_ATTR, AXCACHE, 4, 4) + FIELD(ZDMA_CH_DSCR_ATTR, AXQOS, 0, 4) +REG32(ZDMA_CH_SRC_DSCR_WORD0, 0x128) +REG32(ZDMA_CH_SRC_DSCR_WORD1, 0x12c) + FIELD(ZDMA_CH_SRC_DSCR_WORD1, MSB, 0, 17) +REG32(ZDMA_CH_SRC_DSCR_WORD2, 0x130) + FIELD(ZDMA_CH_SRC_DSCR_WORD2, SIZE, 0, 30) +REG32(ZDMA_CH_SRC_DSCR_WORD3, 0x134) + FIELD(ZDMA_CH_SRC_DSCR_WORD3, CMD, 3, 2) + FIELD(ZDMA_CH_SRC_DSCR_WORD3, INTR, 2, 1) + FIELD(ZDMA_CH_SRC_DSCR_WORD3, TYPE, 1, 1) + FIELD(ZDMA_CH_SRC_DSCR_WORD3, COHRNT, 0, 1) +REG32(ZDMA_CH_DST_DSCR_WORD0, 0x138) +REG32(ZDMA_CH_DST_DSCR_WORD1, 0x13c) + FIELD(ZDMA_CH_DST_DSCR_WORD1, MSB, 0, 17) +REG32(ZDMA_CH_DST_DSCR_WORD2, 0x140) + FIELD(ZDMA_CH_DST_DSCR_WORD2, SIZE, 0, 30) +REG32(ZDMA_CH_DST_DSCR_WORD3, 0x144) + FIELD(ZDMA_CH_DST_DSCR_WORD3, INTR, 2, 1) + FIELD(ZDMA_CH_DST_DSCR_WORD3, TYPE, 1, 1) + FIELD(ZDMA_CH_DST_DSCR_WORD3, COHRNT, 0, 1) +REG32(ZDMA_CH_WR_ONLY_WORD0, 0x148) +REG32(ZDMA_CH_WR_ONLY_WORD1, 0x14c) +REG32(ZDMA_CH_WR_ONLY_WORD2, 0x150) +REG32(ZDMA_CH_WR_ONLY_WORD3, 0x154) +REG32(ZDMA_CH_SRC_START_LSB, 0x158) +REG32(ZDMA_CH_SRC_START_MSB, 0x15c) + FIELD(ZDMA_CH_SRC_START_MSB, ADDR, 0, 17) +REG32(ZDMA_CH_DST_START_LSB, 0x160) +REG32(ZDMA_CH_DST_START_MSB, 0x164) + FIELD(ZDMA_CH_DST_START_MSB, ADDR, 0, 17) +REG32(ZDMA_CH_RATE_CTRL, 0x18c) + FIELD(ZDMA_CH_RATE_CTRL, CNT, 0, 12) +REG32(ZDMA_CH_SRC_CUR_PYLD_LSB, 0x168) +REG32(ZDMA_CH_SRC_CUR_PYLD_MSB, 0x16c) + FIELD(ZDMA_CH_SRC_CUR_PYLD_MSB, ADDR, 0, 17) +REG32(ZDMA_CH_DST_CUR_PYLD_LSB, 0x170) +REG32(ZDMA_CH_DST_CUR_PYLD_MSB, 0x174) + FIELD(ZDMA_CH_DST_CUR_PYLD_MSB, ADDR, 0, 17) +REG32(ZDMA_CH_SRC_CUR_DSCR_LSB, 0x178) +REG32(ZDMA_CH_SRC_CUR_DSCR_MSB, 0x17c) + FIELD(ZDMA_CH_SRC_CUR_DSCR_MSB, ADDR, 0, 17) +REG32(ZDMA_CH_DST_CUR_DSCR_LSB, 0x180) +REG32(ZDMA_CH_DST_CUR_DSCR_MSB, 0x184) + FIELD(ZDMA_CH_DST_CUR_DSCR_MSB, ADDR, 0, 17) +REG32(ZDMA_CH_TOTAL_BYTE, 0x188) +REG32(ZDMA_CH_RATE_CNTL, 0x18c) + FIELD(ZDMA_CH_RATE_CNTL, CNT, 0, 12) +REG32(ZDMA_CH_IRQ_SRC_ACCT, 0x190) + FIELD(ZDMA_CH_IRQ_SRC_ACCT, CNT, 0, 8) +REG32(ZDMA_CH_IRQ_DST_ACCT, 0x194) + FIELD(ZDMA_CH_IRQ_DST_ACCT, CNT, 0, 8) +REG32(ZDMA_CH_DBG0, 0x198) + FIELD(ZDMA_CH_DBG0, CMN_BUF_FREE, 0, 9) +REG32(ZDMA_CH_DBG1, 0x19c) + FIELD(ZDMA_CH_DBG1, CMN_BUF_OCC, 0, 9) +REG32(ZDMA_CH_CTRL2, 0x200) + FIELD(ZDMA_CH_CTRL2, EN, 0, 1) + +enum { + PT_REG =3D 0, + PT_MEM =3D 1, +}; + +enum { + CMD_HALT =3D 1, + CMD_STOP =3D 2, +}; + +enum { + RW_MODE_RW =3D 0, + RW_MODE_WO =3D 1, + RW_MODE_RO =3D 2, +}; + +enum { + DTYPE_LINEAR =3D 0, + DTYPE_LINKED =3D 1, +}; + +enum { + AXI_BURST_FIXED =3D 0, + AXI_BURST_INCR =3D 1, +}; + +static void zdma_ch_imr_update_irq(XlnxZDMA *s) +{ + bool pending; + + pending =3D s->regs[R_ZDMA_CH_ISR] & ~s->regs[R_ZDMA_CH_IMR]; + + qemu_set_irq(s->irq_zdma_ch_imr, pending); +} + +static void zdma_ch_isr_postw(RegisterInfo *reg, uint64_t val64) +{ + XlnxZDMA *s =3D XLNX_ZDMA(reg->opaque); + zdma_ch_imr_update_irq(s); +} + +static uint64_t zdma_ch_ien_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxZDMA *s =3D XLNX_ZDMA(reg->opaque); + uint32_t val =3D val64; + + s->regs[R_ZDMA_CH_IMR] &=3D ~val; + zdma_ch_imr_update_irq(s); + return 0; +} + +static uint64_t zdma_ch_ids_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxZDMA *s =3D XLNX_ZDMA(reg->opaque); + uint32_t val =3D val64; + + s->regs[R_ZDMA_CH_IMR] |=3D val; + zdma_ch_imr_update_irq(s); + return 0; +} + +static void zdma_set_state(XlnxZDMA *s, XlnxZDMAState state) +{ + s->state =3D state; + ARRAY_FIELD_DP32(s->regs, ZDMA_CH_STATUS, STATE, state); + + /* Signal error if we have an error condition. */ + if (s->error) { + ARRAY_FIELD_DP32(s->regs, ZDMA_CH_STATUS, STATE, 3); + } +} + +static void zdma_src_done(XlnxZDMA *s) +{ + unsigned int cnt; + cnt =3D ARRAY_FIELD_EX32(s->regs, ZDMA_CH_IRQ_SRC_ACCT, CNT); + cnt++; + ARRAY_FIELD_DP32(s->regs, ZDMA_CH_IRQ_SRC_ACCT, CNT, cnt); + ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, SRC_DSCR_DONE, true); + + /* Did we overflow? */ + if (cnt !=3D ARRAY_FIELD_EX32(s->regs, ZDMA_CH_IRQ_SRC_ACCT, CNT)) { + ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, IRQ_SRC_ACCT_ERR, true); + } + zdma_ch_imr_update_irq(s); +} + +static void zdma_dst_done(XlnxZDMA *s) +{ + unsigned int cnt; + cnt =3D ARRAY_FIELD_EX32(s->regs, ZDMA_CH_IRQ_DST_ACCT, CNT); + cnt++; + ARRAY_FIELD_DP32(s->regs, ZDMA_CH_IRQ_DST_ACCT, CNT, cnt); + ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, DST_DSCR_DONE, true); + + /* Did we overflow? */ + if (cnt !=3D ARRAY_FIELD_EX32(s->regs, ZDMA_CH_IRQ_DST_ACCT, CNT)) { + ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, IRQ_DST_ACCT_ERR, true); + } + zdma_ch_imr_update_irq(s); +} + +static uint64_t zdma_get_regaddr64(XlnxZDMA *s, unsigned int basereg) +{ + uint64_t addr; + + addr =3D s->regs[basereg + 1]; + addr <<=3D 32; + addr |=3D s->regs[basereg]; + + return addr; +} + +static void zdma_put_regaddr64(XlnxZDMA *s, unsigned int basereg, uint64_t= addr) +{ + s->regs[basereg] =3D addr; + s->regs[basereg + 1] =3D addr >> 32; +} + +static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, void *buf) +{ + /* ZDMA descriptors must be aligned to their own size. */ + if (addr % sizeof(XlnxZDMADescr)) { + qemu_log_mask(LOG_GUEST_ERROR, + "zdma: unaligned descriptor at %" PRIx64, + addr); + memset(buf, 0xdeadbeef, sizeof(XlnxZDMADescr)); + s->error =3D true; + return false; + } + + address_space_rw(s->dma_as, addr, s->attr, + buf, sizeof(XlnxZDMADescr), false); + return true; +} + +static void zdma_load_src_descriptor(XlnxZDMA *s) +{ + uint64_t src_addr; + unsigned int ptype =3D ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_= TYPE); + + if (ptype =3D=3D PT_REG) { + memcpy(&s->dsc_src, &s->regs[R_ZDMA_CH_SRC_DSCR_WORD0], + sizeof(s->dsc_src)); + return; + } + + src_addr =3D zdma_get_regaddr64(s, R_ZDMA_CH_SRC_CUR_DSCR_LSB); + + if (!zdma_load_descriptor(s, src_addr, &s->dsc_src)) { + ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, AXI_RD_SRC_DSCR, true); + } +} + +static void zdma_load_dst_descriptor(XlnxZDMA *s) +{ + uint64_t dst_addr; + unsigned int ptype =3D ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_= TYPE); + + if (ptype =3D=3D PT_REG) { + memcpy(&s->dsc_dst, &s->regs[R_ZDMA_CH_DST_DSCR_WORD0], + sizeof(s->dsc_dst)); + return; + } + + dst_addr =3D zdma_get_regaddr64(s, R_ZDMA_CH_DST_CUR_DSCR_LSB); + + if (!zdma_load_descriptor(s, dst_addr, &s->dsc_dst)) { + ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, AXI_RD_DST_DSCR, true); + } +} + +static uint64_t zdma_update_descr_addr(XlnxZDMA *s, bool type, + unsigned int basereg) +{ + uint64_t addr, next; + + if (type =3D=3D DTYPE_LINEAR) { + next =3D zdma_get_regaddr64(s, basereg); + next +=3D sizeof(s->dsc_dst); + zdma_put_regaddr64(s, basereg, next); + } else { + addr =3D zdma_get_regaddr64(s, basereg); + addr +=3D sizeof(s->dsc_dst); + address_space_rw(s->dma_as, addr, s->attr, (void *) &next, 8, fals= e); + zdma_put_regaddr64(s, basereg, next); + } + return next; +} + +static void zdma_write_dst(XlnxZDMA *s, uint8_t *buf, uint32_t len) +{ + uint32_t dst_size, dlen; + bool dst_intr, dst_type; + unsigned int ptype =3D ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_= TYPE); + unsigned int rw_mode =3D ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, MODE= ); + unsigned int burst_type =3D ARRAY_FIELD_EX32(s->regs, ZDMA_CH_DATA_ATT= R, + AWBURST); + + /* FIXED burst types are only supported in simple dma mode. */ + if (ptype !=3D PT_REG) { + burst_type =3D AXI_BURST_INCR; + } + + while (len) { + dst_size =3D FIELD_EX32(s->dsc_dst.words[2], ZDMA_CH_DST_DSCR_WORD= 2, + SIZE); + dst_type =3D FIELD_EX32(s->dsc_dst.words[3], ZDMA_CH_DST_DSCR_WORD= 3, + TYPE); + if (dst_size =3D=3D 0 && ptype =3D=3D PT_MEM) { + uint64_t next; + next =3D zdma_update_descr_addr(s, dst_type, + R_ZDMA_CH_DST_CUR_DSCR_LSB); + zdma_load_descriptor(s, next, &s->dsc_dst); + dst_size =3D FIELD_EX32(s->dsc_dst.words[2], ZDMA_CH_DST_DSCR_= WORD2, + SIZE); + dst_type =3D FIELD_EX32(s->dsc_dst.words[3], ZDMA_CH_DST_DSCR_= WORD3, + TYPE); + } + + /* Match what hardware does by ignoring the dst_size and only using + * the src size for Simple register mode. */ + if (ptype =3D=3D PT_REG && rw_mode !=3D RW_MODE_WO) { + dst_size =3D len; + } + + dst_intr =3D FIELD_EX32(s->dsc_dst.words[3], ZDMA_CH_DST_DSCR_WORD= 3, + INTR); + + dlen =3D len > dst_size ? dst_size : len; + if (burst_type =3D=3D AXI_BURST_FIXED) { + if (dlen > (s->cfg.bus_width / 8)) { + dlen =3D s->cfg.bus_width / 8; + } + } + + address_space_rw(s->dma_as, s->dsc_dst.addr, s->attr, buf, dlen, + true); + if (burst_type =3D=3D AXI_BURST_INCR) { + s->dsc_dst.addr +=3D dlen; + } + dst_size -=3D dlen; + buf +=3D dlen; + len -=3D dlen; + + if (dst_size =3D=3D 0 && dst_intr) { + zdma_dst_done(s); + } + + /* Write back to buffered descriptor. */ + s->dsc_dst.words[2] =3D FIELD_DP32(s->dsc_dst.words[2], + ZDMA_CH_DST_DSCR_WORD2, + SIZE, + dst_size); + } +} + +static void zdma_process_descr(XlnxZDMA *s) +{ + uint64_t src_addr; + uint32_t src_size, len; + unsigned int src_cmd; + bool src_intr, src_type; + unsigned int ptype =3D ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_= TYPE); + unsigned int rw_mode =3D ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, MODE= ); + unsigned int burst_type =3D ARRAY_FIELD_EX32(s->regs, ZDMA_CH_DATA_ATT= R, + ARBURST); + + src_addr =3D s->dsc_src.addr; + src_size =3D FIELD_EX32(s->dsc_src.words[2], ZDMA_CH_SRC_DSCR_WORD2, S= IZE); + src_cmd =3D FIELD_EX32(s->dsc_src.words[3], ZDMA_CH_SRC_DSCR_WORD3, CM= D); + src_type =3D FIELD_EX32(s->dsc_src.words[3], ZDMA_CH_SRC_DSCR_WORD3, T= YPE); + src_intr =3D FIELD_EX32(s->dsc_src.words[3], ZDMA_CH_SRC_DSCR_WORD3, I= NTR); + + /* FIXED burst types and non-rw modes are only supported in + * simple dma mode. + */ + if (ptype !=3D PT_REG) { + if (rw_mode !=3D RW_MODE_RW) { + qemu_log_mask(LOG_GUEST_ERROR, + "zDMA: rw-mode=3D%d but not simple DMA mode.\n", + rw_mode); + } + if (burst_type !=3D AXI_BURST_INCR) { + qemu_log_mask(LOG_GUEST_ERROR, + "zDMA: burst_type=3D%d but not simple DMA mode.\= n", + burst_type); + } + burst_type =3D AXI_BURST_INCR; + rw_mode =3D RW_MODE_RW; + } + + if (rw_mode =3D=3D RW_MODE_WO) { + /* In Simple DMA Write-Only, we need to push DST size bytes + * regardless of what SRC size is set to. */ + src_size =3D FIELD_EX32(s->dsc_dst.words[2], ZDMA_CH_DST_DSCR_WORD= 2, + SIZE); + memcpy(s->buf, &s->regs[R_ZDMA_CH_WR_ONLY_WORD0], s->cfg.bus_width= / 8); + } + + while (src_size) { + len =3D src_size > ARRAY_SIZE(s->buf) ? ARRAY_SIZE(s->buf) : src_s= ize; + if (burst_type =3D=3D AXI_BURST_FIXED) { + if (len > (s->cfg.bus_width / 8)) { + len =3D s->cfg.bus_width / 8; + } + } + + if (rw_mode =3D=3D RW_MODE_WO) { + if (len > s->cfg.bus_width / 8) { + len =3D s->cfg.bus_width / 8; + } + } else { + address_space_rw(s->dma_as, src_addr, s->attr, s->buf, len, + false); + if (burst_type =3D=3D AXI_BURST_INCR) { + src_addr +=3D len; + } + } + + if (rw_mode !=3D RW_MODE_RO) { + zdma_write_dst(s, s->buf, len); + } + + s->regs[R_ZDMA_CH_TOTAL_BYTE] +=3D len; + src_size -=3D len; + } + + ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, DMA_DONE, true); + + if (src_intr) { + zdma_src_done(s); + } + + /* Load next descriptor. */ + if (ptype =3D=3D PT_REG || src_cmd =3D=3D CMD_STOP) { + ARRAY_FIELD_DP32(s->regs, ZDMA_CH_CTRL2, EN, 0); + zdma_set_state(s, DISABLED); + return; + } + + if (src_cmd =3D=3D CMD_HALT) { + zdma_set_state(s, PAUSED); + ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, DMA_PAUSE, 1); + zdma_ch_imr_update_irq(s); + return; + } + + zdma_update_descr_addr(s, src_type, R_ZDMA_CH_SRC_CUR_DSCR_LSB); +} + +static void zdma_run(XlnxZDMA *s) +{ + while (s->state =3D=3D ENABLED && !s->error) { + zdma_load_src_descriptor(s); + + if (s->error) { + zdma_set_state(s, DISABLED); + } else { + zdma_process_descr(s); + } + } + + zdma_ch_imr_update_irq(s); +} + +static void zdma_update_descr_addr_from_start(XlnxZDMA *s) +{ + uint64_t src_addr, dst_addr; + + src_addr =3D zdma_get_regaddr64(s, R_ZDMA_CH_SRC_START_LSB); + zdma_put_regaddr64(s, R_ZDMA_CH_SRC_CUR_DSCR_LSB, src_addr); + dst_addr =3D zdma_get_regaddr64(s, R_ZDMA_CH_DST_START_LSB); + zdma_put_regaddr64(s, R_ZDMA_CH_DST_CUR_DSCR_LSB, dst_addr); + zdma_load_dst_descriptor(s); +} + +static void zdma_ch_ctrlx_postw(RegisterInfo *reg, uint64_t val64) +{ + XlnxZDMA *s =3D XLNX_ZDMA(reg->opaque); + + if (ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL2, EN)) { + s->error =3D false; + + if (s->state =3D=3D PAUSED && + ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, CONT)) { + if (ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, CONT_ADDR) =3D=3D= 1) { + zdma_update_descr_addr_from_start(s); + } else { + bool src_type =3D FIELD_EX32(s->dsc_src.words[3], + ZDMA_CH_SRC_DSCR_WORD3, TYPE); + zdma_update_descr_addr(s, src_type, + R_ZDMA_CH_SRC_CUR_DSCR_LSB); + } + ARRAY_FIELD_DP32(s->regs, ZDMA_CH_CTRL0, CONT, false); + zdma_set_state(s, ENABLED); + } else if (s->state =3D=3D DISABLED) { + zdma_update_descr_addr_from_start(s); + zdma_set_state(s, ENABLED); + } + } else { + /* Leave Paused state? */ + if (s->state =3D=3D PAUSED && + ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, CONT)) { + zdma_set_state(s, DISABLED); + } + } + + zdma_run(s); +} + +static RegisterAccessInfo zdma_regs_info[] =3D { + { .name =3D "ZDMA_ERR_CTRL", .addr =3D A_ZDMA_ERR_CTRL, + .rsvd =3D 0xfffffffe, + },{ .name =3D "ZDMA_CH_ISR", .addr =3D A_ZDMA_CH_ISR, + .rsvd =3D 0xfffff000, + .w1c =3D 0xfff, + .post_write =3D zdma_ch_isr_postw, + },{ .name =3D "ZDMA_CH_IMR", .addr =3D A_ZDMA_CH_IMR, + .reset =3D 0xfff, + .rsvd =3D 0xfffff000, + .ro =3D 0xfff, + },{ .name =3D "ZDMA_CH_IEN", .addr =3D A_ZDMA_CH_IEN, + .rsvd =3D 0xfffff000, + .pre_write =3D zdma_ch_ien_prew, + },{ .name =3D "ZDMA_CH_IDS", .addr =3D A_ZDMA_CH_IDS, + .rsvd =3D 0xfffff000, + .pre_write =3D zdma_ch_ids_prew, + },{ .name =3D "ZDMA_CH_CTRL0", .addr =3D A_ZDMA_CH_CTRL0, + .reset =3D 0x80, + .rsvd =3D 0xffffff01, + .post_write =3D zdma_ch_ctrlx_postw, + },{ .name =3D "ZDMA_CH_CTRL1", .addr =3D A_ZDMA_CH_CTRL1, + .reset =3D 0x3ff, + .rsvd =3D 0xfffffc00, + },{ .name =3D "ZDMA_CH_FCI", .addr =3D A_ZDMA_CH_FCI, + .rsvd =3D 0xffffffc0, + },{ .name =3D "ZDMA_CH_STATUS", .addr =3D A_ZDMA_CH_STATUS, + .rsvd =3D 0xfffffffc, + .ro =3D 0x3, + },{ .name =3D "ZDMA_CH_DATA_ATTR", .addr =3D A_ZDMA_CH_DATA_ATTR, + .reset =3D 0x483d20f, + .rsvd =3D 0xf0000000, + },{ .name =3D "ZDMA_CH_DSCR_ATTR", .addr =3D A_ZDMA_CH_DSCR_ATTR, + .rsvd =3D 0xfffffe00, + },{ .name =3D "ZDMA_CH_SRC_DSCR_WORD0", .addr =3D A_ZDMA_CH_SRC_DSCR_= WORD0, + },{ .name =3D "ZDMA_CH_SRC_DSCR_WORD1", .addr =3D A_ZDMA_CH_SRC_DSCR_= WORD1, + .rsvd =3D 0xfffe0000, + },{ .name =3D "ZDMA_CH_SRC_DSCR_WORD2", .addr =3D A_ZDMA_CH_SRC_DSCR_= WORD2, + .rsvd =3D 0xc0000000, + },{ .name =3D "ZDMA_CH_SRC_DSCR_WORD3", .addr =3D A_ZDMA_CH_SRC_DSCR_= WORD3, + .rsvd =3D 0xffffffe0, + },{ .name =3D "ZDMA_CH_DST_DSCR_WORD0", .addr =3D A_ZDMA_CH_DST_DSCR_= WORD0, + },{ .name =3D "ZDMA_CH_DST_DSCR_WORD1", .addr =3D A_ZDMA_CH_DST_DSCR_= WORD1, + .rsvd =3D 0xfffe0000, + },{ .name =3D "ZDMA_CH_DST_DSCR_WORD2", .addr =3D A_ZDMA_CH_DST_DSCR_= WORD2, + .rsvd =3D 0xc0000000, + },{ .name =3D "ZDMA_CH_DST_DSCR_WORD3", .addr =3D A_ZDMA_CH_DST_DSCR_= WORD3, + .rsvd =3D 0xfffffffa, + },{ .name =3D "ZDMA_CH_WR_ONLY_WORD0", .addr =3D A_ZDMA_CH_WR_ONLY_WO= RD0, + },{ .name =3D "ZDMA_CH_WR_ONLY_WORD1", .addr =3D A_ZDMA_CH_WR_ONLY_WO= RD1, + },{ .name =3D "ZDMA_CH_WR_ONLY_WORD2", .addr =3D A_ZDMA_CH_WR_ONLY_WO= RD2, + },{ .name =3D "ZDMA_CH_WR_ONLY_WORD3", .addr =3D A_ZDMA_CH_WR_ONLY_WO= RD3, + },{ .name =3D "ZDMA_CH_SRC_START_LSB", .addr =3D A_ZDMA_CH_SRC_START_= LSB, + },{ .name =3D "ZDMA_CH_SRC_START_MSB", .addr =3D A_ZDMA_CH_SRC_START_= MSB, + .rsvd =3D 0xfffe0000, + },{ .name =3D "ZDMA_CH_DST_START_LSB", .addr =3D A_ZDMA_CH_DST_START_= LSB, + },{ .name =3D "ZDMA_CH_DST_START_MSB", .addr =3D A_ZDMA_CH_DST_START_= MSB, + .rsvd =3D 0xfffe0000, + },{ .name =3D "ZDMA_CH_SRC_CUR_PYLD_LSB", .addr =3D A_ZDMA_CH_SRC_CUR= _PYLD_LSB, + .ro =3D 0xffffffff, + },{ .name =3D "ZDMA_CH_SRC_CUR_PYLD_MSB", .addr =3D A_ZDMA_CH_SRC_CUR= _PYLD_MSB, + .rsvd =3D 0xfffe0000, + .ro =3D 0x1ffff, + },{ .name =3D "ZDMA_CH_DST_CUR_PYLD_LSB", .addr =3D A_ZDMA_CH_DST_CUR= _PYLD_LSB, + .ro =3D 0xffffffff, + },{ .name =3D "ZDMA_CH_DST_CUR_PYLD_MSB", .addr =3D A_ZDMA_CH_DST_CUR= _PYLD_MSB, + .rsvd =3D 0xfffe0000, + .ro =3D 0x1ffff, + },{ .name =3D "ZDMA_CH_SRC_CUR_DSCR_LSB", .addr =3D A_ZDMA_CH_SRC_CUR= _DSCR_LSB, + .ro =3D 0xffffffff, + },{ .name =3D "ZDMA_CH_SRC_CUR_DSCR_MSB", .addr =3D A_ZDMA_CH_SRC_CUR= _DSCR_MSB, + .rsvd =3D 0xfffe0000, + .ro =3D 0x1ffff, + },{ .name =3D "ZDMA_CH_DST_CUR_DSCR_LSB", .addr =3D A_ZDMA_CH_DST_CUR= _DSCR_LSB, + .ro =3D 0xffffffff, + },{ .name =3D "ZDMA_CH_DST_CUR_DSCR_MSB", .addr =3D A_ZDMA_CH_DST_CUR= _DSCR_MSB, + .rsvd =3D 0xfffe0000, + .ro =3D 0x1ffff, + },{ .name =3D "ZDMA_CH_TOTAL_BYTE", .addr =3D A_ZDMA_CH_TOTAL_BYTE, + .w1c =3D 0xffffffff, + },{ .name =3D "ZDMA_CH_RATE_CNTL", .addr =3D A_ZDMA_CH_RATE_CNTL, + .rsvd =3D 0xfffff000, + },{ .name =3D "ZDMA_CH_IRQ_SRC_ACCT", .addr =3D A_ZDMA_CH_IRQ_SRC_ACC= T, + .rsvd =3D 0xffffff00, + .ro =3D 0xff, + .cor =3D 0xff, + },{ .name =3D "ZDMA_CH_IRQ_DST_ACCT", .addr =3D A_ZDMA_CH_IRQ_DST_ACC= T, + .rsvd =3D 0xffffff00, + .ro =3D 0xff, + .cor =3D 0xff, + },{ .name =3D "ZDMA_CH_DBG0", .addr =3D A_ZDMA_CH_DBG0, + .rsvd =3D 0xfffffe00, + .ro =3D 0x1ff, + },{ .name =3D "ZDMA_CH_DBG1", .addr =3D A_ZDMA_CH_DBG1, + .rsvd =3D 0xfffffe00, + .ro =3D 0x1ff, + },{ .name =3D "ZDMA_CH_CTRL2", .addr =3D A_ZDMA_CH_CTRL2, + .rsvd =3D 0xfffffffe, + .post_write =3D zdma_ch_ctrlx_postw, + } +}; + +static void zdma_reset(DeviceState *dev) +{ + XlnxZDMA *s =3D XLNX_ZDMA(dev); + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(s->regs_info); ++i) { + register_reset(&s->regs_info[i]); + } + + zdma_ch_imr_update_irq(s); +} + +static uint64_t zdma_read(void *opaque, hwaddr addr, unsigned size) +{ + XlnxZDMA *s =3D XLNX_ZDMA(opaque); + RegisterInfo *r =3D &s->regs_info[addr / 4]; + + if (!r->data) { + qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n", + object_get_canonical_path(OBJECT(s)), + addr); + ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true); + zdma_ch_imr_update_irq(s); + return 0; + } + return register_read(r, ~0, NULL, false); +} + +static void zdma_write(void *opaque, hwaddr addr, uint64_t value, + unsigned size) +{ + XlnxZDMA *s =3D XLNX_ZDMA(opaque); + RegisterInfo *r =3D &s->regs_info[addr / 4]; + + if (!r->data) { + qemu_log("%s: Decode error: write to %" HWADDR_PRIx "=3D%" PRIx64 = "\n", + object_get_canonical_path(OBJECT(s)), + addr, value); + ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true); + zdma_ch_imr_update_irq(s); + return; + } + register_write(r, value, ~0, NULL, false); +} + +static const MemoryRegionOps zdma_ops =3D { + .read =3D zdma_read, + .write =3D zdma_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +static void zdma_realize(DeviceState *dev, Error **errp) +{ + XlnxZDMA *s =3D XLNX_ZDMA(dev); + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(zdma_regs_info); ++i) { + RegisterInfo *r =3D &s->regs_info[zdma_regs_info[i].addr / 4]; + + *r =3D (RegisterInfo) { + .data =3D (uint8_t *)&s->regs[ + zdma_regs_info[i].addr / 4], + .data_size =3D sizeof(uint32_t), + .access =3D &zdma_regs_info[i], + .opaque =3D s, + }; + } + + if (s->dma_mr) { + s->dma_as =3D g_malloc0(sizeof(AddressSpace)); + address_space_init(s->dma_as, s->dma_mr, NULL); + } else { + s->dma_as =3D &address_space_memory; + } + s->attr =3D MEMTXATTRS_UNSPECIFIED; +} + +static void zdma_init(Object *obj) +{ + XlnxZDMA *s =3D XLNX_ZDMA(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->iomem, obj, &zdma_ops, s, + TYPE_XLNX_ZDMA, ZDMA_R_MAX * 4); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq_zdma_ch_imr); + + object_property_add_link(obj, "dma", TYPE_MEMORY_REGION, + (Object **)&s->dma_mr, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_UNREF_ON_RELEASE, + &error_abort); +} + +static const VMStateDescription vmstate_zdma =3D { + .name =3D TYPE_XLNX_ZDMA, + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, XlnxZDMA, ZDMA_R_MAX), + VMSTATE_UINT32(state, XlnxZDMA), + VMSTATE_UINT32_ARRAY(dsc_src.words, XlnxZDMA, 4), + VMSTATE_UINT32_ARRAY(dsc_dst.words, XlnxZDMA, 4), + VMSTATE_END_OF_LIST(), + } +}; + +static Property zdma_props[] =3D { + DEFINE_PROP_UINT32("bus-width", XlnxZDMA, cfg.bus_width, 64), + DEFINE_PROP_END_OF_LIST(), +}; + +static void zdma_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->reset =3D zdma_reset; + dc->realize =3D zdma_realize; + dc->props =3D zdma_props; + dc->vmsd =3D &vmstate_zdma; +} + +static const TypeInfo zdma_info =3D { + .name =3D TYPE_XLNX_ZDMA, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(XlnxZDMA), + .class_init =3D zdma_class_init, + .instance_init =3D zdma_init, +}; + +static void zdma_register_types(void) +{ + type_register_static(&zdma_info); +} + +type_init(zdma_register_types) --=20 2.17.0