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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5G3npuaUGGTDzTHF/+K7xrkhnr6K2y2tGIFOkbvCuNU=; b=W2ghgSfy1B8vH/XmjV6P0qUurM7NHKpIx837RLP1FLDRFS3vWxFjD/3pVCjci1uJkN QTZ1Fh8JS16UkUz8//Fybydtqz+DuGSizfzPjE+39966KxvUyK6VHYzPMWgnDoTAC7mh sO7/GHTpUJkcRlSlRk9PySqiHrabB7Tzh6Bek= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5G3npuaUGGTDzTHF/+K7xrkhnr6K2y2tGIFOkbvCuNU=; b=DC/O4oMRhFQrf9bshRaSSZBmEyt7mG71F+xx5c9N2NMZ98b/PLdZEqDuKxUOE14DMK AtZOj08vOlBH6wAf+h/NEAeovcTIMPoxYGghp95+2uY7s03xro+Jesi/+YMxYOJ2C7on uaFCiPo3rQGvZyhzZA1GwsiGMxJHRx8n5szzc6g40/Th8k1F8j+SRAK4d1yduYqtsVqF biybsgskNyccu1iaPLPXb0Jct40IEz6QqwZReJLcxVDFHdBEolSXjwdWFKPcUi/ihMHx xzIbJEeU2lGZg1tFUA0b68qxx2AXPkMDBANtjzjTWYL+HZevygZ9aRM2th2dfM6sLmfb 9hsQ== X-Gm-Message-State: ALKqPwfYKXig4MpKl7IhS0yZ09+sFbsO9RMnowFL3+wd2306S975h/Y7 Wirgjka9lDgtK2nBpOP5F0PSDKBOYH4= X-Google-Smtp-Source: AB8JxZpPTrW7EE5N5PH62ow2An2U3fSnsgeb3J/fSuf77v7xZJiuYFIBV8hLPH9FciLsdoS9nn3MxQ== X-Received: by 2002:a62:6756:: with SMTP id b83-v6mr2786961pfc.76.1526509844114; Wed, 16 May 2018 15:30:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:30:04 -0700 Message-Id: <20180516223007.10256-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v3-a 24/27] target/arm: Implement SVE Integer Wide Immediate - Predicated Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 10 ++++ target/arm/sve_helper.c | 108 +++++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 88 ++++++++++++++++++++++++++++++ target/arm/sve.decode | 19 ++++++- 4 files changed, 224 insertions(+), 1 deletion(-) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 2831e1643b..79493ab647 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -404,6 +404,16 @@ DEF_HELPER_FLAGS_4(sve_uqaddi_s, TCG_CALL_NO_RWG, void= , ptr, ptr, s64, i32) DEF_HELPER_FLAGS_4(sve_uqaddi_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) DEF_HELPER_FLAGS_4(sve_uqsubi_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) =20 +DEF_HELPER_FLAGS_5(sve_cpy_m_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i64,= i32) +DEF_HELPER_FLAGS_5(sve_cpy_m_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i64,= i32) +DEF_HELPER_FLAGS_5(sve_cpy_m_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i64,= i32) +DEF_HELPER_FLAGS_5(sve_cpy_m_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i64,= i32) + +DEF_HELPER_FLAGS_4(sve_cpy_z_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(sve_cpy_z_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(sve_cpy_z_s, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(sve_cpy_z_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) + DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 979aa5c409..8c7ea989b1 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -1371,3 +1371,111 @@ void HELPER(sve_uqsubi_d)(void *d, void *a, uint64_= t b, uint32_t desc) *(uint64_t *)(d + i) =3D (ai < b ? 0 : ai - b); } } + +/* Two operand predicated copy immediate with merge. All valid immediates + * can fit within 17 signed bits in the simd_data field. + */ +void HELPER(sve_cpy_m_b)(void *vd, void *vn, void *vg, + uint64_t mm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t *d =3D vd, *n =3D vn; + uint8_t *pg =3D vg; + + mm =3D dup_const(MO_8, mm); + for (i =3D 0; i < opr_sz; i +=3D 1) { + uint64_t nn =3D n[i]; + uint64_t pp =3D expand_pred_b(pg[H1(i)]); + d[i] =3D (mm & pp) | (nn & ~pp); + } +} + +void HELPER(sve_cpy_m_h)(void *vd, void *vn, void *vg, + uint64_t mm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t *d =3D vd, *n =3D vn; + uint8_t *pg =3D vg; + + mm =3D dup_const(MO_16, mm); + for (i =3D 0; i < opr_sz; i +=3D 1) { + uint64_t nn =3D n[i]; + uint64_t pp =3D expand_pred_h(pg[H1(i)]); + d[i] =3D (mm & pp) | (nn & ~pp); + } +} + +void HELPER(sve_cpy_m_s)(void *vd, void *vn, void *vg, + uint64_t mm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t *d =3D vd, *n =3D vn; + uint8_t *pg =3D vg; + + mm =3D dup_const(MO_32, mm); + for (i =3D 0; i < opr_sz; i +=3D 1) { + uint64_t nn =3D n[i]; + uint64_t pp =3D expand_pred_s(pg[H1(i)]); + d[i] =3D (mm & pp) | (nn & ~pp); + } +} + +void HELPER(sve_cpy_m_d)(void *vd, void *vn, void *vg, + uint64_t mm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t *d =3D vd, *n =3D vn; + uint8_t *pg =3D vg; + + for (i =3D 0; i < opr_sz; i +=3D 1) { + uint64_t nn =3D n[i]; + d[i] =3D (pg[H1(i)] & 1 ? mm : nn); + } +} + +void HELPER(sve_cpy_z_b)(void *vd, void *vg, uint64_t val, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t *d =3D vd; + uint8_t *pg =3D vg; + + val =3D dup_const(MO_8, val); + for (i =3D 0; i < opr_sz; i +=3D 1) { + d[i] =3D val & expand_pred_b(pg[H1(i)]); + } +} + +void HELPER(sve_cpy_z_h)(void *vd, void *vg, uint64_t val, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t *d =3D vd; + uint8_t *pg =3D vg; + + val =3D dup_const(MO_16, val); + for (i =3D 0; i < opr_sz; i +=3D 1) { + d[i] =3D val & expand_pred_h(pg[H1(i)]); + } +} + +void HELPER(sve_cpy_z_s)(void *vd, void *vg, uint64_t val, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t *d =3D vd; + uint8_t *pg =3D vg; + + val =3D dup_const(MO_32, val); + for (i =3D 0; i < opr_sz; i +=3D 1) { + d[i] =3D val & expand_pred_s(pg[H1(i)]); + } +} + +void HELPER(sve_cpy_z_d)(void *vd, void *vg, uint64_t val, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t *d =3D vd; + uint8_t *pg =3D vg; + + for (i =3D 0; i < opr_sz; i +=3D 1) { + d[i] =3D (pg[H1(i)] & 1 ? val : 0); + } +} diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 9d7c18c48d..9bdd61ff84 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -62,6 +62,12 @@ static inline int plus1(int x) return x + 1; } =20 +/* The SH bit is in bit 8. Extract the low 8 and shift. */ +static inline int expand_imm_sh8s(int x) +{ + return (int8_t)x << (x & 0x100 ? 8 : 0); +} + /* * Include the generated decoder. */ @@ -1834,6 +1840,88 @@ static bool trans_DUPM(DisasContext *s, arg_DUPM *a,= uint32_t insn) return true; } =20 +/* + *** SVE Integer Wide Immediate - Predicated Group + */ + +/* Implement all merging copies. This is used for CPY (immediate), + * FCPY, CPY (scalar), CPY (SIMD&FP scalar). + */ +static void do_cpy_m(DisasContext *s, int esz, int rd, int rn, int pg, + TCGv_i64 val) +{ + typedef void gen_cpy(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_i32); + static gen_cpy * const fns[4] =3D { + gen_helper_sve_cpy_m_b, gen_helper_sve_cpy_m_h, + gen_helper_sve_cpy_m_s, gen_helper_sve_cpy_m_d, + }; + unsigned vsz =3D vec_full_reg_size(s); + TCGv_i32 desc =3D tcg_const_i32(simd_desc(vsz, vsz, 0)); + TCGv_ptr t_zd =3D tcg_temp_new_ptr(); + TCGv_ptr t_zn =3D tcg_temp_new_ptr(); + TCGv_ptr t_pg =3D tcg_temp_new_ptr(); + + tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, rd)); + tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, rn)); + tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); + + fns[esz](t_zd, t_zn, t_pg, val, desc); + + tcg_temp_free_ptr(t_zd); + tcg_temp_free_ptr(t_zn); + tcg_temp_free_ptr(t_pg); + tcg_temp_free_i32(desc); +} + +static bool trans_FCPY(DisasContext *s, arg_FCPY *a, uint32_t insn) +{ + if (a->esz =3D=3D 0) { + return false; + } + if (sve_access_check(s)) { + /* Decode the VFP immediate. */ + uint64_t imm =3D vfp_expand_imm(a->esz, a->imm); + TCGv_i64 t_imm =3D tcg_const_i64(imm); + do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, t_imm); + tcg_temp_free_i64(t_imm); + } + return true; +} + +static bool trans_CPY_m_i(DisasContext *s, arg_rpri_esz *a, uint32_t insn) +{ + if (a->esz =3D=3D 0 && extract32(insn, 13, 1)) { + return false; + } + if (sve_access_check(s)) { + TCGv_i64 t_imm =3D tcg_const_i64(a->imm); + do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, t_imm); + tcg_temp_free_i64(t_imm); + } + return true; +} + +static bool trans_CPY_z_i(DisasContext *s, arg_CPY_z_i *a, uint32_t insn) +{ + static gen_helper_gvec_2i * const fns[4] =3D { + gen_helper_sve_cpy_z_b, gen_helper_sve_cpy_z_h, + gen_helper_sve_cpy_z_s, gen_helper_sve_cpy_z_d, + }; + + if (a->esz =3D=3D 0 && extract32(insn, 13, 1)) { + return false; + } + if (sve_access_check(s)) { + unsigned vsz =3D vec_full_reg_size(s); + TCGv_i64 t_imm =3D tcg_const_i64(a->imm); + tcg_gen_gvec_2i_ool(vec_full_reg_offset(s, a->rd), + pred_full_reg_offset(s, a->pg), + t_imm, vsz, vsz, 0, fns[a->esz]); + tcg_temp_free_i64(t_imm); + } + return true; +} + /* *** SVE Memory - 32-bit Gather and Unsized Contiguous Group */ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index a3277a0d21..4ee7c78cda 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -22,7 +22,7 @@ ########################################################################### # Named fields. These are primarily for disjoint fields. =20 -%imm4_16_p1 16:4 !function=3Dplus1 +%imm4_16_p1 16:4 !function=3Dplus1 %imm6_22_5 22:1 5:5 %imm9_16_10 16:s6 10:3 =20 @@ -38,6 +38,9 @@ %tszimm16_shr 22:2 16:5 !function=3Dtszimm_shr %tszimm16_shl 22:2 16:5 !function=3Dtszimm_shl =20 +# Signed 8-bit immediate, optionally shifted left by 8. +%sh8_i8s 5:9 !function=3Dexpand_imm_sh8s + # Either a copy of rd (at bit 0), or a different source # as propagated via the MOVPRFX instruction. %reg_movprfx 0:5 @@ -112,6 +115,11 @@ @rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \ &rri_esz esz=3D%tszimm16_esz =20 +# Two register operand, one immediate operand, with 4-bit predicate. +# User must fill in imm. +@rdn_pg4 ........ esz:2 .. pg:4 ... ........ rd:5 \ + &rpri_esz rn=3D%reg_movprfx + # Two register operand, one encoded bitmask. @rdn_dbm ........ .. .... dbm:13 rd:5 \ &rr_dbm rn=3D%reg_movprfx @@ -345,6 +353,15 @@ AND_zzi 00000101 10 0000 ............. ..... = @rdn_dbm # SVE broadcast bitmask immediate DUPM 00000101 11 0000 dbm:13 rd:5 =20 +### SVE Integer Wide Immediate - Predicated Group + +# SVE copy floating-point immediate (predicated) +FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4 + +# SVE copy integer immediate (predicated) +CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=3D%= sh8_i8s +CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=3D%= sh8_i8s + ### SVE Predicate Logical Operations Group =20 # SVE predicate logical operations --=20 2.17.0