From nobody Wed Oct 29 22:55:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526510157624878.8504221629408; Wed, 16 May 2018 15:35:57 -0700 (PDT) Received: from localhost ([::1]:44794 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ51U-0002th-8x for importer@patchew.org; Wed, 16 May 2018 18:35:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40887) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4w3-0007Qv-EK for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ4w1-0007IY-Ac for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:15 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:40453) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ4w1-0007Hh-22 for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:13 -0400 Received: by mail-pf0-x242.google.com with SMTP id f189-v6so1051763pfa.7 for ; Wed, 16 May 2018 15:30:12 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=h1F3hxZVW/UCRB1pWg8UE1QkjgeJcS1QB+zq1cm2Y6k=; b=h63W1Eaele51oYhfEp9kDdNxkeNAp+wlzBSBYkP7dWVvmbm3+hume2WEGWUBp5/J6p XjC11okoT1MTLqA2zm1fLhAf7XtcEHJ8dKAAgSE9S0KqIKEKAXwTC+zUf/HRPhXMhN1h tKRSHbG2L2Af39kmrKwVSxYC6QEsDoWNyVhTc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h1F3hxZVW/UCRB1pWg8UE1QkjgeJcS1QB+zq1cm2Y6k=; b=f2eqOL58sls6lMgd63bAqC+gU0FUd1Dcnz2IWlwMeZ8IAGsmb73SKzVMBBuagcA/Jc C7qBbdzwxUpb0uLw3CDo23SnKVffxEMxt2AiAf+YAWHC4L74RF9HUnq32bK4V6nGgieO WclmMJqRB+o2UZZDznCGJGyKTLjMIy3PcLIBP7eeSWNh13FJwgzqMtfh17IPePns6bXk xl2b6CEJEZXDm3xNSG7Dvi6DS2aI5hZNdNj78HVD3bavUaMhlFzKuuuNgyqG/WP8b1tQ AypEHP9/15Df0dXIFlzTKmSpPzYQ2u61P1QP4q8AdB10V8wqmZbRI3poCeXyeAUlgHrP 2L7A== X-Gm-Message-State: ALKqPwc8a5JzDjPu3fNfdtNUvKEUA3Nk16V2e46KC5bvK6OkN6d4gOq0 JoHSQp4/dP7qOK4SEV57IRIuPuxE4Qc= X-Google-Smtp-Source: AB8JxZrngDA76j98bwC0WFBD0WZrhN8XcwQrddrT69s73yZ9SFMHbts6JczmKsI/92IVRt+AMM0fNA== X-Received: by 2002:a62:4544:: with SMTP id s65-v6mr2772996pfa.150.1526509811500; Wed, 16 May 2018 15:30:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:29:41 -0700 Message-Id: <20180516223007.10256-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v3-a 01/27] target/arm: Introduce translate-a64.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Move some stuff that will be common to both translate-a64.c and translate-sve.c. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Move GVecGen2Fn, GVecGen2iFn, GVecGen3Fn too. --- target/arm/translate-a64.h | 118 +++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 112 +++++------------------------------ 2 files changed, 133 insertions(+), 97 deletions(-) create mode 100644 target/arm/translate-a64.h diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h new file mode 100644 index 0000000000..dd9c09f89b --- /dev/null +++ b/target/arm/translate-a64.h @@ -0,0 +1,118 @@ +/* + * AArch64 translation, common definitions. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef TARGET_ARM_TRANSLATE_A64_H +#define TARGET_ARM_TRANSLATE_A64_H + +void unallocated_encoding(DisasContext *s); + +#define unsupported_encoding(s, insn) \ + do { \ + qemu_log_mask(LOG_UNIMP, \ + "%s:%d: unsupported instruction encoding 0x%08x " \ + "at pc=3D%016" PRIx64 "\n", = \ + __FILE__, __LINE__, insn, s->pc - 4); \ + unallocated_encoding(s); \ + } while (0) + +TCGv_i64 new_tmp_a64(DisasContext *s); +TCGv_i64 new_tmp_a64_zero(DisasContext *s); +TCGv_i64 cpu_reg(DisasContext *s, int reg); +TCGv_i64 cpu_reg_sp(DisasContext *s, int reg); +TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf); +TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf); +void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v); +TCGv_ptr get_fpstatus_ptr(bool); +bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, + unsigned int imms, unsigned int immr); +uint64_t vfp_expand_imm(int size, uint8_t imm8); +bool sve_access_check(DisasContext *s); + +/* We should have at some point before trying to access an FP register + * done the necessary access check, so assert that + * (a) we did the check and + * (b) we didn't then just plough ahead anyway if it failed. + * Print the instruction pattern in the abort message so we can figure + * out what we need to fix if a user encounters this problem in the wild. + */ +static inline void assert_fp_access_checked(DisasContext *s) +{ +#ifdef CONFIG_DEBUG_TCG + if (unlikely(!s->fp_access_checked || s->fp_excp_el)) { + fprintf(stderr, "target-arm: FP access check missing for " + "instruction 0x%08x\n", s->insn); + abort(); + } +#endif +} + +/* Return the offset into CPUARMState of an element of specified + * size, 'element' places in from the least significant end of + * the FP/vector register Qn. + */ +static inline int vec_reg_offset(DisasContext *s, int regno, + int element, TCGMemOp size) +{ + int offs =3D 0; +#ifdef HOST_WORDS_BIGENDIAN + /* This is complicated slightly because vfp.zregs[n].d[0] is + * still the low half and vfp.zregs[n].d[1] the high half + * of the 128 bit vector, even on big endian systems. + * Calculate the offset assuming a fully bigendian 128 bits, + * then XOR to account for the order of the two 64 bit halves. + */ + offs +=3D (16 - ((element + 1) * (1 << size))); + offs ^=3D 8; +#else + offs +=3D element * (1 << size); +#endif + offs +=3D offsetof(CPUARMState, vfp.zregs[regno]); + assert_fp_access_checked(s); + return offs; +} + +/* Return the offset info CPUARMState of the "whole" vector register Qn. = */ +static inline int vec_full_reg_offset(DisasContext *s, int regno) +{ + assert_fp_access_checked(s); + return offsetof(CPUARMState, vfp.zregs[regno]); +} + +/* Return a newly allocated pointer to the vector register. */ +static inline TCGv_ptr vec_full_reg_ptr(DisasContext *s, int regno) +{ + TCGv_ptr ret =3D tcg_temp_new_ptr(); + tcg_gen_addi_ptr(ret, cpu_env, vec_full_reg_offset(s, regno)); + return ret; +} + +/* Return the byte size of the "whole" vector register, VL / 8. */ +static inline int vec_full_reg_size(DisasContext *s) +{ + return s->sve_len; +} + +bool disas_sve(DisasContext *, uint32_t); + +/* Note that the gvec expanders operate on offsets + sizes. */ +typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t); +typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t, + uint32_t, uint32_t); +typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t, + uint32_t, uint32_t, uint32_t); + +#endif /* TARGET_ARM_TRANSLATE_A64_H */ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a0b0c43d12..ace9d5063e 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -36,13 +36,13 @@ #include "exec/log.h" =20 #include "trace-tcg.h" +#include "translate-a64.h" =20 static TCGv_i64 cpu_X[32]; static TCGv_i64 cpu_pc; =20 /* Load/store exclusive handling */ static TCGv_i64 cpu_exclusive_high; -static TCGv_i64 cpu_reg(DisasContext *s, int reg); =20 static const char *regnames[] =3D { "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", @@ -86,13 +86,6 @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv= _i32); typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, TCGMemO= p); =20 -/* Note that the gvec expanders operate on offsets + sizes. */ -typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t); -typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t, - uint32_t, uint32_t); -typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t, - uint32_t, uint32_t, uint32_t); - /* initialize TCG globals. */ void a64_translate_init(void) { @@ -405,22 +398,13 @@ static inline void gen_goto_tb(DisasContext *s, int n= , uint64_t dest) } } =20 -static void unallocated_encoding(DisasContext *s) +void unallocated_encoding(DisasContext *s) { /* Unallocated and reserved encodings are uncategorized */ gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), default_exception_el(s)); } =20 -#define unsupported_encoding(s, insn) \ - do { \ - qemu_log_mask(LOG_UNIMP, \ - "%s:%d: unsupported instruction encoding 0x%08x " \ - "at pc=3D%016" PRIx64 "\n", = \ - __FILE__, __LINE__, insn, s->pc - 4); \ - unallocated_encoding(s); \ - } while (0) - static void init_tmp_a64_array(DisasContext *s) { #ifdef CONFIG_DEBUG_TCG @@ -438,13 +422,13 @@ static void free_tmp_a64(DisasContext *s) init_tmp_a64_array(s); } =20 -static TCGv_i64 new_tmp_a64(DisasContext *s) +TCGv_i64 new_tmp_a64(DisasContext *s) { assert(s->tmp_a64_count < TMP_A64_MAX); return s->tmp_a64[s->tmp_a64_count++] =3D tcg_temp_new_i64(); } =20 -static TCGv_i64 new_tmp_a64_zero(DisasContext *s) +TCGv_i64 new_tmp_a64_zero(DisasContext *s) { TCGv_i64 t =3D new_tmp_a64(s); tcg_gen_movi_i64(t, 0); @@ -466,7 +450,7 @@ static TCGv_i64 new_tmp_a64_zero(DisasContext *s) * to cpu_X[31] and ZR accesses to a temporary which can be discarded. * This is the point of the _sp forms. */ -static TCGv_i64 cpu_reg(DisasContext *s, int reg) +TCGv_i64 cpu_reg(DisasContext *s, int reg) { if (reg =3D=3D 31) { return new_tmp_a64_zero(s); @@ -476,7 +460,7 @@ static TCGv_i64 cpu_reg(DisasContext *s, int reg) } =20 /* register access for when 31 =3D=3D SP */ -static TCGv_i64 cpu_reg_sp(DisasContext *s, int reg) +TCGv_i64 cpu_reg_sp(DisasContext *s, int reg) { return cpu_X[reg]; } @@ -485,7 +469,7 @@ static TCGv_i64 cpu_reg_sp(DisasContext *s, int reg) * representing the register contents. This TCGv is an auto-freed * temporary so it need not be explicitly freed, and may be modified. */ -static TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf) +TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf) { TCGv_i64 v =3D new_tmp_a64(s); if (reg !=3D 31) { @@ -500,7 +484,7 @@ static TCGv_i64 read_cpu_reg(DisasContext *s, int reg, = int sf) return v; } =20 -static TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf) +TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf) { TCGv_i64 v =3D new_tmp_a64(s); if (sf) { @@ -511,72 +495,6 @@ static TCGv_i64 read_cpu_reg_sp(DisasContext *s, int r= eg, int sf) return v; } =20 -/* We should have at some point before trying to access an FP register - * done the necessary access check, so assert that - * (a) we did the check and - * (b) we didn't then just plough ahead anyway if it failed. - * Print the instruction pattern in the abort message so we can figure - * out what we need to fix if a user encounters this problem in the wild. - */ -static inline void assert_fp_access_checked(DisasContext *s) -{ -#ifdef CONFIG_DEBUG_TCG - if (unlikely(!s->fp_access_checked || s->fp_excp_el)) { - fprintf(stderr, "target-arm: FP access check missing for " - "instruction 0x%08x\n", s->insn); - abort(); - } -#endif -} - -/* Return the offset into CPUARMState of an element of specified - * size, 'element' places in from the least significant end of - * the FP/vector register Qn. - */ -static inline int vec_reg_offset(DisasContext *s, int regno, - int element, TCGMemOp size) -{ - int offs =3D 0; -#ifdef HOST_WORDS_BIGENDIAN - /* This is complicated slightly because vfp.zregs[n].d[0] is - * still the low half and vfp.zregs[n].d[1] the high half - * of the 128 bit vector, even on big endian systems. - * Calculate the offset assuming a fully bigendian 128 bits, - * then XOR to account for the order of the two 64 bit halves. - */ - offs +=3D (16 - ((element + 1) * (1 << size))); - offs ^=3D 8; -#else - offs +=3D element * (1 << size); -#endif - offs +=3D offsetof(CPUARMState, vfp.zregs[regno]); - assert_fp_access_checked(s); - return offs; -} - -/* Return the offset info CPUARMState of the "whole" vector register Qn. = */ -static inline int vec_full_reg_offset(DisasContext *s, int regno) -{ - assert_fp_access_checked(s); - return offsetof(CPUARMState, vfp.zregs[regno]); -} - -/* Return a newly allocated pointer to the vector register. */ -static TCGv_ptr vec_full_reg_ptr(DisasContext *s, int regno) -{ - TCGv_ptr ret =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(ret, cpu_env, vec_full_reg_offset(s, regno)); - return ret; -} - -/* Return the byte size of the "whole" vector register, VL / 8. */ -static inline int vec_full_reg_size(DisasContext *s) -{ - /* FIXME SVE: We should put the composite ZCR_EL* value into tb->flags. - In the meantime this is just the AdvSIMD length of 128. */ - return 128 / 8; -} - /* Return the offset into CPUARMState of a slice (from * the least significant end) of FP register Qn (ie * Dn, Sn, Hn or Bn). @@ -641,7 +559,7 @@ static void clear_vec_high(DisasContext *s, bool is_q, = int rd) } } =20 -static void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v) +void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v) { unsigned ofs =3D fp_reg_offset(s, reg, MO_64); =20 @@ -658,7 +576,7 @@ static void write_fp_sreg(DisasContext *s, int reg, TCG= v_i32 v) tcg_temp_free_i64(tmp); } =20 -static TCGv_ptr get_fpstatus_ptr(bool is_f16) +TCGv_ptr get_fpstatus_ptr(bool is_f16) { TCGv_ptr statusptr =3D tcg_temp_new_ptr(); int offset; @@ -1246,14 +1164,14 @@ static inline bool fp_access_check(DisasContext *s) /* Check that SVE access is enabled. If it is, return true. * If not, emit code to generate an appropriate exception and return false. */ -static inline bool sve_access_check(DisasContext *s) +bool sve_access_check(DisasContext *s) { if (s->sve_excp_el) { gen_exception_insn(s, 4, EXCP_UDEF, syn_sve_access_trap(), s->sve_excp_el); return false; } - return true; + return fp_access_check(s); } =20 /* @@ -3419,8 +3337,8 @@ static inline uint64_t bitmask64(unsigned int length) * value (ie should cause a guest UNDEF exception), and true if they are * valid, in which case the decoded bit pattern is written to result. */ -static bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, - unsigned int imms, unsigned int immr) +bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, + unsigned int imms, unsigned int immr) { uint64_t mask; unsigned e, levels, s, r; @@ -5637,7 +5555,7 @@ static void disas_fp_3src(DisasContext *s, uint32_t i= nsn) * the range 01....1xx to 10....0xx, and the most significant 4 bits of * the mantissa; see VFPExpandImm() in the v8 ARM ARM. */ -static uint64_t vfp_expand_imm(int size, uint8_t imm8) +uint64_t vfp_expand_imm(int size, uint8_t imm8) { uint64_t imm; =20 --=20 2.17.0 From nobody Wed Oct 29 22:55:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526509980381135.2205705778406; Wed, 16 May 2018 15:33:00 -0700 (PDT) Received: from localhost ([::1]:44758 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4yd-0000cW-Fw for importer@patchew.org; Wed, 16 May 2018 18:32:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40900) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4w3-0007Qx-QY for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ4w2-0007JN-KE for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:15 -0400 Received: from mail-pl0-x241.google.com ([2607:f8b0:400e:c01::241]:39059) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ4w2-0007Iz-CT for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:14 -0400 Received: by mail-pl0-x241.google.com with SMTP id c19-v6so1247160pls.6 for ; Wed, 16 May 2018 15:30:14 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rti76ydk7wCoVs4pArdj2slbyyvaqRbPWHSPcl/C3C0=; b=h79lYeC1s5eoLv6EC57aenR11IDEjzhd9jtoxFONnXdx6YDaykWfdtfn7jWhysN22Z 2+mK+zpocttItIAdJoNh8uc+isiGwB9PUIECoR+qzbnm+tZXFV6c5QqwmpUOP/LKZVFM ZgLNTcRTj9r668YgXstvu+paUsfHTxhdLNqeM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rti76ydk7wCoVs4pArdj2slbyyvaqRbPWHSPcl/C3C0=; b=dzsf0sTKl2O7kOBLXump0ivQ+Zh/UmYOPQo7GP1VQZTVFffWnlXVK4lpeOKs96WqWh pqV3CQhZjxorUyKTVex96Yfpl6vnhu8uk+E8rz8PDhLKAgFILYDNHSWaU422RQqT7pC7 P/ydR40udNSCesTMC2L7uBT7DvA1mdUr7fQ5JLK0vw/BcSWQ0xIDB6QnpivPWHFt0c92 fQjYmefv+HtWYv5gANfyyqXxPQrQaXUTxIBGXbCYxoQ4SEmE3iBYiBNCV6aS6oMN1BHa Lg8+7DG4umsLQamMk1Et/9nky6v7s2B15x8GQAFXtgQQn8UEqlwLFfH/JZWb18hCxcpc lemw== X-Gm-Message-State: ALKqPwdn7R94JsM/b9Kp3R852ilmI8FjuvkJvHqMeK2SzmJPTXJSc9Fj WwGNS8l2cMDWCEmZXf030cIpgPLX9fw= X-Google-Smtp-Source: AB8JxZoaLnm/EFzMPWR33VZ0555Eb7YslLcvdNLVjcmhvy8WVaQLHVHq6DhUn1L4y4c6oQ2wqG4PBA== X-Received: by 2002:a17:902:5502:: with SMTP id f2-v6mr2711426pli.108.1526509812974; Wed, 16 May 2018 15:30:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:29:42 -0700 Message-Id: <20180516223007.10256-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH v3-a 02/27] target/arm: Add SVE decode skeleton X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Including only 4, as-yet unimplemented, instruction patterns so that the whole thing compiles. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 7 ++++- target/arm/translate-sve.c | 63 ++++++++++++++++++++++++++++++++++++++ .gitignore | 1 + target/arm/Makefile.objs | 10 ++++++ target/arm/sve.decode | 45 +++++++++++++++++++++++++++ 5 files changed, 125 insertions(+), 1 deletion(-) create mode 100644 target/arm/translate-sve.c create mode 100644 target/arm/sve.decode diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ace9d5063e..f313d38beb 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13653,9 +13653,14 @@ static void disas_a64_insn(CPUARMState *env, Disas= Context *s) s->fp_access_checked =3D false; =20 switch (extract32(insn, 25, 4)) { - case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */ + case 0x0: case 0x1: case 0x3: /* UNALLOCATED */ unallocated_encoding(s); break; + case 0x2: + if (!arm_dc_feature(s, ARM_FEATURE_SVE) || !disas_sve(s, insn)) { + unallocated_encoding(s); + } + break; case 0x8: case 0x9: /* Data processing - immediate */ disas_data_proc_imm(s, insn); break; diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c new file mode 100644 index 0000000000..d323bd0b67 --- /dev/null +++ b/target/arm/translate-sve.c @@ -0,0 +1,63 @@ +/* + * AArch64 SVE translation + * + * Copyright (c) 2018 Linaro, Ltd + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "tcg-op.h" +#include "tcg-op-gvec.h" +#include "qemu/log.h" +#include "arm_ldst.h" +#include "translate.h" +#include "internals.h" +#include "exec/helper-proto.h" +#include "exec/helper-gen.h" +#include "exec/log.h" +#include "trace-tcg.h" +#include "translate-a64.h" + +/* + * Include the generated decoder. + */ + +#include "decode-sve.inc.c" + +/* + * Implement all of the translator functions referenced by the decoder. + */ + +static bool trans_AND_zzz(DisasContext *s, arg_AND_zzz *a, uint32_t insn) +{ + return false; +} + +static bool trans_ORR_zzz(DisasContext *s, arg_ORR_zzz *a, uint32_t insn) +{ + return false; +} + +static bool trans_EOR_zzz(DisasContext *s, arg_EOR_zzz *a, uint32_t insn) +{ + return false; +} + +static bool trans_BIC_zzz(DisasContext *s, arg_BIC_zzz *a, uint32_t insn) +{ + return false; +} diff --git a/.gitignore b/.gitignore index 4055e12ee8..81e1f2fb0f 100644 --- a/.gitignore +++ b/.gitignore @@ -206,3 +206,4 @@ trace-dtrace-root.h trace-dtrace-root.dtrace trace-ust-all.h trace-ust-all.c +/target/arm/decode-sve.inc.c diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 1297bead5f..a6f733eaa8 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -10,3 +10,13 @@ obj-y +=3D gdbstub.o obj-$(TARGET_AARCH64) +=3D cpu64.o translate-a64.o helper-a64.o gdbstub64.o obj-y +=3D crypto_helper.o obj-$(CONFIG_SOFTMMU) +=3D arm-powerctl.o + +DECODETREE =3D $(SRC_PATH)/scripts/decodetree.py + +target/arm/decode-sve.inc.c: $(SRC_PATH)/target/arm/sve.decode $(DECODETRE= E) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) --decode disas_sve -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + +target/arm/translate-sve.o: target/arm/decode-sve.inc.c +obj-$(TARGET_AARCH64) +=3D translate-sve.o diff --git a/target/arm/sve.decode b/target/arm/sve.decode new file mode 100644 index 0000000000..48dac9f71f --- /dev/null +++ b/target/arm/sve.decode @@ -0,0 +1,45 @@ +# AArch64 SVE instruction descriptions +# +# Copyright (c) 2017 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# + +########################################################################### +# Named attribute sets. These are used to make nice(er) names +# when creating helpers common to those for the individual +# instruction patterns. + +&rrr_esz rd rn rm esz + +########################################################################### +# Named instruction formats. These are generally used to +# reduce the amount of duplication between instruction patterns. + +# Three operand with unused vector element size +@rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz e= sz=3D0 + +########################################################################### +# Instruction patterns. Grouped according to the SVE encodingindex.xhtml. + +### SVE Logical - Unpredicated Group + +# SVE bitwise logical operations (unpredicated) +AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_= e0 +ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_= e0 +EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_= e0 +BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_= e0 --=20 2.17.0 From nobody Wed Oct 29 22:55:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526510163341541.0588093960693; Wed, 16 May 2018 15:36:03 -0700 (PDT) Received: from localhost ([::1]:44798 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ51Z-00032g-C3 for importer@patchew.org; Wed, 16 May 2018 18:35:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40930) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4w5-0007Rm-1w for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ4w3-0007Ka-QJ for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:17 -0400 Received: from mail-pl0-x229.google.com ([2607:f8b0:400e:c01::229]:43851) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ4w3-0007Jr-JS for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:15 -0400 Received: by mail-pl0-x229.google.com with SMTP id c41-v6so1239758plj.10 for ; Wed, 16 May 2018 15:30:15 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6FkDAGxpjtctRPD74Kvsj7pbO4IsIUxfkCQDo+Nmo7Q=; b=EHdeLlsd8AY3TQ0HLEU47faoNa6YDQzmrrI8zSz3SRNbbpz7Zdd5F4Y4qG7jTsvDFf llJ4sdtdZw0/KHKl1Ij6/l6+ZdHixWOfhKha4gbQDV/fCIdFCmhnwy8cx7JsasgEgqXU JBzTzIADCwHnpUnmmArQ83wd4aq17CYSmbMlI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6FkDAGxpjtctRPD74Kvsj7pbO4IsIUxfkCQDo+Nmo7Q=; b=ndxA1PgIdQwuFZ3Jgp0HBz/TGVQWy4NNH8NZYI/Tc6ItCufb8qlgQ6Rux1h2QWzpy7 8t7n7L25bXG5WdlzkM8rYqOIhHWjMFJU5C32EkfVWA7LIgjlAGCs/KUATGBl8F4nIqt3 B1mcKN5i44q0iLlIzxA8o/RLUffDwiP5cGdGZMjmN4FC2XKjBarmvvCKbmYUhKI2E6R9 c05+8BlfUQYe8QpCKLbyqeLcBJKCjr4QXjHpLhTpZ7ztP5DeLzUom2wwgpMdG5yfjTg+ 5pFVKrmD5impb4imF5/mWyPWyPqBEvrryWOc4ZPNZshmfkSdMmkPqOnc4N7OzgvdqbcU KRQw== X-Gm-Message-State: ALKqPwdLYViDAKpfNHr4g74kTQYDWUd4zlmgQbr1xujRc2XXjb9SxLzU vo9hNz8IUf63nOJ4jlCa1OKJzvOjd0Q= X-Google-Smtp-Source: AB8JxZq+WPKwT4huwBiyXGEKtVuwX3LJTQxyjlJjKoNfFuVqFjbfQmha3RDZCmSLgtXS4Zdi81/p7A== X-Received: by 2002:a17:902:22a:: with SMTP id 39-v6mr2715823plc.146.1526509814365; Wed, 16 May 2018 15:30:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:29:43 -0700 Message-Id: <20180516223007.10256-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::229 Subject: [Qemu-devel] [PATCH v3-a 03/27] target/arm: Implement SVE Bitwise Logical - Unpredicated Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These were the instructions that were stubbed out when introducing the decode skeleton. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Remove typedefs now present in translate-a64.h. --- target/arm/translate-sve.c | 55 ++++++++++++++++++++++++++++++++------ 1 file changed, 47 insertions(+), 8 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index d323bd0b67..67d6db313e 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -42,22 +42,61 @@ * Implement all of the translator functions referenced by the decoder. */ =20 -static bool trans_AND_zzz(DisasContext *s, arg_AND_zzz *a, uint32_t insn) +/* Invoke a vector expander on two Zregs. */ +static bool do_vector2_z(DisasContext *s, GVecGen2Fn *gvec_fn, + int esz, int rd, int rn) { - return false; + if (sve_access_check(s)) { + unsigned vsz =3D vec_full_reg_size(s); + gvec_fn(esz, vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), vsz, vsz); + } + return true; } =20 -static bool trans_ORR_zzz(DisasContext *s, arg_ORR_zzz *a, uint32_t insn) +/* Invoke a vector expander on three Zregs. */ +static bool do_vector3_z(DisasContext *s, GVecGen3Fn *gvec_fn, + int esz, int rd, int rn, int rm) { - return false; + if (sve_access_check(s)) { + unsigned vsz =3D vec_full_reg_size(s); + gvec_fn(esz, vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), vsz, vsz); + } + return true; } =20 -static bool trans_EOR_zzz(DisasContext *s, arg_EOR_zzz *a, uint32_t insn) +/* Invoke a vector move on two Zregs. */ +static bool do_mov_z(DisasContext *s, int rd, int rn) { - return false; + return do_vector2_z(s, tcg_gen_gvec_mov, 0, rd, rn); } =20 -static bool trans_BIC_zzz(DisasContext *s, arg_BIC_zzz *a, uint32_t insn) +/* + *** SVE Logical - Unpredicated Group + */ + +static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) { - return false; + return do_vector3_z(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->rm); +} + +static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + if (a->rn =3D=3D a->rm) { /* MOV */ + return do_mov_z(s, a->rd, a->rn); + } else { + return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm); + } +} + +static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + return do_vector3_z(s, tcg_gen_gvec_xor, 0, a->rd, a->rn, a->rm); +} + +static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + return do_vector3_z(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm); } --=20 2.17.0 From nobody Wed Oct 29 22:55:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526509986586822.7670864734234; Wed, 16 May 2018 15:33:06 -0700 (PDT) Received: from localhost ([::1]:44759 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4yk-0000fU-0Y for importer@patchew.org; Wed, 16 May 2018 18:33:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40964) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4w6-0007U2-PD for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ4w5-0007Mr-Bn for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:18 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:43757) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ4w5-0007MK-4t for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:17 -0400 Received: by mail-pf0-x242.google.com with SMTP id j20-v6so1045962pff.10 for ; Wed, 16 May 2018 15:30:17 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=um4QLHX1iMAwR5s1WiFKyjG6exIGzfIhln7mUAYtMVI=; b=J8vhtKl8y86nU7vPIyVwIOu5TK3175Sv/d+pgNdlISti/jgUpsZQexUVHDLKWIoK5i ho1x0cIIyvYDPubj2U8eKZWQHTJNp9HOip1de8xMawOtevWBputs0o4kgWnDewb7zf+/ M9FHt8+AKSmq8rr+c4VvGIVLHqQT419OvAKkU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=um4QLHX1iMAwR5s1WiFKyjG6exIGzfIhln7mUAYtMVI=; b=EOCQpLmIF9y/6M29OvQHCv534yjEYQmOCIv81tNubSznrltjvCq5ySlO/JxO0KlABq LNbzq3GQ5hrpqPd1pZfjgvUO28FCttDbz3JUxtEwPw7DIvad+7kye6L6afGV5LHLOiXC uc388241E7cYTp5Ex5QdLcNnzC4j4Ob4gdYHg+LMUV0Q8QPNgMgEgY+724/fHhskR4p3 Pzs2u5edDjNmClRR4YgIn2xFDrXXL1BTPU9giVKrxxYEx1dFL5ualpFDFKA2je+Fyngx viCpG8JRDA39vrXWs2QBbdMWWNU9mXMUvS2M0CwyOhg3I0DSRWProYcIKeaVtzVVM3Jy Nb5A== X-Gm-Message-State: ALKqPwd397xf3rAlsGwgXLFaDRsRdHoUn2sc7ft2BAEXvpy9rsTmRCMG D61im2pohszDXjkjdqJHr3ZVwQcLwpw= X-Google-Smtp-Source: AB8JxZpeDa7pnYH6whioLk6/K+8ZX3Vpo3TnHjl0lnnqBQ56GovzHf8wBThLQWGYk3kJyBO8WvOqEg== X-Received: by 2002:a63:7d0f:: with SMTP id y15-v6mr2165999pgc.317.1526509815773; Wed, 16 May 2018 15:30:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:29:44 -0700 Message-Id: <20180516223007.10256-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v3-a 04/27] target/arm: Implement SVE load vector/predicate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-sve.c | 127 +++++++++++++++++++++++++++++++++++++ target/arm/sve.decode | 20 ++++++ 2 files changed, 147 insertions(+) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 67d6db313e..5ec18a6aac 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -42,6 +42,20 @@ * Implement all of the translator functions referenced by the decoder. */ =20 +/* Return the offset info CPUARMState of the predicate vector register Pn. + * Note for this purpose, FFR is P16. + */ +static inline int pred_full_reg_offset(DisasContext *s, int regno) +{ + return offsetof(CPUARMState, vfp.pregs[regno]); +} + +/* Return the byte size of the whole predicate register, VL / 64. */ +static inline int pred_full_reg_size(DisasContext *s) +{ + return s->sve_len >> 3; +} + /* Invoke a vector expander on two Zregs. */ static bool do_vector2_z(DisasContext *s, GVecGen2Fn *gvec_fn, int esz, int rd, int rn) @@ -100,3 +114,116 @@ static bool trans_BIC_zzz(DisasContext *s, arg_rrr_es= z *a, uint32_t insn) { return do_vector3_z(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm); } + +/* + *** SVE Memory - 32-bit Gather and Unsized Contiguous Group + */ + +/* Subroutine loading a vector register at VOFS of LEN bytes. + * The load should begin at the address Rn + IMM. + */ + +static void do_ldr(DisasContext *s, uint32_t vofs, uint32_t len, + int rn, int imm) +{ + uint32_t len_align =3D QEMU_ALIGN_DOWN(len, 8); + uint32_t len_remain =3D len % 8; + uint32_t nparts =3D len / 8 + ctpop8(len_remain); + int midx =3D get_mem_index(s); + TCGv_i64 addr, t0, t1; + + addr =3D tcg_temp_new_i64(); + t0 =3D tcg_temp_new_i64(); + + /* Note that unpredicated load/store of vector/predicate registers + * are defined as a stream of bytes, which equates to little-endian + * operations on larger quantities. There is no nice way to force + * a little-endian load for aarch64_be-linux-user out of line. + * + * Attempt to keep code expansion to a minimum by limiting the + * amount of unrolling done. + */ + if (nparts <=3D 4) { + int i; + + for (i =3D 0; i < len_align; i +=3D 8) { + tcg_gen_addi_i64(addr, cpu_reg_sp(s, rn), imm + i); + tcg_gen_qemu_ld_i64(t0, addr, midx, MO_LEQ); + tcg_gen_st_i64(t0, cpu_env, vofs + i); + } + } else { + TCGLabel *loop =3D gen_new_label(); + TCGv_ptr tp, i =3D tcg_const_local_ptr(0); + + gen_set_label(loop); + + /* Minimize the number of local temps that must be re-read from + * the stack each iteration. Instead, re-compute values other + * than the loop counter. + */ + tp =3D tcg_temp_new_ptr(); + tcg_gen_addi_ptr(tp, i, imm); + tcg_gen_extu_ptr_i64(addr, tp); + tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, rn)); + + tcg_gen_qemu_ld_i64(t0, addr, midx, MO_LEQ); + + tcg_gen_add_ptr(tp, cpu_env, i); + tcg_gen_addi_ptr(i, i, 8); + tcg_gen_st_i64(t0, tp, vofs); + tcg_temp_free_ptr(tp); + + tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); + tcg_temp_free_ptr(i); + } + + /* Predicate register loads can be any multiple of 2. + * Note that we still store the entire 64-bit unit into cpu_env. + */ + if (len_remain) { + tcg_gen_addi_i64(addr, cpu_reg_sp(s, rn), imm + len_align); + + switch (len_remain) { + case 2: + case 4: + case 8: + tcg_gen_qemu_ld_i64(t0, addr, midx, MO_LE | ctz32(len_remain)); + break; + + case 6: + t1 =3D tcg_temp_new_i64(); + tcg_gen_qemu_ld_i64(t0, addr, midx, MO_LEUL); + tcg_gen_addi_i64(addr, addr, 4); + tcg_gen_qemu_ld_i64(t1, addr, midx, MO_LEUW); + tcg_gen_deposit_i64(t0, t0, t1, 32, 32); + tcg_temp_free_i64(t1); + break; + + default: + g_assert_not_reached(); + } + tcg_gen_st_i64(t0, cpu_env, vofs + len_align); + } + tcg_temp_free_i64(addr); + tcg_temp_free_i64(t0); +} + +static bool trans_LDR_zri(DisasContext *s, arg_rri *a, uint32_t insn) +{ + if (sve_access_check(s)) { + int size =3D vec_full_reg_size(s); + int off =3D vec_full_reg_offset(s, a->rd); + do_ldr(s, off, size, a->rn, a->imm * size); + } + return true; +} + +static bool trans_LDR_pri(DisasContext *s, arg_rri *a, uint32_t insn) +{ + if (sve_access_check(s)) { + int size =3D pred_full_reg_size(s); + int off =3D pred_full_reg_offset(s, a->rd); + do_ldr(s, off, size, a->rn, a->imm * size); + } + return true; +} diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 48dac9f71f..a2c4450e7c 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -19,11 +19,17 @@ # This file is processed by scripts/decodetree.py # =20 +########################################################################### +# Named fields. These are primarily for disjoint fields. + +%imm9_16_10 16:s6 10:3 + ########################################################################### # Named attribute sets. These are used to make nice(er) names # when creating helpers common to those for the individual # instruction patterns. =20 +&rri rd rn imm &rrr_esz rd rn rm esz =20 ########################################################################### @@ -33,6 +39,12 @@ # Three operand with unused vector element size @rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz e= sz=3D0 =20 +# Basic Load/Store with 9-bit immediate offset +@pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \ + &rri imm=3D%imm9_16_10 +@rd_rn_i9 ........ ........ ...... rn:5 rd:5 \ + &rri imm=3D%imm9_16_10 + ########################################################################### # Instruction patterns. Grouped according to the SVE encodingindex.xhtml. =20 @@ -43,3 +55,11 @@ AND_zzz 00000100 00 1 ..... 001 100 ..... ..... = @rd_rn_rm_e0 ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_= e0 EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_= e0 BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_= e0 + +### SVE Memory - 32-bit Gather and Unsized Contiguous Group + +# SVE load predicate register +LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9 + +# SVE load vector register +LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9 --=20 2.17.0 From nobody Wed Oct 29 22:55:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526510352408469.65925105693077; Wed, 16 May 2018 15:39:12 -0700 (PDT) Received: from localhost ([::1]:44818 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ54d-0005OB-JV for importer@patchew.org; Wed, 16 May 2018 18:39:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40985) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4w8-0007Vw-9j for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ4w6-0007Nq-OU for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:20 -0400 Received: from mail-pl0-x244.google.com ([2607:f8b0:400e:c01::244]:33995) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ4w6-0007NQ-Gl for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:18 -0400 Received: by mail-pl0-x244.google.com with SMTP id ay10-v6so1254170plb.1 for ; Wed, 16 May 2018 15:30:18 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PzwbLhJiRVe64r1PT1lWMYnHdYM6IAY4lau+nQgNzhM=; b=D4VrTr4YMKPhdmtkRhF1/9/qZwuhU54SUIw3TUARarDPLVqmmvZ6B+ui1EWcLFR6kN g41Spt8XnLgOnRFQuWg9+pBHe3k0KEcP3uQEEc5jCnzZ/pyXTdoyh68SAHSdwI053zRS HPZ4H0Qp1IT4n91vxfQG5F88dKgAC1eAvePrU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PzwbLhJiRVe64r1PT1lWMYnHdYM6IAY4lau+nQgNzhM=; b=MDJxNgJEdnSJFVr/TFf6tLUEiyfGZuwllO1c8H3ddC9mPqxl35rFgWT2CiFkXbNQ9k CJir3KJOD/dFvK8Sz0pCUXxv9Xy70P0eyH/JpDjb/jKSbXHpjID7AKeveE5gZMccnFJ2 LVpgFHqRyurYaT8l+wrRx2FWCl7w14/tsFXiS00wx7EiXFVFfD7dRZ38rzx+udqZtLdg 4bC1tSU7N5NlTGPLidntBXINW+CyOLJ4Wo+RLocfBaTIVZN2ocm8VXUeJHZDZKZG+1U7 PvQr5Gkv4b4m47FlRXXLBFe/cyzG673sRvjtmjyWyXb0KPUNe8S8AEj0bFPYD3opfzUW /3IA== X-Gm-Message-State: ALKqPwfk5GRqPaZOh0Qk+22kf5TsIrjTZFLii6Zlft5SNVW3XlWu819g Wlzrqjuz5n4JhxrQH0pmIB3RCEJy//c= X-Google-Smtp-Source: AB8JxZpZ6DKoHtT0y4ugj35HTT9jwDf0S9Ybjarv5tYPeqU82u6hjcUt2oCjJFFsES8ClBNftoaizQ== X-Received: by 2002:a17:902:8f84:: with SMTP id z4-v6mr2764021plo.194.1526509817130; Wed, 16 May 2018 15:30:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:29:45 -0700 Message-Id: <20180516223007.10256-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v3-a 05/27] target/arm: Implement SVE predicate test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 21 ++++++++++ target/arm/helper.h | 1 + target/arm/sve_helper.c | 78 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 65 +++++++++++++++++++++++++++++++ target/arm/Makefile.objs | 2 +- target/arm/sve.decode | 5 +++ 6 files changed, 171 insertions(+), 1 deletion(-) create mode 100644 target/arm/helper-sve.h create mode 100644 target/arm/sve_helper.c diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h new file mode 100644 index 0000000000..b6e91539ae --- /dev/null +++ b/target/arm/helper-sve.h @@ -0,0 +1,21 @@ +/* + * AArch64 SVE specific helper definitions + * + * Copyright (c) 2018 Linaro, Ltd + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +DEF_HELPER_FLAGS_2(sve_predtest1, TCG_CALL_NO_WG, i32, i64, i64) +DEF_HELPER_FLAGS_3(sve_predtest, TCG_CALL_NO_WG, i32, ptr, ptr, i32) diff --git a/target/arm/helper.h b/target/arm/helper.h index ce89968b2d..dcb5343d7e 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -605,4 +605,5 @@ DEF_HELPER_FLAGS_5(gvec_fcmlad, TCG_CALL_NO_RWG, =20 #ifdef TARGET_AARCH64 #include "helper-a64.h" +#include "helper-sve.h" #endif diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c new file mode 100644 index 0000000000..1ebb67e1df --- /dev/null +++ b/target/arm/sve_helper.c @@ -0,0 +1,78 @@ +/* + * ARM SVE Operations + * + * Copyright (c) 2018 Linaro, Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "exec/cpu_ldst.h" +#include "exec/helper-proto.h" +#include "tcg/tcg-gvec-desc.h" + + +/* Return a value for NZCV as per the ARM PredTest pseudofunction. + * + * The return value has bit 31 set if N is set, bit 1 set if Z is clear, + * and bit 0 set if C is set. Compare the definitions of these variables + * within CPUARMState. + */ + +/* For no G bits set, NZCV =3D C. */ +#define PREDTEST_INIT 1 + +/* This is an iterative function, called for each Pd and Pg word + * moving forward. + */ +static uint32_t iter_predtest_fwd(uint64_t d, uint64_t g, uint32_t flags) +{ + if (likely(g)) { + /* Compute N from first D & G. + Use bit 2 to signal first G bit seen. */ + if (!(flags & 4)) { + flags |=3D ((d & (g & -g)) !=3D 0) << 31; + flags |=3D 4; + } + + /* Accumulate Z from each D & G. */ + flags |=3D ((d & g) !=3D 0) << 1; + + /* Compute C from last !(D & G). Replace previous. */ + flags =3D deposit32(flags, 0, 1, (d & pow2floor(g)) =3D=3D 0); + } + return flags; +} + +/* The same for a single word predicate. */ +uint32_t HELPER(sve_predtest1)(uint64_t d, uint64_t g) +{ + return iter_predtest_fwd(d, g, PREDTEST_INIT); +} + +/* The same for a multi-word predicate. */ +uint32_t HELPER(sve_predtest)(void *vd, void *vg, uint32_t words) +{ + uint32_t flags =3D PREDTEST_INIT; + uint64_t *d =3D vd, *g =3D vg; + uintptr_t i =3D 0; + + do { + flags =3D iter_predtest_fwd(d[i], g[i], flags); + } while (++i < words); + + return flags; +} diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 5ec18a6aac..c3f1b0bfa6 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -87,6 +87,43 @@ static bool do_mov_z(DisasContext *s, int rd, int rn) return do_vector2_z(s, tcg_gen_gvec_mov, 0, rd, rn); } =20 +/* Set the cpu flags as per a return from an SVE helper. */ +static void do_pred_flags(TCGv_i32 t) +{ + tcg_gen_mov_i32(cpu_NF, t); + tcg_gen_andi_i32(cpu_ZF, t, 2); + tcg_gen_andi_i32(cpu_CF, t, 1); + tcg_gen_movi_i32(cpu_VF, 0); +} + +/* Subroutines computing the ARM PredTest psuedofunction. */ +static void do_predtest1(TCGv_i64 d, TCGv_i64 g) +{ + TCGv_i32 t =3D tcg_temp_new_i32(); + + gen_helper_sve_predtest1(t, d, g); + do_pred_flags(t); + tcg_temp_free_i32(t); +} + +static void do_predtest(DisasContext *s, int dofs, int gofs, int words) +{ + TCGv_ptr dptr =3D tcg_temp_new_ptr(); + TCGv_ptr gptr =3D tcg_temp_new_ptr(); + TCGv_i32 t; + + tcg_gen_addi_ptr(dptr, cpu_env, dofs); + tcg_gen_addi_ptr(gptr, cpu_env, gofs); + t =3D tcg_const_i32(words); + + gen_helper_sve_predtest(t, dptr, gptr, t); + tcg_temp_free_ptr(dptr); + tcg_temp_free_ptr(gptr); + + do_pred_flags(t); + tcg_temp_free_i32(t); +} + /* *** SVE Logical - Unpredicated Group */ @@ -115,6 +152,34 @@ static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz= *a, uint32_t insn) return do_vector3_z(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm); } =20 +/* + *** SVE Predicate Misc Group + */ + +static bool trans_PTEST(DisasContext *s, arg_PTEST *a, uint32_t insn) +{ + if (sve_access_check(s)) { + int nofs =3D pred_full_reg_offset(s, a->rn); + int gofs =3D pred_full_reg_offset(s, a->pg); + int words =3D DIV_ROUND_UP(pred_full_reg_size(s), 8); + + if (words =3D=3D 1) { + TCGv_i64 pn =3D tcg_temp_new_i64(); + TCGv_i64 pg =3D tcg_temp_new_i64(); + + tcg_gen_ld_i64(pn, cpu_env, nofs); + tcg_gen_ld_i64(pg, cpu_env, gofs); + do_predtest1(pn, pg); + + tcg_temp_free_i64(pn); + tcg_temp_free_i64(pg); + } else { + do_predtest(s, nofs, gofs, words); + } + } + return true; +} + /* *** SVE Memory - 32-bit Gather and Unsized Contiguous Group */ diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index a6f733eaa8..11c7baf8a3 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -19,4 +19,4 @@ target/arm/decode-sve.inc.c: $(SRC_PATH)/target/arm/sve.d= ecode $(DECODETREE) "GEN", $(TARGET_DIR)$@) =20 target/arm/translate-sve.o: target/arm/decode-sve.inc.c -obj-$(TARGET_AARCH64) +=3D translate-sve.o +obj-$(TARGET_AARCH64) +=3D translate-sve.o sve_helper.o diff --git a/target/arm/sve.decode b/target/arm/sve.decode index a2c4450e7c..a44ca2f551 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -56,6 +56,11 @@ ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... = @rd_rn_rm_e0 EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_= e0 BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_= e0 =20 +### SVE Predicate Misc Group + +# SVE predicate test +PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000 + ### SVE Memory - 32-bit Gather and Unsized Contiguous Group =20 # SVE load predicate register --=20 2.17.0 From nobody Wed Oct 29 22:55:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526510534986588.1897868859479; Wed, 16 May 2018 15:42:14 -0700 (PDT) Received: from localhost ([::1]:44838 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ57d-00085n-Sa for importer@patchew.org; Wed, 16 May 2018 18:42:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41011) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4wB-0007ZW-He for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ4w8-0007Or-IG for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:23 -0400 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:33232) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ4w8-0007OH-9r for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:20 -0400 Received: by mail-pg0-x241.google.com with SMTP id v7-v6so917291pgs.0 for ; Wed, 16 May 2018 15:30:20 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tyTxXXhJtDsKfZ1lrg4TQj5gtssaO0T9ygGa368Sz0k=; b=D1s14BUu9KvBtZY/OnJePccqzpVLCXoZzAtBN1UcqrDag9NzlPqUi4mDH9AQcx4AHB 0h4NkwvU8W73rByiJhNG3wz+DU0tumOA2kiMVQuVIh5VuFxUAORrpzkD5gRFkP6GQUqV xnD59YYUhHlCiQuZ3z85caoWEmlafQb/+uPiY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tyTxXXhJtDsKfZ1lrg4TQj5gtssaO0T9ygGa368Sz0k=; b=QQyw0WbDKzfAAUn4ZRqTLJFJR2QcekrogRDk6+gNL9g7MVkKlZIsLMY+TA4DTYbxkR KteP9vOQP7zLCQBMhiGT4rXsJqwKflHXqoF138XMRX/61++tzh1Kd+/7MhSJ3qNqD6ld dq7tpuOFNETKpZhMVeVeUCqJc1H1YQtr0X5jO/SamK4wajuky4vMyIaztT4iYzGNz3/p GckI2OkfqSYpAHkN30MS2TzDwU31DPrKCJUjErkg5EUPmZXZYu681XhWQoK2P1EcGKAM 7tekvSzJQtn+15xR+BJJr/bTHy0Dcb2qaHagmUIsJRqNNc0ejJDDM1gh0sBUDuM7ZMIr tDqQ== X-Gm-Message-State: ALKqPweSWWfaXBb2bU6vKAUEhLC26YjcOPODMYCs8muWrGU9I/Tj+R63 oOrvyAiPFXeCN7Cu5apK9IytpzWIIfc= X-Google-Smtp-Source: AB8JxZo66iStio9I09CXdvMeZ+sMPku6PMBE63HXDvnoBoejUjg4l/JuDC20QzxvSEwR/Vna/DWTgg== X-Received: by 2002:a63:6d8f:: with SMTP id i137-v6mr2165961pgc.268.1526509818707; Wed, 16 May 2018 15:30:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:29:46 -0700 Message-Id: <20180516223007.10256-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v3-a 06/27] target/arm: Implement SVE Predicate Logical Operations Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 4 +- target/arm/helper-sve.h | 10 + target/arm/sve_helper.c | 39 ++++ target/arm/translate-sve.c | 361 +++++++++++++++++++++++++++++++++++++ target/arm/sve.decode | 16 ++ 5 files changed, 429 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3b086be570..f9a163ebdd 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -528,6 +528,8 @@ typedef struct CPUARMState { #ifdef TARGET_AARCH64 /* Store FFR as pregs[16] to make it easier to treat as any other.= */ ARMPredicateReg pregs[17]; + /* Scratch space for aa64 sve predicate temporary. */ + ARMPredicateReg preg_tmp; #endif =20 uint32_t xregs[16]; @@ -535,7 +537,7 @@ typedef struct CPUARMState { int vec_len; int vec_stride; =20 - /* scratch space when Tn are not sufficient. */ + /* Scratch space for aa32 neon expansion. */ uint32_t scratch[8]; =20 /* There are a number of distinct float control structures: diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index b6e91539ae..57adc4d912 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -19,3 +19,13 @@ =20 DEF_HELPER_FLAGS_2(sve_predtest1, TCG_CALL_NO_WG, i32, i64, i64) DEF_HELPER_FLAGS_3(sve_predtest, TCG_CALL_NO_WG, i32, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) +DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) +DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) +DEF_HELPER_FLAGS_5(sve_sel_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) +DEF_HELPER_FLAGS_5(sve_orr_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) +DEF_HELPER_FLAGS_5(sve_orn_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) +DEF_HELPER_FLAGS_5(sve_nor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) +DEF_HELPER_FLAGS_5(sve_nand_pppp, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 1ebb67e1df..2eda6f2ef1 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -76,3 +76,42 @@ uint32_t HELPER(sve_predtest)(void *vd, void *vg, uint32= _t words) =20 return flags; } + +#define LOGICAL_PPPP(NAME, FUNC) \ +void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, uint32_t desc) \ +{ \ + uintptr_t opr_sz =3D simd_oprsz(desc); = \ + uint64_t *d =3D vd, *n =3D vn, *m =3D vm, *g =3D vg; = \ + uintptr_t i; \ + for (i =3D 0; i < opr_sz / 8; ++i) { = \ + d[i] =3D FUNC(n[i], m[i], g[i]); = \ + } \ +} + +#define DO_AND(N, M, G) (((N) & (M)) & (G)) +#define DO_BIC(N, M, G) (((N) & ~(M)) & (G)) +#define DO_EOR(N, M, G) (((N) ^ (M)) & (G)) +#define DO_ORR(N, M, G) (((N) | (M)) & (G)) +#define DO_ORN(N, M, G) (((N) | ~(M)) & (G)) +#define DO_NOR(N, M, G) (~((N) | (M)) & (G)) +#define DO_NAND(N, M, G) (~((N) & (M)) & (G)) +#define DO_SEL(N, M, G) (((N) & (G)) | ((M) & ~(G))) + +LOGICAL_PPPP(sve_and_pppp, DO_AND) +LOGICAL_PPPP(sve_bic_pppp, DO_BIC) +LOGICAL_PPPP(sve_eor_pppp, DO_EOR) +LOGICAL_PPPP(sve_sel_pppp, DO_SEL) +LOGICAL_PPPP(sve_orr_pppp, DO_ORR) +LOGICAL_PPPP(sve_orn_pppp, DO_ORN) +LOGICAL_PPPP(sve_nor_pppp, DO_NOR) +LOGICAL_PPPP(sve_nand_pppp, DO_NAND) + +#undef DO_AND +#undef DO_BIC +#undef DO_EOR +#undef DO_ORR +#undef DO_ORN +#undef DO_NOR +#undef DO_NAND +#undef DO_SEL +#undef LOGICAL_PPPP diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index c3f1b0bfa6..67fb3091ac 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -56,6 +56,28 @@ static inline int pred_full_reg_size(DisasContext *s) return s->sve_len >> 3; } =20 +/* Round up the size of a register to a size allowed by + * the tcg vector infrastructure. Any operation which uses this + * size may assume that the bits above pred_full_reg_size are zero, + * and must leave them the same way. + * + * Note that this is not needed for the vector registers as they + * are always properly sized for tcg vectors. + */ +static int size_for_gvec(int size) +{ + if (size <=3D 8) { + return 8; + } else { + return QEMU_ALIGN_UP(size, 16); + } +} + +static int pred_gvec_reg_size(DisasContext *s) +{ + return size_for_gvec(pred_full_reg_size(s)); +} + /* Invoke a vector expander on two Zregs. */ static bool do_vector2_z(DisasContext *s, GVecGen2Fn *gvec_fn, int esz, int rd, int rn) @@ -87,6 +109,52 @@ static bool do_mov_z(DisasContext *s, int rd, int rn) return do_vector2_z(s, tcg_gen_gvec_mov, 0, rd, rn); } =20 +/* Invoke a vector expander on two Pregs. */ +static bool do_vector2_p(DisasContext *s, GVecGen2Fn *gvec_fn, + int esz, int rd, int rn) +{ + if (sve_access_check(s)) { + unsigned psz =3D pred_gvec_reg_size(s); + gvec_fn(esz, pred_full_reg_offset(s, rd), + pred_full_reg_offset(s, rn), psz, psz); + } + return true; +} + +/* Invoke a vector expander on three Pregs. */ +static bool do_vector3_p(DisasContext *s, GVecGen3Fn *gvec_fn, + int esz, int rd, int rn, int rm) +{ + if (sve_access_check(s)) { + unsigned psz =3D pred_gvec_reg_size(s); + gvec_fn(esz, pred_full_reg_offset(s, rd), + pred_full_reg_offset(s, rn), + pred_full_reg_offset(s, rm), psz, psz); + } + return true; +} + +/* Invoke a vector operation on four Pregs. */ +static bool do_vecop4_p(DisasContext *s, const GVecGen4 *gvec_op, + int rd, int rn, int rm, int rg) +{ + if (sve_access_check(s)) { + unsigned psz =3D pred_gvec_reg_size(s); + tcg_gen_gvec_4(pred_full_reg_offset(s, rd), + pred_full_reg_offset(s, rn), + pred_full_reg_offset(s, rm), + pred_full_reg_offset(s, rg), + psz, psz, gvec_op); + } + return true; +} + +/* Invoke a vector move on two Pregs. */ +static bool do_mov_p(DisasContext *s, int rd, int rn) +{ + return do_vector2_p(s, tcg_gen_gvec_mov, 0, rd, rn); +} + /* Set the cpu flags as per a return from an SVE helper. */ static void do_pred_flags(TCGv_i32 t) { @@ -152,6 +220,299 @@ static bool trans_BIC_zzz(DisasContext *s, arg_rrr_es= z *a, uint32_t insn) return do_vector3_z(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm); } =20 +/* + *** SVE Predicate Logical Operations Group + */ + +static bool do_pppp_flags(DisasContext *s, arg_rprr_s *a, + const GVecGen4 *gvec_op) +{ + if (!sve_access_check(s)) { + return true; + } + + unsigned psz =3D pred_gvec_reg_size(s); + int dofs =3D pred_full_reg_offset(s, a->rd); + int nofs =3D pred_full_reg_offset(s, a->rn); + int mofs =3D pred_full_reg_offset(s, a->rm); + int gofs =3D pred_full_reg_offset(s, a->pg); + + if (psz =3D=3D 8) { + /* Do the operation and the flags generation in temps. */ + TCGv_i64 pd =3D tcg_temp_new_i64(); + TCGv_i64 pn =3D tcg_temp_new_i64(); + TCGv_i64 pm =3D tcg_temp_new_i64(); + TCGv_i64 pg =3D tcg_temp_new_i64(); + + tcg_gen_ld_i64(pn, cpu_env, nofs); + tcg_gen_ld_i64(pm, cpu_env, mofs); + tcg_gen_ld_i64(pg, cpu_env, gofs); + + gvec_op->fni8(pd, pn, pm, pg); + tcg_gen_st_i64(pd, cpu_env, dofs); + + do_predtest1(pd, pg); + + tcg_temp_free_i64(pd); + tcg_temp_free_i64(pn); + tcg_temp_free_i64(pm); + tcg_temp_free_i64(pg); + } else { + /* The operation and flags generation is large. The computation + * of the flags depends on the original contents of the guarding + * predicate. If the destination overwrites the guarding predicat= e, + * then the easiest way to get this right is to save a copy. + */ + int tofs =3D gofs; + if (a->rd =3D=3D a->pg) { + tofs =3D offsetof(CPUARMState, vfp.preg_tmp); + tcg_gen_gvec_mov(0, tofs, gofs, psz, psz); + } + + tcg_gen_gvec_4(dofs, nofs, mofs, gofs, psz, psz, gvec_op); + do_predtest(s, dofs, tofs, psz / 8); + } + return true; +} + +static void gen_and_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64= pg) +{ + tcg_gen_and_i64(pd, pn, pm); + tcg_gen_and_i64(pd, pd, pg); +} + +static void gen_and_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, + TCGv_vec pm, TCGv_vec pg) +{ + tcg_gen_and_vec(vece, pd, pn, pm); + tcg_gen_and_vec(vece, pd, pd, pg); +} + +static bool trans_AND_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) +{ + static const GVecGen4 op =3D { + .fni8 =3D gen_and_pg_i64, + .fniv =3D gen_and_pg_vec, + .fno =3D gen_helper_sve_and_pppp, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + }; + if (a->s) { + return do_pppp_flags(s, a, &op); + } else if (a->rn =3D=3D a->rm) { + if (a->pg =3D=3D a->rn) { + return do_mov_p(s, a->rd, a->rn); + } else { + return do_vector3_p(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->p= g); + } + } else if (a->pg =3D=3D a->rn || a->pg =3D=3D a->rm) { + return do_vector3_p(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->rm); + } else { + return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); + } +} + +static void gen_bic_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64= pg) +{ + tcg_gen_andc_i64(pd, pn, pm); + tcg_gen_and_i64(pd, pd, pg); +} + +static void gen_bic_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, + TCGv_vec pm, TCGv_vec pg) +{ + tcg_gen_andc_vec(vece, pd, pn, pm); + tcg_gen_and_vec(vece, pd, pd, pg); +} + +static bool trans_BIC_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) +{ + static const GVecGen4 op =3D { + .fni8 =3D gen_bic_pg_i64, + .fniv =3D gen_bic_pg_vec, + .fno =3D gen_helper_sve_bic_pppp, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + }; + if (a->s) { + return do_pppp_flags(s, a, &op); + } else if (a->pg =3D=3D a->rn) { + return do_vector3_p(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm); + } else { + return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); + } +} + +static void gen_eor_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64= pg) +{ + tcg_gen_xor_i64(pd, pn, pm); + tcg_gen_and_i64(pd, pd, pg); +} + +static void gen_eor_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, + TCGv_vec pm, TCGv_vec pg) +{ + tcg_gen_xor_vec(vece, pd, pn, pm); + tcg_gen_and_vec(vece, pd, pd, pg); +} + +static bool trans_EOR_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) +{ + static const GVecGen4 op =3D { + .fni8 =3D gen_eor_pg_i64, + .fniv =3D gen_eor_pg_vec, + .fno =3D gen_helper_sve_eor_pppp, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + }; + if (a->s) { + return do_pppp_flags(s, a, &op); + } else { + return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); + } +} + +static void gen_sel_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64= pg) +{ + tcg_gen_and_i64(pn, pn, pg); + tcg_gen_andc_i64(pm, pm, pg); + tcg_gen_or_i64(pd, pn, pm); +} + +static void gen_sel_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, + TCGv_vec pm, TCGv_vec pg) +{ + tcg_gen_and_vec(vece, pn, pn, pg); + tcg_gen_andc_vec(vece, pm, pm, pg); + tcg_gen_or_vec(vece, pd, pn, pm); +} + +static bool trans_SEL_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) +{ + static const GVecGen4 op =3D { + .fni8 =3D gen_sel_pg_i64, + .fniv =3D gen_sel_pg_vec, + .fno =3D gen_helper_sve_sel_pppp, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + }; + if (a->s) { + return false; + } else { + return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); + } +} + +static void gen_orr_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64= pg) +{ + tcg_gen_or_i64(pd, pn, pm); + tcg_gen_and_i64(pd, pd, pg); +} + +static void gen_orr_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, + TCGv_vec pm, TCGv_vec pg) +{ + tcg_gen_or_vec(vece, pd, pn, pm); + tcg_gen_and_vec(vece, pd, pd, pg); +} + +static bool trans_ORR_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) +{ + static const GVecGen4 op =3D { + .fni8 =3D gen_orr_pg_i64, + .fniv =3D gen_orr_pg_vec, + .fno =3D gen_helper_sve_orr_pppp, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + }; + if (a->s) { + return do_pppp_flags(s, a, &op); + } else if (a->pg =3D=3D a->rn && a->rn =3D=3D a->rm) { + return do_mov_p(s, a->rd, a->rn); + } else { + return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); + } +} + +static void gen_orn_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64= pg) +{ + tcg_gen_orc_i64(pd, pn, pm); + tcg_gen_and_i64(pd, pd, pg); +} + +static void gen_orn_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, + TCGv_vec pm, TCGv_vec pg) +{ + tcg_gen_orc_vec(vece, pd, pn, pm); + tcg_gen_and_vec(vece, pd, pd, pg); +} + +static bool trans_ORN_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) +{ + static const GVecGen4 op =3D { + .fni8 =3D gen_orn_pg_i64, + .fniv =3D gen_orn_pg_vec, + .fno =3D gen_helper_sve_orn_pppp, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + }; + if (a->s) { + return do_pppp_flags(s, a, &op); + } else { + return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); + } +} + +static void gen_nor_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64= pg) +{ + tcg_gen_or_i64(pd, pn, pm); + tcg_gen_andc_i64(pd, pg, pd); +} + +static void gen_nor_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, + TCGv_vec pm, TCGv_vec pg) +{ + tcg_gen_or_vec(vece, pd, pn, pm); + tcg_gen_andc_vec(vece, pd, pg, pd); +} + +static bool trans_NOR_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) +{ + static const GVecGen4 op =3D { + .fni8 =3D gen_nor_pg_i64, + .fniv =3D gen_nor_pg_vec, + .fno =3D gen_helper_sve_nor_pppp, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + }; + if (a->s) { + return do_pppp_flags(s, a, &op); + } else { + return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); + } +} + +static void gen_nand_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i6= 4 pg) +{ + tcg_gen_and_i64(pd, pn, pm); + tcg_gen_andc_i64(pd, pg, pd); +} + +static void gen_nand_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, + TCGv_vec pm, TCGv_vec pg) +{ + tcg_gen_and_vec(vece, pd, pn, pm); + tcg_gen_andc_vec(vece, pd, pg, pd); +} + +static bool trans_NAND_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) +{ + static const GVecGen4 op =3D { + .fni8 =3D gen_nand_pg_i64, + .fniv =3D gen_nand_pg_vec, + .fno =3D gen_helper_sve_nand_pppp, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + }; + if (a->s) { + return do_pppp_flags(s, a, &op); + } else { + return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); + } +} + /* *** SVE Predicate Misc Group */ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index a44ca2f551..f695dda3b1 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -31,6 +31,7 @@ =20 &rri rd rn imm &rrr_esz rd rn rm esz +&rprr_s rd pg rn rm s =20 ########################################################################### # Named instruction formats. These are generally used to @@ -39,6 +40,9 @@ # Three operand with unused vector element size @rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz e= sz=3D0 =20 +# Three predicate operand, with governing predicate, flag setting +@pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s + # Basic Load/Store with 9-bit immediate offset @pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \ &rri imm=3D%imm9_16_10 @@ -56,6 +60,18 @@ ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... = @rd_rn_rm_e0 EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_= e0 BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_= e0 =20 +### SVE Predicate Logical Operations Group + +# SVE predicate logical operations +AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_= pm_s +BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_= pm_s +EOR_pppp 00100101 0. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_= pm_s +SEL_pppp 00100101 0. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_= pm_s +ORR_pppp 00100101 1. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_= pm_s +ORN_pppp 00100101 1. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_= pm_s +NOR_pppp 00100101 1. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_= pm_s +NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_= pm_s + ### SVE Predicate Misc Group =20 # SVE predicate test --=20 2.17.0 From nobody Wed Oct 29 22:55:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526510741112881.7906664226396; Wed, 16 May 2018 15:45:41 -0700 (PDT) Received: from localhost ([::1]:44857 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ5Ap-0002Ip-SK for importer@patchew.org; Wed, 16 May 2018 18:45:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41023) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4wC-0007ab-Mu for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ4wA-0007Ph-97 for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:24 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:33117) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ4wA-0007PG-0k for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:22 -0400 Received: by mail-pf0-x243.google.com with SMTP id a20-v6so1057948pfo.0 for ; Wed, 16 May 2018 15:30:21 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=L3S3cpaCBhjw05YBkRNan4r2OCrZvuVbBhO9LP27XAI=; b=ifKYQF4YLTO18TJ4qe5569iZ40/Qi8zPn3USnHr/wdTKHLjN75XCGLLjts5jK+v60F ITYjfwQeInSqPIQVcpiFgR4bMJvn048PuguemyQ0JRXXN9/lUrH+aGG1ZaB5ln+HMglb IWI2UBMEEfOROS4/lXc3REe4BcgzfZs3FvcE8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=L3S3cpaCBhjw05YBkRNan4r2OCrZvuVbBhO9LP27XAI=; b=Yw3Ezu2Fus/Aek7fTpWwIpNiPA363pRMwjiAtawtPO3Z3XlTZqgzl2BYDIGmPxBkqv +St8JQ881urUXPcjba0/iglPg43y4m3gpSreBCnEk8PBeIx2ajULg2kq0FiHpR8h/UG7 GuDGJ49TLhROZPIFHoI3RCnDcjmTFnDRlLL8EtCcECzvsfOTG7CmdRLLsm0riPFjRUuN ZUAssR6jV4X0OHL1tpqEOpccid8fLpGB92fGNg9jo3AZcMcsPGYtl6nkv3ILQmVUvOD0 bk/0mln2OoAllgEnmQBJVQmYqfmQIT1nv4syeL7KM5hBp3kUV8fr6phT+ku0oIrwR4Vz 3ooA== X-Gm-Message-State: ALKqPweBtLs6QLy9UbvywR2sCuYbsrPMnzUav3UTbB6rNQoSp5vBizgo RrpHPMJ1os3tgrbVAmZjCdlajxEYtCc= X-Google-Smtp-Source: AB8JxZrfn+KrkkfsrXwMdTA7xdro8nX8tKAcHt/OUS/BECJTz+Wl7xufmxoLusBw+QANqaZkhQecNQ== X-Received: by 2002:a63:3286:: with SMTP id y128-v6mr2178528pgy.419.1526509820413; Wed, 16 May 2018 15:30:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:29:47 -0700 Message-Id: <20180516223007.10256-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v3-a 07/27] target/arm: Implement SVE Predicate Misc Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 4 + target/arm/helper-sve.h | 3 + target/arm/sve_helper.c | 84 +++++++++++++++ target/arm/translate-sve.c | 209 +++++++++++++++++++++++++++++++++++++ target/arm/sve.decode | 31 ++++++ 5 files changed, 331 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f9a163ebdd..d131ced435 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -527,6 +527,7 @@ typedef struct CPUARMState { =20 #ifdef TARGET_AARCH64 /* Store FFR as pregs[16] to make it easier to treat as any other.= */ +#define FFR_PRED_NUM 16 ARMPredicateReg pregs[17]; /* Scratch space for aa64 sve predicate temporary. */ ARMPredicateReg preg_tmp; @@ -2948,4 +2949,7 @@ static inline uint64_t *aa64_vfp_qreg(CPUARMState *en= v, unsigned regno) return &env->vfp.zregs[regno].d[0]; } =20 +/* Shared between translate-sve.c and sve_helper.c. */ +extern const uint64_t pred_esz_masks[4]; + #endif diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 57adc4d912..0c04afff8c 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -20,6 +20,9 @@ DEF_HELPER_FLAGS_2(sve_predtest1, TCG_CALL_NO_WG, i32, i64, i64) DEF_HELPER_FLAGS_3(sve_predtest, TCG_CALL_NO_WG, i32, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_3(sve_pfirst, TCG_CALL_NO_WG, i32, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_pnext, TCG_CALL_NO_WG, i32, ptr, ptr, i32) + DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 2eda6f2ef1..cc164edfe8 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -115,3 +115,87 @@ LOGICAL_PPPP(sve_nand_pppp, DO_NAND) #undef DO_NAND #undef DO_SEL #undef LOGICAL_PPPP + +/* Similar to the ARM LastActiveElement pseudocode function, except the + result is multiplied by the element size. This includes the not found + indication; e.g. not found for esz=3D3 is -8. */ +static intptr_t last_active_element(uint64_t *g, intptr_t words, intptr_t = esz) +{ + uint64_t mask =3D pred_esz_masks[esz]; + intptr_t i =3D words; + + do { + uint64_t this_g =3D g[--i] & mask; + if (this_g) { + return i * 64 + (63 - clz64(this_g)); + } + } while (i > 0); + return (intptr_t)-1 << esz; +} + +uint32_t HELPER(sve_pfirst)(void *vd, void *vg, uint32_t words) +{ + uint32_t flags =3D PREDTEST_INIT; + uint64_t *d =3D vd, *g =3D vg; + intptr_t i =3D 0; + + do { + uint64_t this_d =3D d[i]; + uint64_t this_g =3D g[i]; + + if (this_g) { + if (!(flags & 4)) { + /* Set in D the first bit of G. */ + this_d |=3D this_g & -this_g; + d[i] =3D this_d; + } + flags =3D iter_predtest_fwd(this_d, this_g, flags); + } + } while (++i < words); + + return flags; +} + +uint32_t HELPER(sve_pnext)(void *vd, void *vg, uint32_t pred_desc) +{ + intptr_t words =3D extract32(pred_desc, 0, SIMD_OPRSZ_BITS); + intptr_t esz =3D extract32(pred_desc, SIMD_DATA_SHIFT, 2); + uint32_t flags =3D PREDTEST_INIT; + uint64_t *d =3D vd, *g =3D vg, esz_mask; + intptr_t i, next; + + next =3D last_active_element(vd, words, esz) + (1 << esz); + esz_mask =3D pred_esz_masks[esz]; + + /* Similar to the pseudocode for pnext, but scaled by ESZ + so that we find the correct bit. */ + if (next < words * 64) { + uint64_t mask =3D -1; + + if (next & 63) { + mask =3D ~((1ull << (next & 63)) - 1); + next &=3D -64; + } + do { + uint64_t this_g =3D g[next / 64] & esz_mask & mask; + if (this_g !=3D 0) { + next =3D (next & -64) + ctz64(this_g); + break; + } + next +=3D 64; + mask =3D -1; + } while (next < words * 64); + } + + i =3D 0; + do { + uint64_t this_d =3D 0; + if (i =3D=3D next / 64) { + this_d =3D 1ull << (next & 63); + } + d[i] =3D this_d; + flags =3D iter_predtest_fwd(this_d, g[i] & esz_mask, flags); + } while (++i < words); + + return flags; +} diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 67fb3091ac..4bb40da119 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -22,6 +22,7 @@ #include "exec/exec-all.h" #include "tcg-op.h" #include "tcg-op-gvec.h" +#include "tcg-gvec-desc.h" #include "qemu/log.h" #include "arm_ldst.h" #include "translate.h" @@ -192,6 +193,12 @@ static void do_predtest(DisasContext *s, int dofs, int= gofs, int words) tcg_temp_free_i32(t); } =20 +/* For each element size, the bits within a predicate word that are active= . */ +const uint64_t pred_esz_masks[4] =3D { + 0xffffffffffffffffull, 0x5555555555555555ull, + 0x1111111111111111ull, 0x0101010101010101ull +}; + /* *** SVE Logical - Unpredicated Group */ @@ -541,6 +548,208 @@ static bool trans_PTEST(DisasContext *s, arg_PTEST *a= , uint32_t insn) return true; } =20 +/* See the ARM pseudocode DecodePredCount. */ +static unsigned decode_pred_count(unsigned fullsz, int pattern, int esz) +{ + unsigned elements =3D fullsz >> esz; + unsigned bound; + + switch (pattern) { + case 0x0: /* POW2 */ + return pow2floor(elements); + case 0x1: /* VL1 */ + case 0x2: /* VL2 */ + case 0x3: /* VL3 */ + case 0x4: /* VL4 */ + case 0x5: /* VL5 */ + case 0x6: /* VL6 */ + case 0x7: /* VL7 */ + case 0x8: /* VL8 */ + bound =3D pattern; + break; + case 0x9: /* VL16 */ + case 0xa: /* VL32 */ + case 0xb: /* VL64 */ + case 0xc: /* VL128 */ + case 0xd: /* VL256 */ + bound =3D 16 << (pattern - 9); + break; + case 0x1d: /* MUL4 */ + return elements - elements % 4; + case 0x1e: /* MUL3 */ + return elements - elements % 3; + case 0x1f: /* ALL */ + return elements; + default: /* #uimm5 */ + return 0; + } + return elements >=3D bound ? bound : 0; +} + +/* This handles all of the predicate initialization instructions, + * PTRUE, PFALSE, SETFFR. For PFALSE, we will have set PAT =3D=3D 32 + * so that decode_pred_count returns 0. For SETFFR, we will have + * set RD =3D=3D 16 =3D=3D FFR. + */ +static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool set= flag) +{ + if (!sve_access_check(s)) { + return true; + } + + unsigned fullsz =3D vec_full_reg_size(s); + unsigned ofs =3D pred_full_reg_offset(s, rd); + unsigned numelem, setsz, i; + uint64_t word, lastword; + TCGv_i64 t; + + numelem =3D decode_pred_count(fullsz, pat, esz); + + /* Determine what we must store into each bit, and how many. */ + if (numelem =3D=3D 0) { + lastword =3D word =3D 0; + setsz =3D fullsz; + } else { + setsz =3D numelem << esz; + lastword =3D word =3D pred_esz_masks[esz]; + if (setsz % 64) { + lastword &=3D ~(-1ull << (setsz % 64)); + } + } + + t =3D tcg_temp_new_i64(); + if (fullsz <=3D 64) { + tcg_gen_movi_i64(t, lastword); + tcg_gen_st_i64(t, cpu_env, ofs); + goto done; + } + + if (word =3D=3D lastword) { + unsigned maxsz =3D size_for_gvec(fullsz / 8); + unsigned oprsz =3D size_for_gvec(setsz / 8); + + if (oprsz * 8 =3D=3D setsz) { + tcg_gen_gvec_dup64i(ofs, oprsz, maxsz, word); + goto done; + } + if (oprsz * 8 =3D=3D setsz + 8) { + tcg_gen_gvec_dup64i(ofs, oprsz, maxsz, word); + tcg_gen_movi_i64(t, 0); + tcg_gen_st_i64(t, cpu_env, ofs + oprsz - 8); + goto done; + } + } + + setsz /=3D 8; + fullsz /=3D 8; + + tcg_gen_movi_i64(t, word); + for (i =3D 0; i < setsz; i +=3D 8) { + tcg_gen_st_i64(t, cpu_env, ofs + i); + } + if (lastword !=3D word) { + tcg_gen_movi_i64(t, lastword); + tcg_gen_st_i64(t, cpu_env, ofs + i); + i +=3D 8; + } + if (i < fullsz) { + tcg_gen_movi_i64(t, 0); + for (; i < fullsz; i +=3D 8) { + tcg_gen_st_i64(t, cpu_env, ofs + i); + } + } + + done: + tcg_temp_free_i64(t); + + /* PTRUES */ + if (setflag) { + tcg_gen_movi_i32(cpu_NF, -(word !=3D 0)); + tcg_gen_movi_i32(cpu_CF, word =3D=3D 0); + tcg_gen_movi_i32(cpu_VF, 0); + tcg_gen_mov_i32(cpu_ZF, cpu_NF); + } + return true; +} + +static bool trans_PTRUE(DisasContext *s, arg_PTRUE *a, uint32_t insn) +{ + return do_predset(s, a->esz, a->rd, a->pat, a->s); +} + +static bool trans_SETFFR(DisasContext *s, arg_SETFFR *a, uint32_t insn) +{ + /* Note pat =3D=3D 31 is #all, to set all elements. */ + return do_predset(s, 0, FFR_PRED_NUM, 31, false); +} + +static bool trans_PFALSE(DisasContext *s, arg_PFALSE *a, uint32_t insn) +{ + /* Note pat =3D=3D 32 is #unimp, to set no elements. */ + return do_predset(s, 0, a->rd, 32, false); +} + +static bool trans_RDFFR_p(DisasContext *s, arg_RDFFR_p *a, uint32_t insn) +{ + /* The path through do_pppp_flags is complicated enough to want to avo= id + * duplication. Frob the arguments into the form of a predicated AND. + */ + arg_rprr_s alt_a =3D { + .rd =3D a->rd, .pg =3D a->pg, .s =3D a->s, + .rn =3D FFR_PRED_NUM, .rm =3D FFR_PRED_NUM, + }; + return trans_AND_pppp(s, &alt_a, insn); +} + +static bool trans_RDFFR(DisasContext *s, arg_RDFFR *a, uint32_t insn) +{ + return do_mov_p(s, a->rd, FFR_PRED_NUM); +} + +static bool trans_WRFFR(DisasContext *s, arg_WRFFR *a, uint32_t insn) +{ + return do_mov_p(s, FFR_PRED_NUM, a->rn); +} + +static bool do_pfirst_pnext(DisasContext *s, arg_rr_esz *a, + void (*gen_fn)(TCGv_i32, TCGv_ptr, + TCGv_ptr, TCGv_i32)) +{ + if (!sve_access_check(s)) { + return true; + } + + TCGv_ptr t_pd =3D tcg_temp_new_ptr(); + TCGv_ptr t_pg =3D tcg_temp_new_ptr(); + TCGv_i32 t; + unsigned desc; + + desc =3D DIV_ROUND_UP(pred_full_reg_size(s), 8); + desc =3D deposit32(desc, SIMD_DATA_SHIFT, 2, a->esz); + + tcg_gen_addi_ptr(t_pd, cpu_env, pred_full_reg_offset(s, a->rd)); + tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->rn)); + t =3D tcg_const_i32(desc); + + gen_fn(t, t_pd, t_pg, t); + tcg_temp_free_ptr(t_pd); + tcg_temp_free_ptr(t_pg); + + do_pred_flags(t); + tcg_temp_free_i32(t); + return true; +} + +static bool trans_PFIRST(DisasContext *s, arg_rr_esz *a, uint32_t insn) +{ + return do_pfirst_pnext(s, a, gen_helper_sve_pfirst); +} + +static bool trans_PNEXT(DisasContext *s, arg_rr_esz *a, uint32_t insn) +{ + return do_pfirst_pnext(s, a, gen_helper_sve_pnext); +} + /* *** SVE Memory - 32-bit Gather and Unsized Contiguous Group */ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index f695dda3b1..a390abb537 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -29,6 +29,7 @@ # when creating helpers common to those for the individual # instruction patterns. =20 +&rr_esz rd rn esz &rri rd rn imm &rrr_esz rd rn rm esz &rprr_s rd pg rn rm s @@ -37,6 +38,12 @@ # Named instruction formats. These are generally used to # reduce the amount of duplication between instruction patterns. =20 +# Two operand with unused vector element size +@pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz es= z=3D0 + +# Two operand +@pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz + # Three operand with unused vector element size @rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz e= sz=3D0 =20 @@ -77,6 +84,30 @@ NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 ...= . @pd_pg_pn_pm_s # SVE predicate test PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000 =20 +# SVE predicate initialize +PTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4 + +# SVE initialize FFR +SETFFR 00100101 0010 1100 1001 0000 0000 0000 + +# SVE zero predicate register +PFALSE 00100101 0001 1000 1110 0100 0000 rd:4 + +# SVE predicate read from FFR (predicated) +RDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4 + +# SVE predicate read from FFR (unpredicated) +RDFFR 00100101 0001 1001 1111 0000 0000 rd:4 + +# SVE FFR write from predicate (WRFFR) +WRFFR 00100101 0010 1000 1001 000 rn:4 00000 + +# SVE predicate first active +PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0 + +# SVE predicate next active +PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn + ### SVE Memory - 32-bit Gather and Unsized Contiguous Group =20 # SVE load predicate register --=20 2.17.0 From nobody Wed Oct 29 22:55:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526510213359708.939619664361; Wed, 16 May 2018 15:36:53 -0700 (PDT) Received: from localhost ([::1]:44799 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ52S-0003gO-AG for importer@patchew.org; Wed, 16 May 2018 18:36:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41061) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4wE-0007ck-Pn for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ4wB-0007Qb-K2 for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:26 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:46561) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ4wB-0007Q3-Au for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:23 -0400 Received: by mail-pf0-x241.google.com with SMTP id p12-v6so1040242pff.13 for ; Wed, 16 May 2018 15:30:23 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jKr7dwsv80AnfIuxMDhCnm0a0d0b4q+foWIn8o+aLxk=; b=i+Miw9ryCl3yJyCZHiCyIr09UTC1LGRjcRgpeu8fA5ORxKqMvWlm6ljqpfWgvhT3a+ iKvFdxiSp4CEZ3TjQ8mbSuG2B+rU+Hd2ODkqBWzIJNvkcEn3ZVN+NUlh+zSRWNtLTKar vJZsOz28mcTrHijTwuA3BozVO7pNfmIjji9fY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jKr7dwsv80AnfIuxMDhCnm0a0d0b4q+foWIn8o+aLxk=; b=NbQFccQWcOoUe6xIpR6RHvWwthcLvjIyJm+qCkbLdFt8znoiE7PRQUCvSegPMnj3fd HMpMESAGDcFZ8wP2LLQzRuGBYFSYvUyXy9Ctq9E3bhE/7NJzL00+dJMdIa+cHdf2Oxzo iba8efcB3M2CvN2Byrx21xQsQi9kqisl+TiIMW4/f1K6sdb4EkfDhC1Y7s8e94yvCXXp eTEvoTxaITOSoj+QeBHDyVEBCfggwzrrYnVDlJoPYCKnUjf9JVHzxYiz99xjgtWCw3Jz C+9sbXw0AM9Bw2XEaQA3r8OBJD4tcrZTWcwweSdw4kN0LApEA9g8NOzC6KZnpCSZ8Z3h 5uHg== X-Gm-Message-State: ALKqPwf0fM7Zs9FIDYNdiJn28YNSWruI9PsEWILovpQMrwejdqZkas6R 62MYh8cM9qwlEXCWcHpZCE4wFJPx6Qg= X-Google-Smtp-Source: AB8JxZr2VAeyfJGcGX3DIasIH+iJNsGm7BojuqfqpsgcWtzRaKz++GrqSP+ZrUfuxQbpZHlFoxiGwA== X-Received: by 2002:a63:7b1d:: with SMTP id w29-v6mr2131400pgc.417.1526509821576; Wed, 16 May 2018 15:30:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:29:48 -0700 Message-Id: <20180516223007.10256-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v3-a 08/27] target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper-sve.h | 145 +++++++++++++++++++++++++++ target/arm/sve_helper.c | 194 +++++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 68 +++++++++++++ target/arm/sve.decode | 42 ++++++++ 4 files changed, 449 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 0c04afff8c..5b82ba1501 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -23,6 +23,151 @@ DEF_HELPER_FLAGS_3(sve_predtest, TCG_CALL_NO_WG, i32, p= tr, ptr, i32) DEF_HELPER_FLAGS_3(sve_pfirst, TCG_CALL_NO_WG, i32, ptr, ptr, i32) DEF_HELPER_FLAGS_3(sve_pnext, TCG_CALL_NO_WG, i32, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_5(sve_and_zpzz_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_and_zpzz_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_and_zpzz_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_and_zpzz_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sve_eor_zpzz_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_eor_zpzz_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_eor_zpzz_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_eor_zpzz_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sve_orr_zpzz_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_orr_zpzz_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_orr_zpzz_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_orr_zpzz_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sve_bic_zpzz_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_bic_zpzz_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_bic_zpzz_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_bic_zpzz_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sve_add_zpzz_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_add_zpzz_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_add_zpzz_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_add_zpzz_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sve_sub_zpzz_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_sub_zpzz_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_sub_zpzz_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_sub_zpzz_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sve_smax_zpzz_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_smax_zpzz_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_smax_zpzz_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_smax_zpzz_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sve_umax_zpzz_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_umax_zpzz_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_umax_zpzz_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_umax_zpzz_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sve_smin_zpzz_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_smin_zpzz_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_smin_zpzz_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_smin_zpzz_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sve_umin_zpzz_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_umin_zpzz_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_umin_zpzz_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_umin_zpzz_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sve_sabd_zpzz_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_sabd_zpzz_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_sabd_zpzz_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_sabd_zpzz_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sve_uabd_zpzz_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_uabd_zpzz_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_uabd_zpzz_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_uabd_zpzz_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sve_mul_zpzz_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_mul_zpzz_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_mul_zpzz_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_mul_zpzz_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sve_smulh_zpzz_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_smulh_zpzz_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_smulh_zpzz_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_smulh_zpzz_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sve_umulh_zpzz_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_umulh_zpzz_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_umulh_zpzz_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_umulh_zpzz_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sve_sdiv_zpzz_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_sdiv_zpzz_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sve_udiv_zpzz_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_udiv_zpzz_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index cc164edfe8..b8c8a06122 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -25,6 +25,22 @@ #include "tcg/tcg-gvec-desc.h" =20 =20 +/* Note that vector data is stored in host-endian 64-bit chunks, + so addressing units smaller than that needs a host-endian fixup. */ +#ifdef HOST_WORDS_BIGENDIAN +#define H1(x) ((x) ^ 7) +#define H1_2(x) ((x) ^ 6) +#define H1_4(x) ((x) ^ 4) +#define H2(x) ((x) ^ 3) +#define H4(x) ((x) ^ 1) +#else +#define H1(x) (x) +#define H1_2(x) (x) +#define H1_4(x) (x) +#define H2(x) (x) +#define H4(x) (x) +#endif + /* Return a value for NZCV as per the ARM PredTest pseudofunction. * * The return value has bit 31 set if N is set, bit 1 set if Z is clear, @@ -116,6 +132,184 @@ LOGICAL_PPPP(sve_nand_pppp, DO_NAND) #undef DO_SEL #undef LOGICAL_PPPP =20 +/* Fully general three-operand expander, controlled by a predicate. + * This is complicated by the host-endian storage of the register file. + */ +/* ??? I don't expect the compiler could ever vectorize this itself. + * With some tables we can convert bit masks to byte masks, and with + * extra care wrt byte/word ordering we could use gcc generic vectors + * and do 16 bytes at a time. + */ +#define DO_ZPZZ(NAME, TYPE, H, OP) \ +void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, uint32_t desc) \ +{ \ + intptr_t i, opr_sz =3D simd_oprsz(desc); \ + for (i =3D 0; i < opr_sz; ) { \ + uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); \ + do { \ + if (pg & 1) { \ + TYPE nn =3D *(TYPE *)(vn + H(i)); \ + TYPE mm =3D *(TYPE *)(vm + H(i)); \ + *(TYPE *)(vd + H(i)) =3D OP(nn, mm); \ + } \ + i +=3D sizeof(TYPE), pg >>=3D sizeof(TYPE); = \ + } while (i & 15); \ + } \ +} + +/* Similarly, specialized for 64-bit operands. */ +#define DO_ZPZZ_D(NAME, TYPE, OP) \ +void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, uint32_t desc) \ +{ \ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; \ + TYPE *d =3D vd, *n =3D vn, *m =3D vm; \ + uint8_t *pg =3D vg; \ + for (i =3D 0; i < opr_sz; i +=3D 1) { \ + if (pg[H1(i)] & 1) { \ + TYPE nn =3D n[i], mm =3D m[i]; \ + d[i] =3D OP(nn, mm); \ + } \ + } \ +} + +#define DO_AND(N, M) (N & M) +#define DO_EOR(N, M) (N ^ M) +#define DO_ORR(N, M) (N | M) +#define DO_BIC(N, M) (N & ~M) +#define DO_ADD(N, M) (N + M) +#define DO_SUB(N, M) (N - M) +#define DO_MAX(N, M) ((N) >=3D (M) ? (N) : (M)) +#define DO_MIN(N, M) ((N) >=3D (M) ? (M) : (N)) +#define DO_ABD(N, M) ((N) >=3D (M) ? (N) - (M) : (M) - (N)) +#define DO_MUL(N, M) (N * M) +#define DO_DIV(N, M) (M ? N / M : 0) + +DO_ZPZZ(sve_and_zpzz_b, uint8_t, H1, DO_AND) +DO_ZPZZ(sve_and_zpzz_h, uint16_t, H1_2, DO_AND) +DO_ZPZZ(sve_and_zpzz_s, uint32_t, H1_4, DO_AND) +DO_ZPZZ_D(sve_and_zpzz_d, uint64_t, DO_AND) + +DO_ZPZZ(sve_orr_zpzz_b, uint8_t, H1, DO_ORR) +DO_ZPZZ(sve_orr_zpzz_h, uint16_t, H1_2, DO_ORR) +DO_ZPZZ(sve_orr_zpzz_s, uint32_t, H1_4, DO_ORR) +DO_ZPZZ_D(sve_orr_zpzz_d, uint64_t, DO_ORR) + +DO_ZPZZ(sve_eor_zpzz_b, uint8_t, H1, DO_EOR) +DO_ZPZZ(sve_eor_zpzz_h, uint16_t, H1_2, DO_EOR) +DO_ZPZZ(sve_eor_zpzz_s, uint32_t, H1_4, DO_EOR) +DO_ZPZZ_D(sve_eor_zpzz_d, uint64_t, DO_EOR) + +DO_ZPZZ(sve_bic_zpzz_b, uint8_t, H1, DO_BIC) +DO_ZPZZ(sve_bic_zpzz_h, uint16_t, H1_2, DO_BIC) +DO_ZPZZ(sve_bic_zpzz_s, uint32_t, H1_4, DO_BIC) +DO_ZPZZ_D(sve_bic_zpzz_d, uint64_t, DO_BIC) + +DO_ZPZZ(sve_add_zpzz_b, uint8_t, H1, DO_ADD) +DO_ZPZZ(sve_add_zpzz_h, uint16_t, H1_2, DO_ADD) +DO_ZPZZ(sve_add_zpzz_s, uint32_t, H1_4, DO_ADD) +DO_ZPZZ_D(sve_add_zpzz_d, uint64_t, DO_ADD) + +DO_ZPZZ(sve_sub_zpzz_b, uint8_t, H1, DO_SUB) +DO_ZPZZ(sve_sub_zpzz_h, uint16_t, H1_2, DO_SUB) +DO_ZPZZ(sve_sub_zpzz_s, uint32_t, H1_4, DO_SUB) +DO_ZPZZ_D(sve_sub_zpzz_d, uint64_t, DO_SUB) + +DO_ZPZZ(sve_smax_zpzz_b, int8_t, H1, DO_MAX) +DO_ZPZZ(sve_smax_zpzz_h, int16_t, H1_2, DO_MAX) +DO_ZPZZ(sve_smax_zpzz_s, int32_t, H1_4, DO_MAX) +DO_ZPZZ_D(sve_smax_zpzz_d, int64_t, DO_MAX) + +DO_ZPZZ(sve_umax_zpzz_b, uint8_t, H1, DO_MAX) +DO_ZPZZ(sve_umax_zpzz_h, uint16_t, H1_2, DO_MAX) +DO_ZPZZ(sve_umax_zpzz_s, uint32_t, H1_4, DO_MAX) +DO_ZPZZ_D(sve_umax_zpzz_d, uint64_t, DO_MAX) + +DO_ZPZZ(sve_smin_zpzz_b, int8_t, H1, DO_MIN) +DO_ZPZZ(sve_smin_zpzz_h, int16_t, H1_2, DO_MIN) +DO_ZPZZ(sve_smin_zpzz_s, int32_t, H1_4, DO_MIN) +DO_ZPZZ_D(sve_smin_zpzz_d, int64_t, DO_MIN) + +DO_ZPZZ(sve_umin_zpzz_b, uint8_t, H1, DO_MIN) +DO_ZPZZ(sve_umin_zpzz_h, uint16_t, H1_2, DO_MIN) +DO_ZPZZ(sve_umin_zpzz_s, uint32_t, H1_4, DO_MIN) +DO_ZPZZ_D(sve_umin_zpzz_d, uint64_t, DO_MIN) + +DO_ZPZZ(sve_sabd_zpzz_b, int8_t, H1, DO_ABD) +DO_ZPZZ(sve_sabd_zpzz_h, int16_t, H1_2, DO_ABD) +DO_ZPZZ(sve_sabd_zpzz_s, int32_t, H1_4, DO_ABD) +DO_ZPZZ_D(sve_sabd_zpzz_d, int64_t, DO_ABD) + +DO_ZPZZ(sve_uabd_zpzz_b, uint8_t, H1, DO_ABD) +DO_ZPZZ(sve_uabd_zpzz_h, uint16_t, H1_2, DO_ABD) +DO_ZPZZ(sve_uabd_zpzz_s, uint32_t, H1_4, DO_ABD) +DO_ZPZZ_D(sve_uabd_zpzz_d, uint64_t, DO_ABD) + +/* Because the computation type is at least twice as large as required, + these work for both signed and unsigned source types. */ +static inline uint8_t do_mulh_b(int32_t n, int32_t m) +{ + return (n * m) >> 8; +} + +static inline uint16_t do_mulh_h(int32_t n, int32_t m) +{ + return (n * m) >> 16; +} + +static inline uint32_t do_mulh_s(int64_t n, int64_t m) +{ + return (n * m) >> 32; +} + +static inline uint64_t do_smulh_d(uint64_t n, uint64_t m) +{ + uint64_t lo, hi; + muls64(&lo, &hi, n, m); + return hi; +} + +static inline uint64_t do_umulh_d(uint64_t n, uint64_t m) +{ + uint64_t lo, hi; + mulu64(&lo, &hi, n, m); + return hi; +} + +DO_ZPZZ(sve_mul_zpzz_b, uint8_t, H1, DO_MUL) +DO_ZPZZ(sve_mul_zpzz_h, uint16_t, H1_2, DO_MUL) +DO_ZPZZ(sve_mul_zpzz_s, uint32_t, H1_4, DO_MUL) +DO_ZPZZ_D(sve_mul_zpzz_d, uint64_t, DO_MUL) + +DO_ZPZZ(sve_smulh_zpzz_b, int8_t, H1, do_mulh_b) +DO_ZPZZ(sve_smulh_zpzz_h, int16_t, H1_2, do_mulh_h) +DO_ZPZZ(sve_smulh_zpzz_s, int32_t, H1_4, do_mulh_s) +DO_ZPZZ_D(sve_smulh_zpzz_d, uint64_t, do_smulh_d) + +DO_ZPZZ(sve_umulh_zpzz_b, uint8_t, H1, do_mulh_b) +DO_ZPZZ(sve_umulh_zpzz_h, uint16_t, H1_2, do_mulh_h) +DO_ZPZZ(sve_umulh_zpzz_s, uint32_t, H1_4, do_mulh_s) +DO_ZPZZ_D(sve_umulh_zpzz_d, uint64_t, do_umulh_d) + +DO_ZPZZ(sve_sdiv_zpzz_s, int32_t, H1_4, DO_DIV) +DO_ZPZZ_D(sve_sdiv_zpzz_d, int64_t, DO_DIV) + +DO_ZPZZ(sve_udiv_zpzz_s, uint32_t, H1_4, DO_DIV) +DO_ZPZZ_D(sve_udiv_zpzz_d, uint64_t, DO_DIV) + +#undef DO_ZPZZ +#undef DO_ZPZZ_D +#undef DO_AND +#undef DO_ORR +#undef DO_EOR +#undef DO_BIC +#undef DO_ADD +#undef DO_SUB +#undef DO_MAX +#undef DO_MIN +#undef DO_ABD +#undef DO_MUL +#undef DO_DIV + /* Similar to the ARM LastActiveElement pseudocode function, except the result is multiplied by the element size. This includes the not found indication; e.g. not found for esz=3D3 is -8. */ diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 4bb40da119..bba04ea0af 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -227,6 +227,74 @@ static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz= *a, uint32_t insn) return do_vector3_z(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm); } =20 +/* + *** SVE Integer Arithmetic - Binary Predicated Group + */ + +static bool do_zpzz_ool(DisasContext *s, arg_rprr_esz *a, gen_helper_gvec_= 4 *fn) +{ + unsigned vsz =3D vec_full_reg_size(s); + if (fn =3D=3D NULL) { + return false; + } + if (sve_access_check(s)) { + tcg_gen_gvec_4_ool(vec_full_reg_offset(s, a->rd), + vec_full_reg_offset(s, a->rn), + vec_full_reg_offset(s, a->rm), + pred_full_reg_offset(s, a->pg), + vsz, vsz, 0, fn); + } + return true; +} + +#define DO_ZPZZ(NAME, name) \ +static bool trans_##NAME##_zpzz(DisasContext *s, arg_rprr_esz *a, \ + uint32_t insn) \ +{ \ + static gen_helper_gvec_4 * const fns[4] =3D { = \ + gen_helper_sve_##name##_zpzz_b, gen_helper_sve_##name##_zpzz_h, \ + gen_helper_sve_##name##_zpzz_s, gen_helper_sve_##name##_zpzz_d, \ + }; \ + return do_zpzz_ool(s, a, fns[a->esz]); \ +} + +DO_ZPZZ(AND, and) +DO_ZPZZ(EOR, eor) +DO_ZPZZ(ORR, orr) +DO_ZPZZ(BIC, bic) + +DO_ZPZZ(ADD, add) +DO_ZPZZ(SUB, sub) + +DO_ZPZZ(SMAX, smax) +DO_ZPZZ(UMAX, umax) +DO_ZPZZ(SMIN, smin) +DO_ZPZZ(UMIN, umin) +DO_ZPZZ(SABD, sabd) +DO_ZPZZ(UABD, uabd) + +DO_ZPZZ(MUL, mul) +DO_ZPZZ(SMULH, smulh) +DO_ZPZZ(UMULH, umulh) + +static bool trans_SDIV_zpzz(DisasContext *s, arg_rprr_esz *a, uint32_t ins= n) +{ + static gen_helper_gvec_4 * const fns[4] =3D { + NULL, NULL, gen_helper_sve_sdiv_zpzz_s, gen_helper_sve_sdiv_zpzz_d + }; + return do_zpzz_ool(s, a, fns[a->esz]); +} + +static bool trans_UDIV_zpzz(DisasContext *s, arg_rprr_esz *a, uint32_t ins= n) +{ + static gen_helper_gvec_4 * const fns[4] =3D { + NULL, NULL, gen_helper_sve_udiv_zpzz_s, gen_helper_sve_udiv_zpzz_d + }; + return do_zpzz_ool(s, a, fns[a->esz]); +} + +#undef DO_ZPZZ + /* *** SVE Predicate Logical Operations Group */ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index a390abb537..c444357c82 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -24,6 +24,10 @@ =20 %imm9_16_10 16:s6 10:3 =20 +# Either a copy of rd (at bit 0), or a different source +# as propagated via the MOVPRFX instruction. +%reg_movprfx 0:5 + ########################################################################### # Named attribute sets. These are used to make nice(er) names # when creating helpers common to those for the individual @@ -33,6 +37,7 @@ &rri rd rn imm &rrr_esz rd rn rm esz &rprr_s rd pg rn rm s +&rprr_esz rd pg rn rm esz =20 ########################################################################### # Named instruction formats. These are generally used to @@ -50,6 +55,12 @@ # Three predicate operand, with governing predicate, flag setting @pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s =20 +# Two register operand, with governing predicate, vector element size +@rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \ + &rprr_esz rn=3D%reg_movprfx +@rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \ + &rprr_esz rm=3D%reg_movprfx + # Basic Load/Store with 9-bit immediate offset @pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \ &rri imm=3D%imm9_16_10 @@ -59,6 +70,37 @@ ########################################################################### # Instruction patterns. Grouped according to the SVE encodingindex.xhtml. =20 +### SVE Integer Arithmetic - Binary Predicated Group + +# SVE bitwise logical vector operations (predicated) +ORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm +EOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm +AND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm +BIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm + +# SVE integer add/subtract vectors (predicated) +ADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm +SUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm +SUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR + +# SVE integer min/max/difference (predicated) +SMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm +UMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm +SMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm +UMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm +SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm +UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm + +# SVE integer multiply/divide (predicated) +MUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm +SMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm +UMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm +# Note that divide requires size >=3D 2; below 2 is unallocated. +SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm +UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm +SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDI= VR +UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDI= VR + ### SVE Logical - Unpredicated Group =20 # SVE bitwise logical operations (unpredicated) --=20 2.17.0 From nobody Wed Oct 29 22:55:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526510423780584.8150664570322; Wed, 16 May 2018 15:40:23 -0700 (PDT) Received: from localhost ([::1]:44821 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ55n-0006P4-8X for importer@patchew.org; Wed, 16 May 2018 18:40:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41070) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4wF-0007dn-OV for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ4wD-0007RS-4t for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:27 -0400 Received: from mail-pf0-x230.google.com ([2607:f8b0:400e:c00::230]:40331) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ4wC-0007Ql-DC for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:24 -0400 Received: by mail-pf0-x230.google.com with SMTP id f189-v6so1051980pfa.7 for ; Wed, 16 May 2018 15:30:24 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1hlcX/gG9mGYvuUO+jDVkljJBNZqveRr6WJLnX1Q8Nw=; b=jVzKrkfcSQ4rdh36NX+G7SOs4QQEeW89k/orblbK5ONKCM2YVovP0MbzUleLjP1aRx mjpkObVbK8ebLb9EcajaojELhfCZ7fh6aq7UMFhw5ES8wSqM8p+0PSgt0huoYoMvbt9K sFNTegj2iy+5m6ZRjDTUfQILhRpWV5G5XCUBI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1hlcX/gG9mGYvuUO+jDVkljJBNZqveRr6WJLnX1Q8Nw=; b=aCnrSw3RfN1OBQKXhrnLtxh4UpJgDsXY55dg1UuMDQRhTbssO9IKrxPYkWK6LsF+CC /jH9fNN0ZowrD+CccU6A4iC6OM6nkp5ehLpJC4LyVq/Tp1BP70hjWLf3vOBsOhcfkL+w W7cEC0ElRPzm4BA2Sru9KkrH+Q4gNCQGcFFqqmJrJkW6ABq4d2HzZUGRyiHylzLUxH3V 62mz9cz6EG2GfWIBDQkOTjxVpFGxfYrA5eZUJZYYmb0G5C+rcSdjkahlYrPiAb16jt7u WEMc4WEVyR83MnaFRwSpWJ8Vamdh7tdWp6jARKKqFXOK00NgXlZY6rEHY4ttJbA/LUnc 0qlA== X-Gm-Message-State: ALKqPwcGjp9I5Xyxx9G2lPeBGhg0WLfEuD3Pinsgf5nTOJd1CHmz5ik9 dRVM6N9zalK8eBW/54kdut5Er/DZqSA= X-Google-Smtp-Source: AB8JxZpv2N5zBeEUpL+1TmEMnN5tVD6bKpIWd65LwEWrutqMQlS3QZo70DRNRHhga2sH6zSkBTFA9Q== X-Received: by 2002:a62:6a0a:: with SMTP id f10-v6mr2697697pfc.99.1526509822921; Wed, 16 May 2018 15:30:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:29:49 -0700 Message-Id: <20180516223007.10256-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::230 Subject: [Qemu-devel] [PATCH v3-a 09/27] target/arm: Implement SVE Integer Reduction Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Excepting MOVPRFX, which isn't a reduction. Presumably it is placed within the group because of its encoding. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 44 ++++++++++++++++++ target/arm/sve_helper.c | 91 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 68 ++++++++++++++++++++++++++++ target/arm/sve.decode | 22 +++++++++ 4 files changed, 225 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 5b82ba1501..6b6bbeb272 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -168,6 +168,50 @@ DEF_HELPER_FLAGS_5(sve_udiv_zpzz_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_udiv_zpzz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_3(sve_orv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_orv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_orv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_orv_d, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(sve_eorv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_eorv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_eorv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_eorv_d, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(sve_andv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_andv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_andv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_andv_d, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(sve_saddv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_saddv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_saddv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(sve_uaddv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_uaddv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_uaddv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_uaddv_d, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(sve_smaxv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_smaxv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_smaxv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_smaxv_d, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(sve_umaxv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_umaxv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_umaxv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_umaxv_d, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(sve_sminv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_sminv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_sminv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_sminv_d, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(sve_uminv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_uminv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_uminv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_uminv_d, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) + DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index b8c8a06122..c1719e407a 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -298,6 +298,97 @@ DO_ZPZZ_D(sve_udiv_zpzz_d, uint64_t, DO_DIV) =20 #undef DO_ZPZZ #undef DO_ZPZZ_D + +/* Two-operand reduction expander, controlled by a predicate. + * The difference between TYPERED and TYPERET has to do with + * sign-extension. E.g. for SMAX, TYPERED must be signed, + * but TYPERET must be unsigned so that e.g. a 32-bit value + * is not sign-extended to the ABI uint64_t return type. + */ +/* ??? If we were to vectorize this by hand the reduction ordering + * would change. For integer operands, this is perfectly fine. + */ +#define DO_VPZ(NAME, TYPEELT, TYPERED, TYPERET, H, INIT, OP) \ +uint64_t HELPER(NAME)(void *vn, void *vg, uint32_t desc) \ +{ \ + intptr_t i, opr_sz =3D simd_oprsz(desc); \ + TYPERED ret =3D INIT; \ + for (i =3D 0; i < opr_sz; ) { \ + uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); \ + do { \ + if (pg & 1) { \ + TYPEELT nn =3D *(TYPEELT *)(vn + H(i)); \ + ret =3D OP(ret, nn); \ + } \ + i +=3D sizeof(TYPEELT), pg >>=3D sizeof(TYPEELT); \ + } while (i & 15); \ + } \ + return (TYPERET)ret; \ +} + +#define DO_VPZ_D(NAME, TYPEE, TYPER, INIT, OP) \ +uint64_t HELPER(NAME)(void *vn, void *vg, uint32_t desc) \ +{ \ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; \ + TYPEE *n =3D vn; \ + uint8_t *pg =3D vg; \ + TYPER ret =3D INIT; \ + for (i =3D 0; i < opr_sz; i +=3D 1) { \ + if (pg[H1(i)] & 1) { \ + TYPEE nn =3D n[i]; \ + ret =3D OP(ret, nn); \ + } \ + } \ + return ret; \ +} + +DO_VPZ(sve_orv_b, uint8_t, uint8_t, uint8_t, H1, 0, DO_ORR) +DO_VPZ(sve_orv_h, uint16_t, uint16_t, uint16_t, H1_2, 0, DO_ORR) +DO_VPZ(sve_orv_s, uint32_t, uint32_t, uint32_t, H1_4, 0, DO_ORR) +DO_VPZ_D(sve_orv_d, uint64_t, uint64_t, 0, DO_ORR) + +DO_VPZ(sve_eorv_b, uint8_t, uint8_t, uint8_t, H1, 0, DO_EOR) +DO_VPZ(sve_eorv_h, uint16_t, uint16_t, uint16_t, H1_2, 0, DO_EOR) +DO_VPZ(sve_eorv_s, uint32_t, uint32_t, uint32_t, H1_4, 0, DO_EOR) +DO_VPZ_D(sve_eorv_d, uint64_t, uint64_t, 0, DO_EOR) + +DO_VPZ(sve_andv_b, uint8_t, uint8_t, uint8_t, H1, -1, DO_AND) +DO_VPZ(sve_andv_h, uint16_t, uint16_t, uint16_t, H1_2, -1, DO_AND) +DO_VPZ(sve_andv_s, uint32_t, uint32_t, uint32_t, H1_4, -1, DO_AND) +DO_VPZ_D(sve_andv_d, uint64_t, uint64_t, -1, DO_AND) + +DO_VPZ(sve_saddv_b, int8_t, uint64_t, uint64_t, H1, 0, DO_ADD) +DO_VPZ(sve_saddv_h, int16_t, uint64_t, uint64_t, H1_2, 0, DO_ADD) +DO_VPZ(sve_saddv_s, int32_t, uint64_t, uint64_t, H1_4, 0, DO_ADD) + +DO_VPZ(sve_uaddv_b, uint8_t, uint64_t, uint64_t, H1, 0, DO_ADD) +DO_VPZ(sve_uaddv_h, uint16_t, uint64_t, uint64_t, H1_2, 0, DO_ADD) +DO_VPZ(sve_uaddv_s, uint32_t, uint64_t, uint64_t, H1_4, 0, DO_ADD) +DO_VPZ_D(sve_uaddv_d, uint64_t, uint64_t, 0, DO_ADD) + +DO_VPZ(sve_smaxv_b, int8_t, int8_t, uint8_t, H1, INT8_MIN, DO_MAX) +DO_VPZ(sve_smaxv_h, int16_t, int16_t, uint16_t, H1_2, INT16_MIN, DO_MAX) +DO_VPZ(sve_smaxv_s, int32_t, int32_t, uint32_t, H1_4, INT32_MIN, DO_MAX) +DO_VPZ_D(sve_smaxv_d, int64_t, int64_t, INT64_MIN, DO_MAX) + +DO_VPZ(sve_umaxv_b, uint8_t, uint8_t, uint8_t, H1, 0, DO_MAX) +DO_VPZ(sve_umaxv_h, uint16_t, uint16_t, uint16_t, H1_2, 0, DO_MAX) +DO_VPZ(sve_umaxv_s, uint32_t, uint32_t, uint32_t, H1_4, 0, DO_MAX) +DO_VPZ_D(sve_umaxv_d, uint64_t, uint64_t, 0, DO_MAX) + +DO_VPZ(sve_sminv_b, int8_t, int8_t, uint8_t, H1, INT8_MAX, DO_MIN) +DO_VPZ(sve_sminv_h, int16_t, int16_t, uint16_t, H1_2, INT16_MAX, DO_MIN) +DO_VPZ(sve_sminv_s, int32_t, int32_t, uint32_t, H1_4, INT32_MAX, DO_MIN) +DO_VPZ_D(sve_sminv_d, int64_t, int64_t, INT64_MAX, DO_MIN) + +DO_VPZ(sve_uminv_b, uint8_t, uint8_t, uint8_t, H1, -1, DO_MIN) +DO_VPZ(sve_uminv_h, uint16_t, uint16_t, uint16_t, H1_2, -1, DO_MIN) +DO_VPZ(sve_uminv_s, uint32_t, uint32_t, uint32_t, H1_4, -1, DO_MIN) +DO_VPZ_D(sve_uminv_d, uint64_t, uint64_t, -1, DO_MIN) + +#undef DO_VPZ +#undef DO_VPZ_D + #undef DO_AND #undef DO_ORR #undef DO_EOR diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index bba04ea0af..66ef01712d 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -295,6 +295,74 @@ static bool trans_UDIV_zpzz(DisasContext *s, arg_rprr_= esz *a, uint32_t insn) =20 #undef DO_ZPZZ =20 +/* + *** SVE Integer Reduction Group + */ + +typedef void gen_helper_gvec_reduc(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_i32); +static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a, + gen_helper_gvec_reduc *fn) +{ + unsigned vsz =3D vec_full_reg_size(s); + TCGv_ptr t_zn, t_pg; + TCGv_i32 desc; + TCGv_i64 temp; + + if (fn =3D=3D NULL) { + return false; + } + if (!sve_access_check(s)) { + return true; + } + + desc =3D tcg_const_i32(simd_desc(vsz, vsz, 0)); + temp =3D tcg_temp_new_i64(); + t_zn =3D tcg_temp_new_ptr(); + t_pg =3D tcg_temp_new_ptr(); + + tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn)); + tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg)); + fn(temp, t_zn, t_pg, desc); + tcg_temp_free_ptr(t_zn); + tcg_temp_free_ptr(t_pg); + tcg_temp_free_i32(desc); + + write_fp_dreg(s, a->rd, temp); + tcg_temp_free_i64(temp); + return true; +} + +#define DO_VPZ(NAME, name) \ +static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a, uint32_t insn) \ +{ \ + static gen_helper_gvec_reduc * const fns[4] =3D { = \ + gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \ + gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \ + }; \ + return do_vpz_ool(s, a, fns[a->esz]); \ +} + +DO_VPZ(ORV, orv) +DO_VPZ(ANDV, andv) +DO_VPZ(EORV, eorv) + +DO_VPZ(UADDV, uaddv) +DO_VPZ(SMAXV, smaxv) +DO_VPZ(UMAXV, umaxv) +DO_VPZ(SMINV, sminv) +DO_VPZ(UMINV, uminv) + +static bool trans_SADDV(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + static gen_helper_gvec_reduc * const fns[4] =3D { + gen_helper_sve_saddv_b, gen_helper_sve_saddv_h, + gen_helper_sve_saddv_s, NULL + }; + return do_vpz_ool(s, a, fns[a->esz]); +} + +#undef DO_VPZ + /* *** SVE Predicate Logical Operations Group */ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index c444357c82..ba27ff0979 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -36,6 +36,7 @@ &rr_esz rd rn esz &rri rd rn imm &rrr_esz rd rn rm esz +&rpr_esz rd pg rn esz &rprr_s rd pg rn rm s &rprr_esz rd pg rn rm esz =20 @@ -61,6 +62,9 @@ @rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \ &rprr_esz rm=3D%reg_movprfx =20 +# One register operand, with governing predicate, vector element size +@rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz + # Basic Load/Store with 9-bit immediate offset @pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \ &rri imm=3D%imm9_16_10 @@ -101,6 +105,24 @@ UDIV_zpzz 00000100 .. 010 101 000 ... ..... ....= . @rdn_pg_rm SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDI= VR UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDI= VR =20 +### SVE Integer Reduction Group + +# SVE bitwise logical reduction (predicated) +ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn +EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn +ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn + +# SVE integer add reduction (predicated) +# Note that saddv requires size !=3D 3. +UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn +SADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn + +# SVE integer min/max reduction (predicated) +SMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn +UMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn +SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn +UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn + ### SVE Logical - Unpredicated Group =20 # SVE bitwise logical operations (unpredicated) --=20 2.17.0 From nobody Wed Oct 29 22:55:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526510945625717.4847317933705; Wed, 16 May 2018 15:49:05 -0700 (PDT) Received: from localhost ([::1]:45097 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ5EG-0005Sp-Ol for importer@patchew.org; Wed, 16 May 2018 18:49:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41140) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4wI-0007gT-BF for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ4wE-0007Se-TH for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:30 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:41222) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ4wE-0007Rm-10 for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:26 -0400 Received: by mail-pf0-x242.google.com with SMTP id v63-v6so1047963pfk.8 for ; Wed, 16 May 2018 15:30:25 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LP6xP2qM9de66t560+OwJCDT8ovvM2+ohWFbkSQlNoI=; b=DMhmBl2UCmvtNdcwzDnFOab7sI4Qh1JbjJcSIQ6kHyUsBkUdxKVP1BpZ/DtJMbCExQ mWn4u18AiBL3cyNpe3GKeNDyiTzTg4q4ZYAaWxw6tkmT4wJ2g57D58K3N2H6uSaxwqlE aJBFJ7u48dj3aTuhQz4IW8CbPWgIHCHC/X/t0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LP6xP2qM9de66t560+OwJCDT8ovvM2+ohWFbkSQlNoI=; b=CyR3qGatK89ZOnX0+yYZI/sG+LZvEi93IlhkHjSwaQBJkNsyWlLAZP29ul6mWOXjyk STFSgzy9OZxelu2gQP42RMjN88dZcGIGTB5wItszAmJGinLaZ8KKqOL5cfdiz8lQk+As NormdlVe3LBNXU16FBstFZfk7qhjt2wAuC0q5OFfQj9y5FpxAI7bGiQyk6cD+L0o9BrT XCWgfLQLEM1Pbzm+/xEQwmC6g7OvCx5ZxIiaB7E/hZPyw84NxhTzb21cSLbWY0S7CmXk zGe+jeYo/6r0Y7tQg1OOCdjgd28+XSHTT3L5wf/mwtcylL0qv4Aa+45NcXrM3Ao8jvzh hwKQ== X-Gm-Message-State: ALKqPwe1b1fBQepU3C/xM4vZ3Pg+KHGZZKIQWo80LVKCQBJnA4pWGzhM h7w5ii03B0v5Sjy1hY3dN/piQ3jJqBg= X-Google-Smtp-Source: AB8JxZq7NiCbpMw94pUmrChuL8g72swT0a4wmkYNJIrTDlzlAgo3gD+vEcYwq4iWlx8wFUqX/Om99Q== X-Received: by 2002:a63:6bc7:: with SMTP id g190-v6mr2155508pgc.230.1526509824309; Wed, 16 May 2018 15:30:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:29:50 -0700 Message-Id: <20180516223007.10256-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v3-a 10/27] target/arm: Implement SVE bitwise shift by immediate (predicated) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 25 ++++ target/arm/sve_helper.c | 264 +++++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 130 ++++++++++++++++++ target/arm/sve.decode | 26 ++++ 4 files changed, 445 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 6b6bbeb272..b3c89579af 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -212,6 +212,31 @@ DEF_HELPER_FLAGS_3(sve_uminv_h, TCG_CALL_NO_RWG, i64, = ptr, ptr, i32) DEF_HELPER_FLAGS_3(sve_uminv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) DEF_HELPER_FLAGS_3(sve_uminv_d, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_3(sve_clr_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_clr_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_clr_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_clr_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve_asr_zpzi_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(sve_asr_zpzi_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(sve_asr_zpzi_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(sve_asr_zpzi_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) + +DEF_HELPER_FLAGS_4(sve_lsr_zpzi_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(sve_lsr_zpzi_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(sve_lsr_zpzi_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(sve_lsr_zpzi_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) + +DEF_HELPER_FLAGS_4(sve_lsl_zpzi_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(sve_lsl_zpzi_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(sve_lsl_zpzi_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(sve_lsl_zpzi_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) + +DEF_HELPER_FLAGS_4(sve_asrd_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_asrd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_asrd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_asrd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index c1719e407a..b6b9a08965 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -93,6 +93,150 @@ uint32_t HELPER(sve_predtest)(void *vd, void *vg, uint3= 2_t words) return flags; } =20 +/* Expand active predicate bits to bytes, for byte elements. + * for (i =3D 0; i < 256; ++i) { + * unsigned long m =3D 0; + * for (j =3D 0; j < 8; j++) { + * if ((i >> j) & 1) { + * m |=3D 0xfful << (j << 3); + * } + * } + * printf("0x%016lx,\n", m); + * } + */ +static inline uint64_t expand_pred_b(uint8_t byte) +{ + static const uint64_t word[256] =3D { + 0x0000000000000000, 0x00000000000000ff, 0x000000000000ff00, + 0x000000000000ffff, 0x0000000000ff0000, 0x0000000000ff00ff, + 0x0000000000ffff00, 0x0000000000ffffff, 0x00000000ff000000, + 0x00000000ff0000ff, 0x00000000ff00ff00, 0x00000000ff00ffff, + 0x00000000ffff0000, 0x00000000ffff00ff, 0x00000000ffffff00, + 0x00000000ffffffff, 0x000000ff00000000, 0x000000ff000000ff, + 0x000000ff0000ff00, 0x000000ff0000ffff, 0x000000ff00ff0000, + 0x000000ff00ff00ff, 0x000000ff00ffff00, 0x000000ff00ffffff, + 0x000000ffff000000, 0x000000ffff0000ff, 0x000000ffff00ff00, + 0x000000ffff00ffff, 0x000000ffffff0000, 0x000000ffffff00ff, + 0x000000ffffffff00, 0x000000ffffffffff, 0x0000ff0000000000, + 0x0000ff00000000ff, 0x0000ff000000ff00, 0x0000ff000000ffff, + 0x0000ff0000ff0000, 0x0000ff0000ff00ff, 0x0000ff0000ffff00, + 0x0000ff0000ffffff, 0x0000ff00ff000000, 0x0000ff00ff0000ff, + 0x0000ff00ff00ff00, 0x0000ff00ff00ffff, 0x0000ff00ffff0000, + 0x0000ff00ffff00ff, 0x0000ff00ffffff00, 0x0000ff00ffffffff, + 0x0000ffff00000000, 0x0000ffff000000ff, 0x0000ffff0000ff00, + 0x0000ffff0000ffff, 0x0000ffff00ff0000, 0x0000ffff00ff00ff, + 0x0000ffff00ffff00, 0x0000ffff00ffffff, 0x0000ffffff000000, + 0x0000ffffff0000ff, 0x0000ffffff00ff00, 0x0000ffffff00ffff, + 0x0000ffffffff0000, 0x0000ffffffff00ff, 0x0000ffffffffff00, + 0x0000ffffffffffff, 0x00ff000000000000, 0x00ff0000000000ff, + 0x00ff00000000ff00, 0x00ff00000000ffff, 0x00ff000000ff0000, + 0x00ff000000ff00ff, 0x00ff000000ffff00, 0x00ff000000ffffff, + 0x00ff0000ff000000, 0x00ff0000ff0000ff, 0x00ff0000ff00ff00, + 0x00ff0000ff00ffff, 0x00ff0000ffff0000, 0x00ff0000ffff00ff, + 0x00ff0000ffffff00, 0x00ff0000ffffffff, 0x00ff00ff00000000, + 0x00ff00ff000000ff, 0x00ff00ff0000ff00, 0x00ff00ff0000ffff, + 0x00ff00ff00ff0000, 0x00ff00ff00ff00ff, 0x00ff00ff00ffff00, + 0x00ff00ff00ffffff, 0x00ff00ffff000000, 0x00ff00ffff0000ff, + 0x00ff00ffff00ff00, 0x00ff00ffff00ffff, 0x00ff00ffffff0000, + 0x00ff00ffffff00ff, 0x00ff00ffffffff00, 0x00ff00ffffffffff, + 0x00ffff0000000000, 0x00ffff00000000ff, 0x00ffff000000ff00, + 0x00ffff000000ffff, 0x00ffff0000ff0000, 0x00ffff0000ff00ff, + 0x00ffff0000ffff00, 0x00ffff0000ffffff, 0x00ffff00ff000000, + 0x00ffff00ff0000ff, 0x00ffff00ff00ff00, 0x00ffff00ff00ffff, + 0x00ffff00ffff0000, 0x00ffff00ffff00ff, 0x00ffff00ffffff00, + 0x00ffff00ffffffff, 0x00ffffff00000000, 0x00ffffff000000ff, + 0x00ffffff0000ff00, 0x00ffffff0000ffff, 0x00ffffff00ff0000, + 0x00ffffff00ff00ff, 0x00ffffff00ffff00, 0x00ffffff00ffffff, + 0x00ffffffff000000, 0x00ffffffff0000ff, 0x00ffffffff00ff00, + 0x00ffffffff00ffff, 0x00ffffffffff0000, 0x00ffffffffff00ff, + 0x00ffffffffffff00, 0x00ffffffffffffff, 0xff00000000000000, + 0xff000000000000ff, 0xff0000000000ff00, 0xff0000000000ffff, + 0xff00000000ff0000, 0xff00000000ff00ff, 0xff00000000ffff00, + 0xff00000000ffffff, 0xff000000ff000000, 0xff000000ff0000ff, + 0xff000000ff00ff00, 0xff000000ff00ffff, 0xff000000ffff0000, + 0xff000000ffff00ff, 0xff000000ffffff00, 0xff000000ffffffff, + 0xff0000ff00000000, 0xff0000ff000000ff, 0xff0000ff0000ff00, + 0xff0000ff0000ffff, 0xff0000ff00ff0000, 0xff0000ff00ff00ff, + 0xff0000ff00ffff00, 0xff0000ff00ffffff, 0xff0000ffff000000, + 0xff0000ffff0000ff, 0xff0000ffff00ff00, 0xff0000ffff00ffff, + 0xff0000ffffff0000, 0xff0000ffffff00ff, 0xff0000ffffffff00, + 0xff0000ffffffffff, 0xff00ff0000000000, 0xff00ff00000000ff, + 0xff00ff000000ff00, 0xff00ff000000ffff, 0xff00ff0000ff0000, + 0xff00ff0000ff00ff, 0xff00ff0000ffff00, 0xff00ff0000ffffff, + 0xff00ff00ff000000, 0xff00ff00ff0000ff, 0xff00ff00ff00ff00, + 0xff00ff00ff00ffff, 0xff00ff00ffff0000, 0xff00ff00ffff00ff, + 0xff00ff00ffffff00, 0xff00ff00ffffffff, 0xff00ffff00000000, + 0xff00ffff000000ff, 0xff00ffff0000ff00, 0xff00ffff0000ffff, + 0xff00ffff00ff0000, 0xff00ffff00ff00ff, 0xff00ffff00ffff00, + 0xff00ffff00ffffff, 0xff00ffffff000000, 0xff00ffffff0000ff, + 0xff00ffffff00ff00, 0xff00ffffff00ffff, 0xff00ffffffff0000, + 0xff00ffffffff00ff, 0xff00ffffffffff00, 0xff00ffffffffffff, + 0xffff000000000000, 0xffff0000000000ff, 0xffff00000000ff00, + 0xffff00000000ffff, 0xffff000000ff0000, 0xffff000000ff00ff, + 0xffff000000ffff00, 0xffff000000ffffff, 0xffff0000ff000000, + 0xffff0000ff0000ff, 0xffff0000ff00ff00, 0xffff0000ff00ffff, + 0xffff0000ffff0000, 0xffff0000ffff00ff, 0xffff0000ffffff00, + 0xffff0000ffffffff, 0xffff00ff00000000, 0xffff00ff000000ff, + 0xffff00ff0000ff00, 0xffff00ff0000ffff, 0xffff00ff00ff0000, + 0xffff00ff00ff00ff, 0xffff00ff00ffff00, 0xffff00ff00ffffff, + 0xffff00ffff000000, 0xffff00ffff0000ff, 0xffff00ffff00ff00, + 0xffff00ffff00ffff, 0xffff00ffffff0000, 0xffff00ffffff00ff, + 0xffff00ffffffff00, 0xffff00ffffffffff, 0xffffff0000000000, + 0xffffff00000000ff, 0xffffff000000ff00, 0xffffff000000ffff, + 0xffffff0000ff0000, 0xffffff0000ff00ff, 0xffffff0000ffff00, + 0xffffff0000ffffff, 0xffffff00ff000000, 0xffffff00ff0000ff, + 0xffffff00ff00ff00, 0xffffff00ff00ffff, 0xffffff00ffff0000, + 0xffffff00ffff00ff, 0xffffff00ffffff00, 0xffffff00ffffffff, + 0xffffffff00000000, 0xffffffff000000ff, 0xffffffff0000ff00, + 0xffffffff0000ffff, 0xffffffff00ff0000, 0xffffffff00ff00ff, + 0xffffffff00ffff00, 0xffffffff00ffffff, 0xffffffffff000000, + 0xffffffffff0000ff, 0xffffffffff00ff00, 0xffffffffff00ffff, + 0xffffffffffff0000, 0xffffffffffff00ff, 0xffffffffffffff00, + 0xffffffffffffffff, + }; + return word[byte]; +} + +/* Similarly for half-word elements. + * for (i =3D 0; i < 256; ++i) { + * unsigned long m =3D 0; + * if (i & 0xaa) { + * continue; + * } + * for (j =3D 0; j < 8; j +=3D 2) { + * if ((i >> j) & 1) { + * m |=3D 0xfffful << (j << 3); + * } + * } + * printf("[0x%x] =3D 0x%016lx,\n", i, m); + * } + */ +static inline uint64_t expand_pred_h(uint8_t byte) +{ + static const uint64_t word[] =3D { + [0x01] =3D 0x000000000000ffff, [0x04] =3D 0x00000000ffff0000, + [0x05] =3D 0x00000000ffffffff, [0x10] =3D 0x0000ffff00000000, + [0x11] =3D 0x0000ffff0000ffff, [0x14] =3D 0x0000ffffffff0000, + [0x15] =3D 0x0000ffffffffffff, [0x40] =3D 0xffff000000000000, + [0x41] =3D 0xffff00000000ffff, [0x44] =3D 0xffff0000ffff0000, + [0x45] =3D 0xffff0000ffffffff, [0x50] =3D 0xffffffff00000000, + [0x51] =3D 0xffffffff0000ffff, [0x54] =3D 0xffffffffffff0000, + [0x55] =3D 0xffffffffffffffff, + }; + return word[byte & 0x55]; +} + +/* Similarly for single word elements. */ +static inline uint64_t expand_pred_s(uint8_t byte) +{ + static const uint64_t word[] =3D { + [0x01] =3D 0x00000000ffffffffull, + [0x10] =3D 0xffffffff00000000ull, + [0x11] =3D 0xffffffffffffffffull, + }; + return word[byte & 0x11]; +} + #define LOGICAL_PPPP(NAME, FUNC) \ void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, uint32_t desc) \ { \ @@ -484,3 +628,123 @@ uint32_t HELPER(sve_pnext)(void *vd, void *vg, uint32= _t pred_desc) =20 return flags; } + +/* Store zero into every active element of Zd. We will use this for two + * and three-operand predicated instructions for which logic dictates a + * zero result. In particular, logical shift by element size, which is + * otherwise undefined on the host. + * + * For element sizes smaller than uint64_t, we use tables to expand + * the N bits of the controlling predicate to a byte mask, and clear + * those bytes. + */ +void HELPER(sve_clr_b)(void *vd, void *vg, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t *d =3D vd; + uint8_t *pg =3D vg; + for (i =3D 0; i < opr_sz; i +=3D 1) { + d[i] &=3D ~expand_pred_b(pg[H1(i)]); + } +} + +void HELPER(sve_clr_h)(void *vd, void *vg, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t *d =3D vd; + uint8_t *pg =3D vg; + for (i =3D 0; i < opr_sz; i +=3D 1) { + d[i] &=3D ~expand_pred_h(pg[H1(i)]); + } +} + +void HELPER(sve_clr_s)(void *vd, void *vg, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t *d =3D vd; + uint8_t *pg =3D vg; + for (i =3D 0; i < opr_sz; i +=3D 1) { + d[i] &=3D ~expand_pred_s(pg[H1(i)]); + } +} + +void HELPER(sve_clr_d)(void *vd, void *vg, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t *d =3D vd; + uint8_t *pg =3D vg; + for (i =3D 0; i < opr_sz; i +=3D 1) { + if (pg[H1(i)] & 1) { + d[i] =3D 0; + } + } +} + +/* Three-operand expander, immediate operand, controlled by a predicate. + */ +#define DO_ZPZI(NAME, TYPE, H, OP) \ +void HELPER(NAME)(void *vd, void *vn, void *vg, uint32_t desc) \ +{ \ + intptr_t i, opr_sz =3D simd_oprsz(desc); \ + TYPE imm =3D simd_data(desc); \ + for (i =3D 0; i < opr_sz; ) { \ + uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); \ + do { \ + if (pg & 1) { \ + TYPE nn =3D *(TYPE *)(vn + H(i)); \ + *(TYPE *)(vd + H(i)) =3D OP(nn, imm); \ + } \ + i +=3D sizeof(TYPE), pg >>=3D sizeof(TYPE); \ + } while (i & 15); \ + } \ +} + +/* Similarly, specialized for 64-bit operands. */ +#define DO_ZPZI_D(NAME, TYPE, OP) \ +void HELPER(NAME)(void *vd, void *vn, void *vg, uint32_t desc) \ +{ \ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; \ + TYPE *d =3D vd, *n =3D vn; \ + TYPE imm =3D simd_data(desc); \ + uint8_t *pg =3D vg; \ + for (i =3D 0; i < opr_sz; i +=3D 1) { \ + if (pg[H1(i)] & 1) { \ + TYPE nn =3D n[i]; \ + d[i] =3D OP(nn, imm); \ + } \ + } \ +} + +#define DO_SHR(N, M) (N >> M) +#define DO_SHL(N, M) (N << M) + +/* Arithmetic shift right for division. This rounds negative numbers + toward zero as per signed division. Therefore before shifting, + when N is negative, add 2**M-1. */ +#define DO_ASRD(N, M) ((N + (N < 0 ? ((__typeof(N))1 << M) - 1 : 0)) >> M) + +DO_ZPZI(sve_asr_zpzi_b, int8_t, H1, DO_SHR) +DO_ZPZI(sve_asr_zpzi_h, int16_t, H1_2, DO_SHR) +DO_ZPZI(sve_asr_zpzi_s, int32_t, H1_4, DO_SHR) +DO_ZPZI_D(sve_asr_zpzi_d, int64_t, DO_SHR) + +DO_ZPZI(sve_lsr_zpzi_b, uint8_t, H1, DO_SHR) +DO_ZPZI(sve_lsr_zpzi_h, uint16_t, H1_2, DO_SHR) +DO_ZPZI(sve_lsr_zpzi_s, uint32_t, H1_4, DO_SHR) +DO_ZPZI_D(sve_lsr_zpzi_d, uint64_t, DO_SHR) + +DO_ZPZI(sve_lsl_zpzi_b, uint8_t, H1, DO_SHL) +DO_ZPZI(sve_lsl_zpzi_h, uint16_t, H1_2, DO_SHL) +DO_ZPZI(sve_lsl_zpzi_s, uint32_t, H1_4, DO_SHL) +DO_ZPZI_D(sve_lsl_zpzi_d, uint64_t, DO_SHL) + +DO_ZPZI(sve_asrd_b, int8_t, H1, DO_ASRD) +DO_ZPZI(sve_asrd_h, int16_t, H1_2, DO_ASRD) +DO_ZPZI(sve_asrd_s, int32_t, H1_4, DO_ASRD) +DO_ZPZI_D(sve_asrd_d, int64_t, DO_ASRD) + +#undef DO_SHR +#undef DO_SHL +#undef DO_ASRD +#undef DO_ZPZI +#undef DO_ZPZI_D diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 66ef01712d..7607a90a4a 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -33,6 +33,30 @@ #include "trace-tcg.h" #include "translate-a64.h" =20 +/* + * Helpers for extracting complex instruction fields. + */ + +/* See e.g. ASR (immediate, predicated). + * Returns -1 for unallocated encoding; diagnose later. + */ +static int tszimm_esz(int x) +{ + x >>=3D 3; /* discard imm3 */ + return 31 - clz32(x); +} + +static int tszimm_shr(int x) +{ + return (16 << tszimm_esz(x)) - x; +} + +/* See e.g. LSL (immediate, predicated). */ +static int tszimm_shl(int x) +{ + return x - (8 << tszimm_esz(x)); +} + /* * Include the generated decoder. */ @@ -363,6 +387,112 @@ static bool trans_SADDV(DisasContext *s, arg_rpr_esz = *a, uint32_t insn) =20 #undef DO_VPZ =20 +/* + *** SVE Shift by Immediate - Predicated Group + */ + +/* Store zero into every active element of Zd. We will use this for two + * and three-operand predicated instructions for which logic dictates a + * zero result. + */ +static bool do_clr_zp(DisasContext *s, int rd, int pg, int esz) +{ + static gen_helper_gvec_2 * const fns[4] =3D { + gen_helper_sve_clr_b, gen_helper_sve_clr_h, + gen_helper_sve_clr_s, gen_helper_sve_clr_d, + }; + if (sve_access_check(s)) { + unsigned vsz =3D vec_full_reg_size(s); + tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd), + pred_full_reg_offset(s, pg), + vsz, vsz, 0, fns[esz]); + } + return true; +} + +static bool do_zpzi_ool(DisasContext *s, arg_rpri_esz *a, + gen_helper_gvec_3 *fn) +{ + if (sve_access_check(s)) { + unsigned vsz =3D vec_full_reg_size(s); + tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd), + vec_full_reg_offset(s, a->rn), + pred_full_reg_offset(s, a->pg), + vsz, vsz, a->imm, fn); + } + return true; +} + +static bool trans_ASR_zpzi(DisasContext *s, arg_rpri_esz *a, uint32_t insn) +{ + static gen_helper_gvec_3 * const fns[4] =3D { + gen_helper_sve_asr_zpzi_b, gen_helper_sve_asr_zpzi_h, + gen_helper_sve_asr_zpzi_s, gen_helper_sve_asr_zpzi_d, + }; + if (a->esz < 0) { + /* Invalid tsz encoding -- see tszimm_esz. */ + return false; + } + /* Shift by element size is architecturally valid. For + arithmetic right-shift, it's the same as by one less. */ + a->imm =3D MIN(a->imm, (8 << a->esz) - 1); + return do_zpzi_ool(s, a, fns[a->esz]); +} + +static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a, uint32_t insn) +{ + static gen_helper_gvec_3 * const fns[4] =3D { + gen_helper_sve_lsr_zpzi_b, gen_helper_sve_lsr_zpzi_h, + gen_helper_sve_lsr_zpzi_s, gen_helper_sve_lsr_zpzi_d, + }; + if (a->esz < 0) { + return false; + } + /* Shift by element size is architecturally valid. + For logical shifts, it is a zeroing operation. */ + if (a->imm >=3D (8 << a->esz)) { + return do_clr_zp(s, a->rd, a->pg, a->esz); + } else { + return do_zpzi_ool(s, a, fns[a->esz]); + } +} + +static bool trans_LSL_zpzi(DisasContext *s, arg_rpri_esz *a, uint32_t insn) +{ + static gen_helper_gvec_3 * const fns[4] =3D { + gen_helper_sve_lsl_zpzi_b, gen_helper_sve_lsl_zpzi_h, + gen_helper_sve_lsl_zpzi_s, gen_helper_sve_lsl_zpzi_d, + }; + if (a->esz < 0) { + return false; + } + /* Shift by element size is architecturally valid. + For logical shifts, it is a zeroing operation. */ + if (a->imm >=3D (8 << a->esz)) { + return do_clr_zp(s, a->rd, a->pg, a->esz); + } else { + return do_zpzi_ool(s, a, fns[a->esz]); + } +} + +static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a, uint32_t insn) +{ + static gen_helper_gvec_3 * const fns[4] =3D { + gen_helper_sve_asrd_b, gen_helper_sve_asrd_h, + gen_helper_sve_asrd_s, gen_helper_sve_asrd_d, + }; + if (a->esz < 0) { + return false; + } + /* Shift by element size is architecturally valid. For arithmetic + right shift for division, it is a zeroing operation. */ + if (a->imm >=3D (8 << a->esz)) { + return do_clr_zp(s, a->rd, a->pg, a->esz); + } else { + return do_zpzi_ool(s, a, fns[a->esz]); + } +} + /* *** SVE Predicate Logical Operations Group */ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index ba27ff0979..a1791c1d7b 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -22,8 +22,16 @@ ########################################################################### # Named fields. These are primarily for disjoint fields. =20 +%imm6_22_5 22:1 5:5 %imm9_16_10 16:s6 10:3 =20 +# A combination of tsz:imm3 -- extract esize. +%tszimm_esz 22:2 5:5 !function=3Dtszimm_esz +# A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3) +%tszimm_shr 22:2 5:5 !function=3Dtszimm_shr +# A combination of tsz:imm3 -- extract (tsz:imm3) - esize +%tszimm_shl 22:2 5:5 !function=3Dtszimm_shl + # Either a copy of rd (at bit 0), or a different source # as propagated via the MOVPRFX instruction. %reg_movprfx 0:5 @@ -39,6 +47,7 @@ &rpr_esz rd pg rn esz &rprr_s rd pg rn rm s &rprr_esz rd pg rn rm esz +&rpri_esz rd pg rn imm esz =20 ########################################################################### # Named instruction formats. These are generally used to @@ -65,6 +74,11 @@ # One register operand, with governing predicate, vector element size @rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz =20 +# Two register operand, one immediate operand, with predicate, +# element size encoded as TSZHL. User must fill in imm. +@rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 \ + &rpri_esz rn=3D%reg_movprfx esz=3D%tszimm_esz + # Basic Load/Store with 9-bit immediate offset @pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \ &rri imm=3D%imm9_16_10 @@ -123,6 +137,18 @@ UMAXV 00000100 .. 001 001 001 ... ..... ....= . @rd_pg_rn SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn =20 +### SVE Shift by Immediate - Predicated Group + +# SVE bitwise shift by immediate (predicated) +ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... \ + @rdn_pg_tszimm imm=3D%tszimm_shr +LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... \ + @rdn_pg_tszimm imm=3D%tszimm_shr +LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... \ + @rdn_pg_tszimm imm=3D%tszimm_shl +ASRD 00000100 .. 000 100 100 ... .. ... ..... \ + @rdn_pg_tszimm imm=3D%tszimm_shr + ### SVE Logical - Unpredicated Group =20 # SVE bitwise logical operations (unpredicated) --=20 2.17.0 From nobody Wed Oct 29 22:55:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15265106153840.04427652552294603; Wed, 16 May 2018 15:43:35 -0700 (PDT) Received: from localhost ([::1]:44842 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ58w-0000hb-E5 for importer@patchew.org; Wed, 16 May 2018 18:43:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41100) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4wH-0007fB-2M for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ4wF-0007T0-4M for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:29 -0400 Received: from mail-pl0-x231.google.com ([2607:f8b0:400e:c01::231]:41913) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ4wE-0007SL-Sw for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:27 -0400 Received: by mail-pl0-x231.google.com with SMTP id az12-v6so1244479plb.8 for ; Wed, 16 May 2018 15:30:26 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7AC5updE5bB1Jshy6R6nMxGYJxwwQEY9qKd1RRimZss=; b=OjMGal069Gg8pw/fkouqzNKR03SyapZ936TQllcqya1dAwMFbtkfjalaDyAnpvx4hs tHXjS5PCUG5ow5UPhJpKIb638Vf2XF0ZOijnVAuOGg5DQwc8Hwd3R9nMl+WWseRIyuyN YERa51wYTaGMM3oN5J7TKVtbeNZeoRpTQ9vgE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7AC5updE5bB1Jshy6R6nMxGYJxwwQEY9qKd1RRimZss=; b=SsviUSAUCPLzHAatcj6lW3eQ0PAjyKR47mMN0Wy7tngxL4KJFYEYMy6yLWKxijuxFe yJGYhdnEesGh705rdBG53MalA0Neuih+4454pxppajpmkskVi7ykX7M3uF25ViSATbf1 MpJiMcSLIBdNOxhVwduUtTCmTcZWsFFNM1c/IGI/rqPNqbf3aa/KEQDrB/SILTkfXV3l dE4671wvNpm4atxyVV+pd4vybrHLbbP62UWq6RVdCH1rVB0yE1bblLygyfA8tyvQxZUI /RoWM5rgOxHaUDml/hcNYRynrJKAfhgcQWPFuchO180O0VUf7POuQX1Trmb3kvqVXY+q w2LQ== X-Gm-Message-State: ALKqPwftB4LICzUs1i5fm4bnWlPtONFecSt9QFu/eviDknroqKL16BMj 1bZdBxxCmROogiLrSmSCqlLSSpt6fCA= X-Google-Smtp-Source: AB8JxZpakwvWuHZy/hNeolGKNO5v0e0Qf6oLdJpna19sVGciEd8RdnE4jABPovob8QaaSTrnpvtuLQ== X-Received: by 2002:a17:902:8f93:: with SMTP id z19-v6mr2676641plo.166.1526509825543; Wed, 16 May 2018 15:30:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:29:51 -0700 Message-Id: <20180516223007.10256-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::231 Subject: [Qemu-devel] [PATCH v3-a 11/27] target/arm: Implement SVE bitwise shift by vector (predicated) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 27 +++++++++++++++++++++++++++ target/arm/sve_helper.c | 25 +++++++++++++++++++++++++ target/arm/translate-sve.c | 4 ++++ target/arm/sve.decode | 8 ++++++++ 4 files changed, 64 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index b3c89579af..0cc02ee59e 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -168,6 +168,33 @@ DEF_HELPER_FLAGS_5(sve_udiv_zpzz_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_udiv_zpzz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_5(sve_asr_zpzz_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_asr_zpzz_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_asr_zpzz_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_asr_zpzz_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sve_lsr_zpzz_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_lsr_zpzz_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_lsr_zpzz_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_lsr_zpzz_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sve_lsl_zpzz_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_lsl_zpzz_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_lsl_zpzz_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_lsl_zpzz_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_3(sve_orv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) DEF_HELPER_FLAGS_3(sve_orv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) DEF_HELPER_FLAGS_3(sve_orv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index b6b9a08965..ece3a81ad3 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -440,6 +440,28 @@ DO_ZPZZ_D(sve_sdiv_zpzz_d, int64_t, DO_DIV) DO_ZPZZ(sve_udiv_zpzz_s, uint32_t, H1_4, DO_DIV) DO_ZPZZ_D(sve_udiv_zpzz_d, uint64_t, DO_DIV) =20 +/* Note that all bits of the shift are significant + and not modulo the element size. */ +#define DO_ASR(N, M) (N >> MIN(M, sizeof(N) * 8 - 1)) +#define DO_LSR(N, M) (M < sizeof(N) * 8 ? N >> M : 0) +#define DO_LSL(N, M) (M < sizeof(N) * 8 ? N << M : 0) + +DO_ZPZZ(sve_asr_zpzz_b, int8_t, H1, DO_ASR) +DO_ZPZZ(sve_lsr_zpzz_b, uint8_t, H1_2, DO_LSR) +DO_ZPZZ(sve_lsl_zpzz_b, uint8_t, H1_4, DO_LSL) + +DO_ZPZZ(sve_asr_zpzz_h, int16_t, H1, DO_ASR) +DO_ZPZZ(sve_lsr_zpzz_h, uint16_t, H1_2, DO_LSR) +DO_ZPZZ(sve_lsl_zpzz_h, uint16_t, H1_4, DO_LSL) + +DO_ZPZZ(sve_asr_zpzz_s, int32_t, H1, DO_ASR) +DO_ZPZZ(sve_lsr_zpzz_s, uint32_t, H1_2, DO_LSR) +DO_ZPZZ(sve_lsl_zpzz_s, uint32_t, H1_4, DO_LSL) + +DO_ZPZZ_D(sve_asr_zpzz_d, int64_t, DO_ASR) +DO_ZPZZ_D(sve_lsr_zpzz_d, uint64_t, DO_LSR) +DO_ZPZZ_D(sve_lsl_zpzz_d, uint64_t, DO_LSL) + #undef DO_ZPZZ #undef DO_ZPZZ_D =20 @@ -544,6 +566,9 @@ DO_VPZ_D(sve_uminv_d, uint64_t, uint64_t, -1, DO_MIN) #undef DO_ABD #undef DO_MUL #undef DO_DIV +#undef DO_ASR +#undef DO_LSR +#undef DO_LSL =20 /* Similar to the ARM LastActiveElement pseudocode function, except the result is multiplied by the element size. This includes the not found diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 7607a90a4a..f0400e35d9 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -301,6 +301,10 @@ DO_ZPZZ(MUL, mul) DO_ZPZZ(SMULH, smulh) DO_ZPZZ(UMULH, umulh) =20 +DO_ZPZZ(ASR, asr) +DO_ZPZZ(LSR, lsr) +DO_ZPZZ(LSL, lsl) + static bool trans_SDIV_zpzz(DisasContext *s, arg_rprr_esz *a, uint32_t ins= n) { static gen_helper_gvec_4 * const fns[4] =3D { diff --git a/target/arm/sve.decode b/target/arm/sve.decode index a1791c1d7b..8267963b6b 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -149,6 +149,14 @@ LSL_zpzi 00000100 .. 000 011 100 ... .. ... ...= .. \ ASRD 00000100 .. 000 100 100 ... .. ... ..... \ @rdn_pg_tszimm imm=3D%tszimm_shr =20 +# SVE bitwise shift by vector (predicated) +ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm +LSR_zpzz 00000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm +LSL_zpzz 00000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm +ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR +LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR +LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR + ### SVE Logical - Unpredicated Group =20 # SVE bitwise logical operations (unpredicated) --=20 2.17.0 From nobody Wed Oct 29 22:55:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526510398517301.8613518310492; Wed, 16 May 2018 15:39:58 -0700 (PDT) Received: from localhost ([::1]:44820 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ55R-00067E-Ja for importer@patchew.org; Wed, 16 May 2018 18:39:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41176) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4wK-0007io-Gz for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ4wH-0007Tx-3x for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:32 -0400 Received: from mail-pg0-x235.google.com ([2607:f8b0:400e:c05::235]:44038) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ4wG-0007TO-CT for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:29 -0400 Received: by mail-pg0-x235.google.com with SMTP id c22-v6so228478pgn.11 for ; Wed, 16 May 2018 15:30:28 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jn7iQEcALvVjdLYSB5FiKkJpuIIKitvxbTtwkOopkaE=; b=X7R1dc1JIY3Vvh6awzmE88YMEnBUWWDWR/5Ptbo2PQKxHvsbKwfbnEW/Zky55VVAjr E8/mDG1iRyvjYggS4sbQaY5WKtL1tXV+AqMrsM27TQzuyNAFazjHUl2VZxjThqkOOrJt TH4uBqYusWTfY7FkZENryiSEW/bOjM0AaSjWY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jn7iQEcALvVjdLYSB5FiKkJpuIIKitvxbTtwkOopkaE=; b=GGVzw6QahiWIZSV53E87RL8b38l69xFFw4Ygeepa16MCc+6sU67Nk3zCCttpxOj8tr gE/kjBKrJ6GO1DLN/Sp1OZSwt4mqfmFexcvqXc55GaRuquK8SpJUSEcKCDiR9rHfN0X+ ZGGdldVo4pBlIRrkr1F/QakWk+ryFpENnJB1iGERR9o+jOqf5j+MxIRdAdapHvVcdqtI s7UNF3B5i5UpfvU5UO8C4f9n7YoggkyPityMI4wB9coSL7U6OrmV+vDQmBFbG6++dQbZ YVJGYOgCVuUBXLETf8847M+qNLHqzG09mYudN1jEEQXn2I3s1L2HCRuUauXDDeYK9heP GrTA== X-Gm-Message-State: ALKqPwepSpEyZBiIpb+HvldllFPkXbAZdQAoD/3KWLBXqigwyUPmgBxg 6uhuxTdifTMDqfuVPtYiqnUgap+oeas= X-Google-Smtp-Source: AB8JxZoykn9ybeX1h7/8ZmXPnbvtzVpHg7ys5PhWKyNpdckY9euQq+XoNv0G0GawPDexJcUa92zZmA== X-Received: by 2002:a62:78c:: with SMTP id 12-v6mr2751850pfh.178.1526509826989; Wed, 16 May 2018 15:30:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:29:52 -0700 Message-Id: <20180516223007.10256-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::235 Subject: [Qemu-devel] [PATCH v3-a 12/27] target/arm: Implement SVE bitwise shift by wide elements (predicated) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 21 +++++++++++++++++++++ target/arm/sve_helper.c | 35 +++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 24 ++++++++++++++++++++++++ target/arm/sve.decode | 6 ++++++ 4 files changed, 86 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 0cc02ee59e..d516580134 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -195,6 +195,27 @@ DEF_HELPER_FLAGS_5(sve_lsl_zpzz_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_lsl_zpzz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_5(sve_asr_zpzw_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_asr_zpzw_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_asr_zpzw_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sve_lsr_zpzw_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_lsr_zpzw_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_lsr_zpzw_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sve_lsl_zpzw_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_lsl_zpzw_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_lsl_zpzw_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_3(sve_orv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) DEF_HELPER_FLAGS_3(sve_orv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) DEF_HELPER_FLAGS_3(sve_orv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index ece3a81ad3..a5d12603e5 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -465,6 +465,41 @@ DO_ZPZZ_D(sve_lsl_zpzz_d, uint64_t, DO_LSL) #undef DO_ZPZZ #undef DO_ZPZZ_D =20 +/* Three-operand expander, controlled by a predicate, in which the + * third operand is "wide". That is, for D =3D N op M, the same 64-bit + * value of M is used with all of the narrower values of N. + */ +#define DO_ZPZW(NAME, TYPE, TYPEW, H, OP) \ +void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, uint32_t desc) \ +{ \ + intptr_t i, opr_sz =3D simd_oprsz(desc); \ + for (i =3D 0; i < opr_sz; ) { \ + uint8_t pg =3D *(uint8_t *)(vg + H1(i >> 3)); \ + TYPEW mm =3D *(TYPEW *)(vm + i); \ + do { \ + if (pg & 1) { \ + TYPE nn =3D *(TYPE *)(vn + H(i)); \ + *(TYPE *)(vd + H(i)) =3D OP(nn, mm); \ + } \ + i +=3D sizeof(TYPE), pg >>=3D sizeof(TYPE); = \ + } while (i & 7); \ + } \ +} + +DO_ZPZW(sve_asr_zpzw_b, int8_t, uint64_t, H1, DO_ASR) +DO_ZPZW(sve_lsr_zpzw_b, uint8_t, uint64_t, H1, DO_LSR) +DO_ZPZW(sve_lsl_zpzw_b, uint8_t, uint64_t, H1, DO_LSL) + +DO_ZPZW(sve_asr_zpzw_h, int16_t, uint64_t, H1_2, DO_ASR) +DO_ZPZW(sve_lsr_zpzw_h, uint16_t, uint64_t, H1_2, DO_LSR) +DO_ZPZW(sve_lsl_zpzw_h, uint16_t, uint64_t, H1_2, DO_LSL) + +DO_ZPZW(sve_asr_zpzw_s, int32_t, uint64_t, H1_4, DO_ASR) +DO_ZPZW(sve_lsr_zpzw_s, uint32_t, uint64_t, H1_4, DO_LSR) +DO_ZPZW(sve_lsl_zpzw_s, uint32_t, uint64_t, H1_4, DO_LSL) + +#undef DO_ZPZW + /* Two-operand reduction expander, controlled by a predicate. * The difference between TYPERED and TYPERET has to do with * sign-extension. E.g. for SMAX, TYPERED must be signed, diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index f0400e35d9..438df6359e 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -497,6 +497,30 @@ static bool trans_ASRD(DisasContext *s, arg_rpri_esz *= a, uint32_t insn) } } =20 +/* + *** SVE Bitwise Shift - Predicated Group + */ + +#define DO_ZPZW(NAME, name) \ +static bool trans_##NAME##_zpzw(DisasContext *s, arg_rprr_esz *a, \ + uint32_t insn) \ +{ \ + static gen_helper_gvec_4 * const fns[3] =3D { = \ + gen_helper_sve_##name##_zpzw_b, gen_helper_sve_##name##_zpzw_h, \ + gen_helper_sve_##name##_zpzw_s, \ + }; \ + if (a->esz < 0 || a->esz >=3D 3) { = \ + return false; \ + } \ + return do_zpzz_ool(s, a, fns[a->esz]); \ +} + +DO_ZPZW(ASR, asr) +DO_ZPZW(LSR, lsr) +DO_ZPZW(LSL, lsl) + +#undef DO_ZPZW + /* *** SVE Predicate Logical Operations Group */ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 8267963b6b..1de289e55d 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -157,6 +157,12 @@ ASR_zpzz 00000100 .. 010 100 100 ... ..... ....= . @rdm_pg_rn # ASRR LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR =20 +# SVE bitwise shift by wide elements (predicated) +# Note these require size !=3D 3. +ASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm +LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm +LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm + ### SVE Logical - Unpredicated Group =20 # SVE bitwise logical operations (unpredicated) --=20 2.17.0 From nobody Wed Oct 29 22:55:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526510797583785.7933052837863; Wed, 16 May 2018 15:46:37 -0700 (PDT) Received: from localhost ([::1]:44866 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ5Bo-00039y-Py for importer@patchew.org; Wed, 16 May 2018 18:46:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41182) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4wK-0007iy-Lx for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ4wI-0007Uk-7W for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:32 -0400 Received: from mail-pf0-x230.google.com ([2607:f8b0:400e:c00::230]:33911) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ4wH-0007UF-QE for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:30 -0400 Received: by mail-pf0-x230.google.com with SMTP id a14-v6so1058236pfi.1 for ; Wed, 16 May 2018 15:30:29 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/VEy6LkfxsEGTRAmtCOV9nGa+of9Of/uJqK50rkNees=; b=EWziYGYfGOc0My+tlCibhpzlRRSnsOBGaBkFLTT4NO8+yCfOOWdbVZayMEeoqhwlOf OLdCJv+aDgMYdPpUezxsUWckrDm1mT1MpaGBYR5bV/Qk7mlkWsEAtna07G6wmBog5c0N GPw4fDX0EGVbw8lgLQXSXBt3XjXDq2AdtSoHs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/VEy6LkfxsEGTRAmtCOV9nGa+of9Of/uJqK50rkNees=; b=kF9WblUJdsA2cj2XMOm0IsvEIMBX5ioxQ4XsqHHbOG/cJxWNafT29tA1mkC+IXdJy8 sCWgRWzgrjuRr6+OM6Tbfk6QU9pgJVvAEJ4DQOSNECof0s1M4/KwMGLIUtoj7wze3mcQ nllla7zXd+Ul1EmDwORI/d/txmvU/mL2xJwqZW6uE7ZMpNuoONeIIoD+yPppdcjS8WXM VHLaaDcJhLn9DjyJCvPSTWAebUVYxhCLJ3uax9aY33hCpRsroTcM1taA8p8V3UBheUtU oS7Q+yR0PrM+p7s7PQA91VX6FFjAqCINEWdI2O3WpZ1jldxDlQjvXwVrBevXLbaZ7bKz 29yA== X-Gm-Message-State: ALKqPweF6Nst8gjaHYaIyyl3RMmSf2GBRC8jWwwlXXvu/RsVSpIYy0Kv ZVc42uHdo5EeiOSSvNdg1J78ZdqE73k= X-Google-Smtp-Source: AB8JxZqtq4M0vk/E5Qzioxl9At1bfnrQyExJoCwxlD+HheiVsS09ecK3HJQPaz219sC55A8M668f9A== X-Received: by 2002:a62:c413:: with SMTP id y19-v6mr2739127pff.97.1526509828330; Wed, 16 May 2018 15:30:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:29:53 -0700 Message-Id: <20180516223007.10256-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::230 Subject: [Qemu-devel] [PATCH v3-a 13/27] target/arm: Implement SVE Integer Arithmetic - Unary Predicated Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 60 ++++++++++++++++++ target/arm/sve_helper.c | 127 +++++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 113 +++++++++++++++++++++++++++++++++ target/arm/sve.decode | 23 +++++++ 4 files changed, 323 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index d516580134..11644125d1 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -285,6 +285,66 @@ DEF_HELPER_FLAGS_4(sve_asrd_h, TCG_CALL_NO_RWG, void, = ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_asrd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_asrd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_4(sve_cls_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_cls_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_cls_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_cls_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve_clz_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_clz_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_clz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_clz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve_cnt_zpz_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sve_cnt_zpz_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sve_cnt_zpz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sve_cnt_zpz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) + +DEF_HELPER_FLAGS_4(sve_cnot_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_cnot_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_cnot_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_cnot_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve_fabs_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_fabs_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_fabs_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve_fneg_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_fneg_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_fneg_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve_not_zpz_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sve_not_zpz_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sve_not_zpz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sve_not_zpz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) + +DEF_HELPER_FLAGS_4(sve_sxtb_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_sxtb_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_sxtb_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve_uxtb_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_uxtb_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_uxtb_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve_sxth_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_sxth_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve_uxth_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_uxth_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve_sxtw_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_uxtw_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve_abs_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_abs_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_abs_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_abs_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve_neg_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_neg_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_neg_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_neg_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index a5d12603e5..236d21e771 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -500,6 +500,133 @@ DO_ZPZW(sve_lsl_zpzw_s, uint32_t, uint64_t, H1_4, DO_= LSL) =20 #undef DO_ZPZW =20 +/* Fully general two-operand expander, controlled by a predicate. + */ +#define DO_ZPZ(NAME, TYPE, H, OP) \ +void HELPER(NAME)(void *vd, void *vn, void *vg, uint32_t desc) \ +{ \ + intptr_t i, opr_sz =3D simd_oprsz(desc); \ + for (i =3D 0; i < opr_sz; ) { \ + uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); \ + do { \ + if (pg & 1) { \ + TYPE nn =3D *(TYPE *)(vn + H(i)); \ + *(TYPE *)(vd + H(i)) =3D OP(nn); \ + } \ + i +=3D sizeof(TYPE), pg >>=3D sizeof(TYPE); \ + } while (i & 15); \ + } \ +} + +/* Similarly, specialized for 64-bit operands. */ +#define DO_ZPZ_D(NAME, TYPE, OP) \ +void HELPER(NAME)(void *vd, void *vn, void *vg, uint32_t desc) \ +{ \ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; \ + TYPE *d =3D vd, *n =3D vn; \ + uint8_t *pg =3D vg; \ + for (i =3D 0; i < opr_sz; i +=3D 1) { \ + if (pg[H1(i)] & 1) { \ + TYPE nn =3D n[i]; \ + d[i] =3D OP(nn); \ + } \ + } \ +} + +#define DO_CLS_B(N) (clrsb32(N) - 24) +#define DO_CLS_H(N) (clrsb32(N) - 16) + +DO_ZPZ(sve_cls_b, int8_t, H1, DO_CLS_B) +DO_ZPZ(sve_cls_h, int16_t, H1_2, DO_CLS_H) +DO_ZPZ(sve_cls_s, int32_t, H1_4, clrsb32) +DO_ZPZ_D(sve_cls_d, int64_t, clrsb64) + +#define DO_CLZ_B(N) (clz32(N) - 24) +#define DO_CLZ_H(N) (clz32(N) - 16) + +DO_ZPZ(sve_clz_b, uint8_t, H1, DO_CLZ_B) +DO_ZPZ(sve_clz_h, uint16_t, H1_2, DO_CLZ_H) +DO_ZPZ(sve_clz_s, uint32_t, H1_4, clz32) +DO_ZPZ_D(sve_clz_d, uint64_t, clz64) + +DO_ZPZ(sve_cnt_zpz_b, uint8_t, H1, ctpop8) +DO_ZPZ(sve_cnt_zpz_h, uint16_t, H1_2, ctpop16) +DO_ZPZ(sve_cnt_zpz_s, uint32_t, H1_4, ctpop32) +DO_ZPZ_D(sve_cnt_zpz_d, uint64_t, ctpop64) + +#define DO_CNOT(N) (N =3D=3D 0) + +DO_ZPZ(sve_cnot_b, uint8_t, H1, DO_CNOT) +DO_ZPZ(sve_cnot_h, uint16_t, H1_2, DO_CNOT) +DO_ZPZ(sve_cnot_s, uint32_t, H1_4, DO_CNOT) +DO_ZPZ_D(sve_cnot_d, uint64_t, DO_CNOT) + +#define DO_FABS(N) (N & ((__typeof(N))-1 >> 1)) + +DO_ZPZ(sve_fabs_h, uint16_t, H1_2, DO_FABS) +DO_ZPZ(sve_fabs_s, uint32_t, H1_4, DO_FABS) +DO_ZPZ_D(sve_fabs_d, uint64_t, DO_FABS) + +#define DO_FNEG(N) (N ^ ~((__typeof(N))-1 >> 1)) + +DO_ZPZ(sve_fneg_h, uint16_t, H1_2, DO_FNEG) +DO_ZPZ(sve_fneg_s, uint32_t, H1_4, DO_FNEG) +DO_ZPZ_D(sve_fneg_d, uint64_t, DO_FNEG) + +#define DO_NOT(N) (~N) + +DO_ZPZ(sve_not_zpz_b, uint8_t, H1, DO_NOT) +DO_ZPZ(sve_not_zpz_h, uint16_t, H1_2, DO_NOT) +DO_ZPZ(sve_not_zpz_s, uint32_t, H1_4, DO_NOT) +DO_ZPZ_D(sve_not_zpz_d, uint64_t, DO_NOT) + +#define DO_SXTB(N) ((int8_t)N) +#define DO_SXTH(N) ((int16_t)N) +#define DO_SXTS(N) ((int32_t)N) +#define DO_UXTB(N) ((uint8_t)N) +#define DO_UXTH(N) ((uint16_t)N) +#define DO_UXTS(N) ((uint32_t)N) + +DO_ZPZ(sve_sxtb_h, uint16_t, H1_2, DO_SXTB) +DO_ZPZ(sve_sxtb_s, uint32_t, H1_4, DO_SXTB) +DO_ZPZ(sve_sxth_s, uint32_t, H1_4, DO_SXTH) +DO_ZPZ_D(sve_sxtb_d, uint64_t, DO_SXTB) +DO_ZPZ_D(sve_sxth_d, uint64_t, DO_SXTH) +DO_ZPZ_D(sve_sxtw_d, uint64_t, DO_SXTS) + +DO_ZPZ(sve_uxtb_h, uint16_t, H1_2, DO_UXTB) +DO_ZPZ(sve_uxtb_s, uint32_t, H1_4, DO_UXTB) +DO_ZPZ(sve_uxth_s, uint32_t, H1_4, DO_UXTH) +DO_ZPZ_D(sve_uxtb_d, uint64_t, DO_UXTB) +DO_ZPZ_D(sve_uxth_d, uint64_t, DO_UXTH) +DO_ZPZ_D(sve_uxtw_d, uint64_t, DO_UXTS) + +#define DO_ABS(N) (N < 0 ? -N : N) + +DO_ZPZ(sve_abs_b, int8_t, H1, DO_ABS) +DO_ZPZ(sve_abs_h, int16_t, H1_2, DO_ABS) +DO_ZPZ(sve_abs_s, int32_t, H1_4, DO_ABS) +DO_ZPZ_D(sve_abs_d, int64_t, DO_ABS) + +#define DO_NEG(N) (-N) + +DO_ZPZ(sve_neg_b, uint8_t, H1, DO_NEG) +DO_ZPZ(sve_neg_h, uint16_t, H1_2, DO_NEG) +DO_ZPZ(sve_neg_s, uint32_t, H1_4, DO_NEG) +DO_ZPZ_D(sve_neg_d, uint64_t, DO_NEG) + +#undef DO_CLS_B +#undef DO_CLS_H +#undef DO_CLZ_B +#undef DO_CLZ_H +#undef DO_CNOT +#undef DO_FABS +#undef DO_FNEG +#undef DO_ABS +#undef DO_NEG +#undef DO_ZPZ +#undef DO_ZPZ_D + /* Two-operand reduction expander, controlled by a predicate. * The difference between TYPERED and TYPERET has to do with * sign-extension. E.g. for SMAX, TYPERED must be signed, diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 438df6359e..52f1b4dbf5 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -323,6 +323,119 @@ static bool trans_UDIV_zpzz(DisasContext *s, arg_rprr= _esz *a, uint32_t insn) =20 #undef DO_ZPZZ =20 +/* + *** SVE Integer Arithmetic - Unary Predicated Group + */ + +static bool do_zpz_ool(DisasContext *s, arg_rpr_esz *a, gen_helper_gvec_3 = *fn) +{ + if (fn =3D=3D NULL) { + return false; + } + if (sve_access_check(s)) { + unsigned vsz =3D vec_full_reg_size(s); + tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd), + vec_full_reg_offset(s, a->rn), + pred_full_reg_offset(s, a->pg), + vsz, vsz, 0, fn); + } + return true; +} + +#define DO_ZPZ(NAME, name) \ +static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a, uint32_t insn) \ +{ \ + static gen_helper_gvec_3 * const fns[4] =3D { \ + gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \ + gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \ + }; \ + return do_zpz_ool(s, a, fns[a->esz]); \ +} + +DO_ZPZ(CLS, cls) +DO_ZPZ(CLZ, clz) +DO_ZPZ(CNT_zpz, cnt_zpz) +DO_ZPZ(CNOT, cnot) +DO_ZPZ(NOT_zpz, not_zpz) +DO_ZPZ(ABS, abs) +DO_ZPZ(NEG, neg) + +static bool trans_FABS(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + static gen_helper_gvec_3 * const fns[4] =3D { + NULL, + gen_helper_sve_fabs_h, + gen_helper_sve_fabs_s, + gen_helper_sve_fabs_d + }; + return do_zpz_ool(s, a, fns[a->esz]); +} + +static bool trans_FNEG(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + static gen_helper_gvec_3 * const fns[4] =3D { + NULL, + gen_helper_sve_fneg_h, + gen_helper_sve_fneg_s, + gen_helper_sve_fneg_d + }; + return do_zpz_ool(s, a, fns[a->esz]); +} + +static bool trans_SXTB(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + static gen_helper_gvec_3 * const fns[4] =3D { + NULL, + gen_helper_sve_sxtb_h, + gen_helper_sve_sxtb_s, + gen_helper_sve_sxtb_d + }; + return do_zpz_ool(s, a, fns[a->esz]); +} + +static bool trans_UXTB(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + static gen_helper_gvec_3 * const fns[4] =3D { + NULL, + gen_helper_sve_uxtb_h, + gen_helper_sve_uxtb_s, + gen_helper_sve_uxtb_d + }; + return do_zpz_ool(s, a, fns[a->esz]); +} + +static bool trans_SXTH(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + static gen_helper_gvec_3 * const fns[4] =3D { + NULL, NULL, + gen_helper_sve_sxth_s, + gen_helper_sve_sxth_d + }; + return do_zpz_ool(s, a, fns[a->esz]); +} + +static bool trans_UXTH(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + static gen_helper_gvec_3 * const fns[4] =3D { + NULL, NULL, + gen_helper_sve_uxth_s, + gen_helper_sve_uxth_d + }; + return do_zpz_ool(s, a, fns[a->esz]); +} + +static bool trans_SXTW(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + return do_zpz_ool(s, a, a->esz =3D=3D 3 ? gen_helper_sve_sxtw_d : NULL= ); +} + +static bool trans_UXTW(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + return do_zpz_ool(s, a, a->esz =3D=3D 3 ? gen_helper_sve_uxtw_d : NULL= ); +} + +#undef DO_ZPZ + /* *** SVE Integer Reduction Group */ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 1de289e55d..0ddc1e96be 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -163,6 +163,29 @@ ASR_zpzw 00000100 .. 011 000 100 ... ..... ....= . @rdn_pg_rm LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm =20 +### SVE Integer Arithmetic - Unary Predicated Group + +# SVE unary bit operations (predicated) +# Note esz !=3D 0 for FABS and FNEG. +CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn +CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn +CNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn +CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn +NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn +FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn +FNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn + +# SVE integer unary operations (predicated) +# Note esz > original size for extensions. +ABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn +NEG 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn +SXTB 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn +UXTB 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn +SXTH 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn +UXTH 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn +SXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn +UXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn + ### SVE Logical - Unpredicated Group =20 # SVE bitwise logical operations (unpredicated) --=20 2.17.0 From nobody Wed Oct 29 22:55:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526510240071188.43677393670953; Wed, 16 May 2018 15:37:20 -0700 (PDT) Received: from localhost ([::1]:44800 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ52t-00043k-8Y for importer@patchew.org; Wed, 16 May 2018 18:37:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41214) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4wL-0007k8-Or for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ4wJ-0007Ve-L3 for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:33 -0400 Received: from mail-pg0-x22c.google.com ([2607:f8b0:400e:c05::22c]:38366) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ4wJ-0007VB-7E for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:31 -0400 Received: by mail-pg0-x22c.google.com with SMTP id n9-v6so896149pgq.5 for ; Wed, 16 May 2018 15:30:31 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=glh4d2APpezpBz9IDQVX/72okeWJ0gX7vbbiOtLdZLo=; b=ANyc3pcMNgnYLkrq186VhCWZzIigPEmhgTgTyN7yrevaL2tHv1OUfMRlxW0qEk/NB0 O6V4Qgwyt6p5RMrNSWliNWtjmKdNUw5zIcdLyAQrLRE7rzSJhVhtbwDsEzRYayRvzraz bnihbD/M8bbL5gKsXkexLflSlcbzIWvhK0/q0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=glh4d2APpezpBz9IDQVX/72okeWJ0gX7vbbiOtLdZLo=; b=aKtwf/CCw4Zd8wyXKlqqXT+mGPINj1uLzfVjTJTuw8QI/p0+2Z6fyTbdWT7KesauGS H3vVMf/5sKQl6Ep3nvMRfhmu9p0CzwdNZm3I52rXVdwaPg7dVoUVyIK+1kN1EImivdFI KLLUkFg2RcK6zePdl4gVZWpkgjLC3bN4gGF3E+goZ1kgQ8dmsL3vMIUYeSZkAzLqRwPN K3Q4/Dx6AXM7lEe7wmkrV5Szby9FwzwPxbZOQthW+fQV+KpXc2dkhwp/M8V2DKfUDciP Bqy8Gqm0CWm5BwnhkhWaTmmWeF3jFvLn1BYf7A5TWkg/jCez1OzyN7Mc0ttLxMwIvx8p eKyA== X-Gm-Message-State: ALKqPwdP9UPp4wwdxs88kYACjEqMtEeX0DSIzW/+q8E8fGgi5pb3XqrJ uHIToidmgj0UYbaBfQthCUYOutlMB2s= X-Google-Smtp-Source: AB8JxZo/Uyc7ClTLEBL/fxHWI13bNZADc4GYPHuzMCBnCwekp5ENd7EuQ/mlaOeuQRL9vcOGkNL5jg== X-Received: by 2002:a62:d044:: with SMTP id p65-v6mr2808230pfg.64.1526509829814; Wed, 16 May 2018 15:30:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:29:54 -0700 Message-Id: <20180516223007.10256-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22c Subject: [Qemu-devel] [PATCH v3-a 14/27] target/arm: Implement SVE Integer Multiply-Add Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 18 ++++++++++++ target/arm/sve_helper.c | 57 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 34 +++++++++++++++++++++++ target/arm/sve.decode | 17 ++++++++++++ 4 files changed, 126 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 11644125d1..b31d497f31 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -345,6 +345,24 @@ DEF_HELPER_FLAGS_4(sve_neg_h, TCG_CALL_NO_RWG, void, p= tr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_neg_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_neg_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_6(sve_mla_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sve_mla_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sve_mla_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sve_mla_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_6(sve_mls_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sve_mls_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sve_mls_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sve_mls_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 236d21e771..56a4eb71d5 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -935,3 +935,60 @@ DO_ZPZI_D(sve_asrd_d, int64_t, DO_ASRD) #undef DO_ASRD #undef DO_ZPZI #undef DO_ZPZI_D + +/* Fully general four-operand expander, controlled by a predicate. + */ +#define DO_ZPZZZ(NAME, TYPE, H, OP) \ +void HELPER(NAME)(void *vd, void *va, void *vn, void *vm, \ + void *vg, uint32_t desc) \ +{ \ + intptr_t i, opr_sz =3D simd_oprsz(desc); \ + for (i =3D 0; i < opr_sz; ) { \ + uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); \ + do { \ + if (pg & 1) { \ + TYPE nn =3D *(TYPE *)(vn + H(i)); \ + TYPE mm =3D *(TYPE *)(vm + H(i)); \ + TYPE aa =3D *(TYPE *)(va + H(i)); \ + *(TYPE *)(vd + H(i)) =3D OP(aa, nn, mm); \ + } \ + i +=3D sizeof(TYPE), pg >>=3D sizeof(TYPE); \ + } while (i & 15); \ + } \ +} + +/* Similarly, specialized for 64-bit operands. */ +#define DO_ZPZZZ_D(NAME, TYPE, OP) \ +void HELPER(NAME)(void *vd, void *va, void *vn, void *vm, \ + void *vg, uint32_t desc) \ +{ \ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; \ + TYPE *d =3D vd, *a =3D va, *n =3D vn, *m =3D vm; \ + uint8_t *pg =3D vg; \ + for (i =3D 0; i < opr_sz; i +=3D 1) { \ + if (pg[H1(i)] & 1) { \ + TYPE aa =3D a[i], nn =3D n[i], mm =3D m[i]; \ + d[i] =3D OP(aa, nn, mm); \ + } \ + } \ +} + +#define DO_MLA(A, N, M) (A + N * M) +#define DO_MLS(A, N, M) (A - N * M) + +DO_ZPZZZ(sve_mla_b, uint8_t, H1, DO_MLA) +DO_ZPZZZ(sve_mls_b, uint8_t, H1, DO_MLS) + +DO_ZPZZZ(sve_mla_h, uint16_t, H1_2, DO_MLA) +DO_ZPZZZ(sve_mls_h, uint16_t, H1_2, DO_MLS) + +DO_ZPZZZ(sve_mla_s, uint32_t, H1_4, DO_MLA) +DO_ZPZZZ(sve_mls_s, uint32_t, H1_4, DO_MLS) + +DO_ZPZZZ_D(sve_mla_d, uint64_t, DO_MLA) +DO_ZPZZZ_D(sve_mls_d, uint64_t, DO_MLS) + +#undef DO_MLA +#undef DO_MLS +#undef DO_ZPZZZ +#undef DO_ZPZZZ_D diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 52f1b4dbf5..f14bb2196a 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -634,6 +634,40 @@ DO_ZPZW(LSL, lsl) =20 #undef DO_ZPZW =20 +/* + *** SVE Integer Multiply-Add Group + */ + +static bool do_zpzzz_ool(DisasContext *s, arg_rprrr_esz *a, + gen_helper_gvec_5 *fn) +{ + if (sve_access_check(s)) { + unsigned vsz =3D vec_full_reg_size(s); + tcg_gen_gvec_5_ool(vec_full_reg_offset(s, a->rd), + vec_full_reg_offset(s, a->ra), + vec_full_reg_offset(s, a->rn), + vec_full_reg_offset(s, a->rm), + pred_full_reg_offset(s, a->pg), + vsz, vsz, 0, fn); + } + return true; +} + +#define DO_ZPZZZ(NAME, name) \ +static bool trans_##NAME(DisasContext *s, arg_rprrr_esz *a, uint32_t insn)= \ +{ \ + static gen_helper_gvec_5 * const fns[4] =3D { \ + gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \ + gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \ + }; \ + return do_zpzzz_ool(s, a, fns[a->esz]); \ +} + +DO_ZPZZZ(MLA, mla) +DO_ZPZZZ(MLS, mls) + +#undef DO_ZPZZZ + /* *** SVE Predicate Logical Operations Group */ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 0ddc1e96be..5e4335b2ae 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -47,6 +47,7 @@ &rpr_esz rd pg rn esz &rprr_s rd pg rn rm s &rprr_esz rd pg rn rm esz +&rprrr_esz rd pg rn rm ra esz &rpri_esz rd pg rn imm esz =20 ########################################################################### @@ -71,6 +72,12 @@ @rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \ &rprr_esz rm=3D%reg_movprfx =20 +# Three register operand, with governing predicate, vector element size +@rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \ + &rprrr_esz ra=3D%reg_movprfx +@rdn_pg_ra_rm ........ esz:2 . rm:5 ... pg:3 ra:5 rd:5 \ + &rprrr_esz rn=3D%reg_movprfx + # One register operand, with governing predicate, vector element size @rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz =20 @@ -186,6 +193,16 @@ UXTH 00000100 .. 010 011 101 ... ..... ....= . @rd_pg_rn SXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn UXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn =20 +### SVE Integer Multiply-Add Group + +# SVE integer multiply-add writing addend (predicated) +MLA 00000100 .. 0 ..... 010 ... ..... ..... @rda_pg_rn_rm +MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm + +# SVE integer multiply-add writing multiplicand (predicated) +MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # = MAD +MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # = MSB + ### SVE Logical - Unpredicated Group =20 # SVE bitwise logical operations (unpredicated) --=20 2.17.0 From nobody Wed Oct 29 22:55:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526510968268336.97881182968706; Wed, 16 May 2018 15:49:28 -0700 (PDT) Received: from localhost ([::1]:45109 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ5Ed-0005lx-B4 for importer@patchew.org; Wed, 16 May 2018 18:49:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41220) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4wL-0007kO-TL for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ4wK-0007Wk-Sa for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:33 -0400 Received: from mail-pl0-x241.google.com ([2607:f8b0:400e:c01::241]:40157) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ4wK-0007W7-HN for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:32 -0400 Received: by mail-pl0-x241.google.com with SMTP id t12-v6so1244645plo.7 for ; Wed, 16 May 2018 15:30:32 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aEw+icNHDVvyjfO6zFShh6ZmP/DNMAOE4EL6agkNtMo=; b=WCkNwAl+4oo1DRZ7cbZ+3ss+BBw1DSNNjctGX9npqcFZKhN3Z+e/9+4cFyfV1TOmBv DH4m1HGFbtjLjKeCdROGe/R4QsjFShf/WK03VTzhqnrZovOjWXJ7VBYdXsAEqv1H1lvS ITc2evKEnlk8bG9Lhw0uxKmAAgtsCY0+fR1Is= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aEw+icNHDVvyjfO6zFShh6ZmP/DNMAOE4EL6agkNtMo=; b=tjOCyHIchm7DVEj6/SvsLHfk2tZsRgWhTUZukZqFniURCk8ryufaYSJKnQEkrL9rrC D6fEetE9AvPU/xcl8O/RwfhsSibgF9vHVkDTOGO4mkIxfysJJRcCyOxzqbcEljp+O0w+ F1qG+CWuQd3arenJ/aIF7z1Iub5QvcZVRIt7g5k0y262ohBowKaxnl19iaRlGiCc3dJZ BxzbzgfSRJXKBPuZyFL1lxOq/o9Rde4jGjkOwd+DaD63EEk9J51ka2tbhaOeKWbQkocP xU2Ml2M+zAeRt1W9moIMZu++jQ1W16G83Tn4OJe/zuckR8EkxpBbq9+TnO2CYuY8WqTg J4UQ== X-Gm-Message-State: ALKqPwe1+0s3S7l02y3m9KApj92IS30dy92mJp7+D+rPkqq7qbxH+D/D KCJeCe0li7gyxteCxcP4VUyPVw/PTKc= X-Google-Smtp-Source: AB8JxZrU+/zhcbo+f6RDwpY5sR/jDTASjYE6tTSjZ4Yinwu3v+9/0m9qWZRPPRdigXw4JDbArRaxuA== X-Received: by 2002:a17:902:710f:: with SMTP id a15-v6mr2758561pll.171.1526509831287; Wed, 16 May 2018 15:30:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:29:55 -0700 Message-Id: <20180516223007.10256-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH v3-a 15/27] target/arm: Implement SVE Integer Arithmetic - Unpredicated Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 34 ++++++++++++++++++++++++++++++++++ target/arm/sve.decode | 13 +++++++++++++ 2 files changed, 47 insertions(+) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index f14bb2196a..d9c4118d46 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -251,6 +251,40 @@ static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz= *a, uint32_t insn) return do_vector3_z(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm); } =20 +/* + *** SVE Integer Arithmetic - Unpredicated Group + */ + +static bool trans_ADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + return do_vector3_z(s, tcg_gen_gvec_add, a->esz, a->rd, a->rn, a->rm); +} + +static bool trans_SUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + return do_vector3_z(s, tcg_gen_gvec_sub, a->esz, a->rd, a->rn, a->rm); +} + +static bool trans_SQADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + return do_vector3_z(s, tcg_gen_gvec_ssadd, a->esz, a->rd, a->rn, a->rm= ); +} + +static bool trans_SQSUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + return do_vector3_z(s, tcg_gen_gvec_sssub, a->esz, a->rd, a->rn, a->rm= ); +} + +static bool trans_UQADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + return do_vector3_z(s, tcg_gen_gvec_usadd, a->esz, a->rd, a->rn, a->rm= ); +} + +static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + return do_vector3_z(s, tcg_gen_gvec_ussub, a->esz, a->rd, a->rn, a->rm= ); +} + /* *** SVE Integer Arithmetic - Binary Predicated Group */ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 5e4335b2ae..58d59c7b77 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -66,6 +66,9 @@ # Three predicate operand, with governing predicate, flag setting @pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s =20 +# Three operand, vector element size +@rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz + # Two register operand, with governing predicate, vector element size @rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \ &rprr_esz rn=3D%reg_movprfx @@ -203,6 +206,16 @@ MLS 00000100 .. 0 ..... 011 ... ..... ....= . @rda_pg_rn_rm MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # = MAD MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # = MSB =20 +### SVE Integer Arithmetic - Unpredicated Group + +# SVE integer add/subtract vectors (unpredicated) +ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm +SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm +SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm +UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm +SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm +UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm + ### SVE Logical - Unpredicated Group =20 # SVE bitwise logical operations (unpredicated) --=20 2.17.0 From nobody Wed Oct 29 22:55:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526511148292371.24738798730027; Wed, 16 May 2018 15:52:28 -0700 (PDT) Received: from localhost ([::1]:45298 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ5HT-0008JJ-He for importer@patchew.org; Wed, 16 May 2018 18:52:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41263) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4wN-0007mp-TB for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ4wM-0007Xn-Fx for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:35 -0400 Received: from mail-pl0-x22f.google.com ([2607:f8b0:400e:c01::22f]:33468) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ4wM-0007X8-3S for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:34 -0400 Received: by mail-pl0-x22f.google.com with SMTP id n10-v6so1251025plp.0 for ; Wed, 16 May 2018 15:30:34 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=urvFqiQxPp3CQoQc6xCxWJ/+pIBwOhdS02gT2zu4FKc=; b=P6dTbGC9/seefUR+7fEvgxfY8EABBhYXsJAYos+ykSDd5srrfmvq1LzWkgqW3RBUZi 2QSa8CyiUNAOnutqlelOAe0sm869NC/zpOSa7Uf2V8IEPo2RR7q1byDvDrQqLuYT0EM9 28zP8ZKef2bbxmIGxejhaXB+QCgANZSHFtPm0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=urvFqiQxPp3CQoQc6xCxWJ/+pIBwOhdS02gT2zu4FKc=; b=jbF+4n93bCbg7XxUyAghIgfa6CcJcIvISpFQuikGPrYvuVd1dNYOogC6wsn2kdlY0b wq6sQDpBa8zSlPS+lxNCI8VZduorHawMo2X5mxQNCkSbndYD9iNk3SYyORMuOU3aJn27 W1bIn0ZrwBqEKvRXj+Rt872ob+udwdDwR0RrDUboYb26Awbx8AwsxSLz3YSb+KYEPqLM fW4N2iAY1Im6PB2qy6XqC9NxFPyxh96Sh2cbEGCvgcHmr4SuhRIkkRTFBsHYbdB8CUaJ kxBEvpAgSxwfFOZiohxHUxB+FirUCsEZIwWJbMgLVtxDHrbBVq51CA+R8Ov428eXfApO lYig== X-Gm-Message-State: ALKqPwciFAbyu7nDvXt66xAclOmgedviN9QV/QYzpOKnYGYzVGVdWsXn mVP6E/oIPW4b+dGYmzHcxImXnFhBe9Q= X-Google-Smtp-Source: AB8JxZrAQhgUPHelqkPMpQpblw7QDx7zbgDXzJISAXOYZrHLbB2wammAqGJCN2octzQJJ3X5bHSf6Q== X-Received: by 2002:a17:902:26:: with SMTP id 35-v6mr2834857pla.104.1526509832695; Wed, 16 May 2018 15:30:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:29:56 -0700 Message-Id: <20180516223007.10256-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::22f Subject: [Qemu-devel] [PATCH v3-a 16/27] target/arm: Implement SVE Index Generation Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 5 +++ target/arm/sve_helper.c | 40 +++++++++++++++++++ target/arm/translate-sve.c | 79 ++++++++++++++++++++++++++++++++++++++ target/arm/sve.decode | 14 +++++++ 4 files changed, 138 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index b31d497f31..2a2dbe98dd 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -363,6 +363,11 @@ DEF_HELPER_FLAGS_6(sve_mls_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_mls_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_4(sve_index_b, TCG_CALL_NO_RWG, void, ptr, i32, i32, i32) +DEF_HELPER_FLAGS_4(sve_index_h, TCG_CALL_NO_RWG, void, ptr, i32, i32, i32) +DEF_HELPER_FLAGS_4(sve_index_s, TCG_CALL_NO_RWG, void, ptr, i32, i32, i32) +DEF_HELPER_FLAGS_4(sve_index_d, TCG_CALL_NO_RWG, void, ptr, i64, i64, i32) + DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 56a4eb71d5..385bb8b314 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -992,3 +992,43 @@ DO_ZPZZZ_D(sve_mls_d, uint64_t, DO_MLS) #undef DO_MLS #undef DO_ZPZZZ #undef DO_ZPZZZ_D + +void HELPER(sve_index_b)(void *vd, uint32_t start, + uint32_t incr, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc); + uint8_t *d =3D vd; + for (i =3D 0; i < opr_sz; i +=3D 1) { + d[H1(i)] =3D start + i * incr; + } +} + +void HELPER(sve_index_h)(void *vd, uint32_t start, + uint32_t incr, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 2; + uint16_t *d =3D vd; + for (i =3D 0; i < opr_sz; i +=3D 1) { + d[H2(i)] =3D start + i * incr; + } +} + +void HELPER(sve_index_s)(void *vd, uint32_t start, + uint32_t incr, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 4; + uint32_t *d =3D vd; + for (i =3D 0; i < opr_sz; i +=3D 1) { + d[H4(i)] =3D start + i * incr; + } +} + +void HELPER(sve_index_d)(void *vd, uint64_t start, + uint64_t incr, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t *d =3D vd; + for (i =3D 0; i < opr_sz; i +=3D 1) { + d[i] =3D start + i * incr; + } +} diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index d9c4118d46..e3a8e9506e 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -702,6 +702,85 @@ DO_ZPZZZ(MLS, mls) =20 #undef DO_ZPZZZ =20 +/* + *** SVE Index Generation Group + */ + +static void do_index(DisasContext *s, int esz, int rd, + TCGv_i64 start, TCGv_i64 incr) +{ + unsigned vsz =3D vec_full_reg_size(s); + TCGv_i32 desc =3D tcg_const_i32(simd_desc(vsz, vsz, 0)); + TCGv_ptr t_zd =3D tcg_temp_new_ptr(); + + tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, rd)); + if (esz =3D=3D 3) { + gen_helper_sve_index_d(t_zd, start, incr, desc); + } else { + typedef void index_fn(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); + static index_fn * const fns[3] =3D { + gen_helper_sve_index_b, + gen_helper_sve_index_h, + gen_helper_sve_index_s, + }; + TCGv_i32 s32 =3D tcg_temp_new_i32(); + TCGv_i32 i32 =3D tcg_temp_new_i32(); + + tcg_gen_extrl_i64_i32(s32, start); + tcg_gen_extrl_i64_i32(i32, incr); + fns[esz](t_zd, s32, i32, desc); + + tcg_temp_free_i32(s32); + tcg_temp_free_i32(i32); + } + tcg_temp_free_ptr(t_zd); + tcg_temp_free_i32(desc); +} + +static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a, uint32_t insn) +{ + if (sve_access_check(s)) { + TCGv_i64 start =3D tcg_const_i64(a->imm1); + TCGv_i64 incr =3D tcg_const_i64(a->imm2); + do_index(s, a->esz, a->rd, start, incr); + tcg_temp_free_i64(start); + tcg_temp_free_i64(incr); + } + return true; +} + +static bool trans_INDEX_ir(DisasContext *s, arg_INDEX_ir *a, uint32_t insn) +{ + if (sve_access_check(s)) { + TCGv_i64 start =3D tcg_const_i64(a->imm); + TCGv_i64 incr =3D cpu_reg(s, a->rm); + do_index(s, a->esz, a->rd, start, incr); + tcg_temp_free_i64(start); + } + return true; +} + +static bool trans_INDEX_ri(DisasContext *s, arg_INDEX_ri *a, uint32_t insn) +{ + if (sve_access_check(s)) { + TCGv_i64 start =3D cpu_reg(s, a->rn); + TCGv_i64 incr =3D tcg_const_i64(a->imm); + do_index(s, a->esz, a->rd, start, incr); + tcg_temp_free_i64(incr); + } + return true; +} + +static bool trans_INDEX_rr(DisasContext *s, arg_INDEX_rr *a, uint32_t insn) +{ + if (sve_access_check(s)) { + TCGv_i64 start =3D cpu_reg(s, a->rn); + TCGv_i64 incr =3D cpu_reg(s, a->rm); + do_index(s, a->esz, a->rd, start, incr); + } + return true; +} + /* *** SVE Predicate Logical Operations Group */ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 58d59c7b77..4f9f64f5ab 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -224,6 +224,20 @@ ORR_zzz 00000100 01 1 ..... 001 100 ..... ....= . @rd_rn_rm_e0 EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_= e0 BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_= e0 =20 +### SVE Index Generation Group + +# SVE index generation (immediate start, immediate increment) +INDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5 + +# SVE index generation (immediate start, register increment) +INDEX_ir 00000100 esz:2 1 rm:5 010010 imm:s5 rd:5 + +# SVE index generation (register start, immediate increment) +INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5 + +# SVE index generation (register start, register increment) +INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm + ### SVE Predicate Logical Operations Group =20 # SVE predicate logical operations --=20 2.17.0 From nobody Wed Oct 29 22:55:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526510597611501.0192482306129; Wed, 16 May 2018 15:43:17 -0700 (PDT) Received: from localhost ([::1]:44841 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ58e-0000U4-Tq for importer@patchew.org; Wed, 16 May 2018 18:43:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41296) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4wP-0007o5-3V for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ4wN-0007Zf-UI for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:36 -0400 Received: from mail-pl0-x244.google.com ([2607:f8b0:400e:c01::244]:40160) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ4wN-0007Xx-Bv for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:35 -0400 Received: by mail-pl0-x244.google.com with SMTP id t12-v6so1244693plo.7 for ; Wed, 16 May 2018 15:30:35 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=N/YOlr76XoGcfWJEp8TVu7OeRp/aErPflcP4crzDavo=; b=hU11cnEu0Kz9w9M6k+j63DFKC6lF55qgwLcs9K4DmDOoSaJZ1ocJjJoQzRKQj5OMMV e207EtJaDgO96QfWhDJrgDDrcZjumbsWoUzsT9bqbzkuAeADRJxU6cwBu8PvBLUM/rjB C3mHsL9v7ShhxozvDSySaZgmY3KVdJBxTCUO8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=N/YOlr76XoGcfWJEp8TVu7OeRp/aErPflcP4crzDavo=; b=DjoGk3B8a5B6QxD74KZ3R/REAxyNgBq2cOsm4jgNTgbS4S3PhEphM7pK85SqGmCnUx JBq/o9uohwqWJYQZWv7RMqGIT8PBwIcgdZHTYmxTQDofWupZEZuL5SK4MqvOld3Yf93j JVUsNhEs1Uwjb1IHdLJ0zklzFUGDOEiFk5rgNz8Wbs48C884mEl0W2DcCSzqQboHcyOv /9winmkeiBy1cE+AZLiQWJMFccrUpgX0e248bqXTPYZ8/LhKdE/wn9WiQRiRafub0wGI TQerW0aLcqBxHs1he1H7zymhYZYrIZ5xejTjqssT0J71Fmoozv+iMuZGLsZEIO4NAF5q Cbtw== X-Gm-Message-State: ALKqPwcjQ7GudNcwzGbfX4u5xyWVL4aTyP1hOIbk+g/wIfqSNbvuiMnH sT2ID7bucCko0ZF3+I8GDPFLBPYQwxw= X-Google-Smtp-Source: AB8JxZp4tGuhLJcCdN3HBqnXHXE56JhvjRGnXdEjed1Gba2CQU2Be5LH6QOndYkbTRWojxu6S8SDZA== X-Received: by 2002:a17:902:7409:: with SMTP id g9-v6mr2679043pll.255.1526509834097; Wed, 16 May 2018 15:30:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:29:57 -0700 Message-Id: <20180516223007.10256-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v3-a 17/27] target/arm: Implement SVE Stack Allocation Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 27 +++++++++++++++++++++++++++ target/arm/sve.decode | 12 ++++++++++++ 2 files changed, 39 insertions(+) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index e3a8e9506e..f95efa3c72 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -781,6 +781,33 @@ static bool trans_INDEX_rr(DisasContext *s, arg_INDEX_= rr *a, uint32_t insn) return true; } =20 +/* + *** SVE Stack Allocation Group + */ + +static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a, uint32_t insn) +{ + TCGv_i64 rd =3D cpu_reg_sp(s, a->rd); + TCGv_i64 rn =3D cpu_reg_sp(s, a->rn); + tcg_gen_addi_i64(rd, rn, a->imm * vec_full_reg_size(s)); + return true; +} + +static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a, uint32_t insn) +{ + TCGv_i64 rd =3D cpu_reg_sp(s, a->rd); + TCGv_i64 rn =3D cpu_reg_sp(s, a->rn); + tcg_gen_addi_i64(rd, rn, a->imm * pred_full_reg_size(s)); + return true; +} + +static bool trans_RDVL(DisasContext *s, arg_RDVL *a, uint32_t insn) +{ + TCGv_i64 reg =3D cpu_reg(s, a->rd); + tcg_gen_movi_i64(reg, a->imm * vec_full_reg_size(s)); + return true; +} + /* *** SVE Predicate Logical Operations Group */ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 4f9f64f5ab..9d5c061165 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -84,6 +84,9 @@ # One register operand, with governing predicate, vector element size @rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz =20 +# Two register operands with a 6-bit signed immediate. +@rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri + # Two register operand, one immediate operand, with predicate, # element size encoded as TSZHL. User must fill in imm. @rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 \ @@ -238,6 +241,15 @@ INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd= :5 # SVE index generation (register start, register increment) INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm =20 +### SVE Stack Allocation Group + +# SVE stack frame adjustment +ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6 +ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6 + +# SVE stack frame size +RDVL 00000100 101 11111 01010 imm:s6 rd:5 + ### SVE Predicate Logical Operations Group =20 # SVE predicate logical operations --=20 2.17.0 From nobody Wed Oct 29 22:55:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152651042875547.764342442395105; Wed, 16 May 2018 15:40:28 -0700 (PDT) Received: from localhost ([::1]:44822 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ55v-0006bL-J8 for importer@patchew.org; Wed, 16 May 2018 18:40:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41322) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4wQ-0007pm-NH for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ4wP-0007b7-4l for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:38 -0400 Received: from mail-pl0-x22d.google.com ([2607:f8b0:400e:c01::22d]:43856) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ4wO-0007Zy-Jm for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:36 -0400 Received: by mail-pl0-x22d.google.com with SMTP id c41-v6so1240279plj.10 for ; Wed, 16 May 2018 15:30:36 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uOjj/7uF2ODA0nDNk1uedyW754Dt3SijjcaKFE2CybU=; b=J6OqBAtcDgIFodUlfP5Dau6bHYlM0OjpUKaWg2QVEkR/zh35Yy+zKesIVu/WCouxiI qlb66hu4Na997AjMfzfBuAL0H9vzwKSaq7PJvy2cPBIwp0F7m1GOpHmneLh8QM0PE1b/ Atd1EfQmWntfiawHME4tc00epse3ZO6eJtolk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uOjj/7uF2ODA0nDNk1uedyW754Dt3SijjcaKFE2CybU=; b=WLoeghAxWvNY2fgWpP/42rhTcMiFQuUeb4qSp70p3CLqEIqM3Jts4UNx+pN01XrsXA WnQcKbseBqSMWK6jE6SlhieljsKNZqJvJ10rU0Z/LDeBAKRZAUHRkYZi5t+fKpgbrS2O uwBiBgNiMSbv5ZojukSGUlJMysNJa4Coar+QMoyzqSXeGLBinUdsmcQODdkc0sK4shRS IrpyGaIh8CsyZQt8KBrRT9LRPVXWVE6fDrj17pilS5ocTZc9lcTSUzCetyF1SOUSmD9o tBM/jTfhoXI24jeknkojXDXvu65ThQO3DxKg2T3jZ/Y6dujMX7HIE520ENSIk/UnP0fb IzDw== X-Gm-Message-State: ALKqPwe+vj1CYXRJQcuRIyQiqYStzs5ZFiuZYFEw/miwNLs7URYgfWeH 55jTcAGIsddt3RMXtf7hHZMcWzBKoqc= X-Google-Smtp-Source: AB8JxZo2p+Do8otpJXJx8D82attfc0oXpA7Ihd4mtPhHOaBmpluqGIE6gGU+yKQc9bN6Ab55lhYtMA== X-Received: by 2002:a17:902:4203:: with SMTP id g3-v6mr2760210pld.315.1526509835286; Wed, 16 May 2018 15:30:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:29:58 -0700 Message-Id: <20180516223007.10256-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::22d Subject: [Qemu-devel] [PATCH v3-a 18/27] target/arm: Implement SVE Bitwise Shift - Unpredicated Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 12 ++++++ target/arm/sve_helper.c | 30 ++++++++++++++ target/arm/translate-sve.c | 85 ++++++++++++++++++++++++++++++++++++++ target/arm/sve.decode | 26 ++++++++++++ 4 files changed, 153 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 2a2dbe98dd..00e3cd48bb 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -368,6 +368,18 @@ DEF_HELPER_FLAGS_4(sve_index_h, TCG_CALL_NO_RWG, void,= ptr, i32, i32, i32) DEF_HELPER_FLAGS_4(sve_index_s, TCG_CALL_NO_RWG, void, ptr, i32, i32, i32) DEF_HELPER_FLAGS_4(sve_index_d, TCG_CALL_NO_RWG, void, ptr, i64, i64, i32) =20 +DEF_HELPER_FLAGS_4(sve_asr_zzw_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sve_asr_zzw_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sve_asr_zzw_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) + +DEF_HELPER_FLAGS_4(sve_lsr_zzw_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sve_lsr_zzw_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sve_lsr_zzw_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) + +DEF_HELPER_FLAGS_4(sve_lsl_zzw_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sve_lsl_zzw_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sve_lsl_zzw_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) + DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 385bb8b314..f43640c1eb 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -615,6 +615,36 @@ DO_ZPZ(sve_neg_h, uint16_t, H1_2, DO_NEG) DO_ZPZ(sve_neg_s, uint32_t, H1_4, DO_NEG) DO_ZPZ_D(sve_neg_d, uint64_t, DO_NEG) =20 +/* Three-operand expander, unpredicated, in which the third operand is "wi= de". + */ +#define DO_ZZW(NAME, TYPE, TYPEW, H, OP) \ +void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \ +{ \ + intptr_t i, opr_sz =3D simd_oprsz(desc); \ + for (i =3D 0; i < opr_sz; ) { \ + TYPEW mm =3D *(TYPEW *)(vm + i); \ + do { \ + TYPE nn =3D *(TYPE *)(vn + H(i)); \ + *(TYPE *)(vd + H(i)) =3D OP(nn, mm); \ + i +=3D sizeof(TYPE); \ + } while (i & 7); \ + } \ +} + +DO_ZZW(sve_asr_zzw_b, int8_t, uint64_t, H1, DO_ASR) +DO_ZZW(sve_lsr_zzw_b, uint8_t, uint64_t, H1, DO_LSR) +DO_ZZW(sve_lsl_zzw_b, uint8_t, uint64_t, H1, DO_LSL) + +DO_ZZW(sve_asr_zzw_h, int16_t, uint64_t, H1_2, DO_ASR) +DO_ZZW(sve_lsr_zzw_h, uint16_t, uint64_t, H1_2, DO_LSR) +DO_ZZW(sve_lsl_zzw_h, uint16_t, uint64_t, H1_2, DO_LSL) + +DO_ZZW(sve_asr_zzw_s, int32_t, uint64_t, H1_4, DO_ASR) +DO_ZZW(sve_lsr_zzw_s, uint32_t, uint64_t, H1_4, DO_LSR) +DO_ZZW(sve_lsl_zzw_s, uint32_t, uint64_t, H1_4, DO_LSL) + +#undef DO_ZZW + #undef DO_CLS_B #undef DO_CLS_H #undef DO_CLZ_B diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index f95efa3c72..2c2218bc31 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -134,6 +134,13 @@ static bool do_mov_z(DisasContext *s, int rd, int rn) return do_vector2_z(s, tcg_gen_gvec_mov, 0, rd, rn); } =20 +/* Initialize a Zreg with replications of a 64-bit immediate. */ +static void do_dupi_z(DisasContext *s, int rd, uint64_t word) +{ + unsigned vsz =3D vec_full_reg_size(s); + tcg_gen_gvec_dup64i(vec_full_reg_offset(s, rd), vsz, vsz, word); +} + /* Invoke a vector expander on two Pregs. */ static bool do_vector2_p(DisasContext *s, GVecGen2Fn *gvec_fn, int esz, int rd, int rn) @@ -668,6 +675,84 @@ DO_ZPZW(LSL, lsl) =20 #undef DO_ZPZW =20 +/* + *** SVE Bitwise Shift - Unpredicated Group + */ + +static bool do_shift_imm(DisasContext *s, arg_rri_esz *a, bool asr, + void (*gvec_fn)(unsigned, uint32_t, uint32_t, + int64_t, uint32_t, uint32_t)) +{ + if (a->esz < 0) { + /* Invalid tsz encoding -- see tszimm_esz. */ + return false; + } + if (sve_access_check(s)) { + unsigned vsz =3D vec_full_reg_size(s); + /* Shift by element size is architecturally valid. For + arithmetic right-shift, it's the same as by one less. + Otherwise it is a zeroing operation. */ + if (a->imm >=3D 8 << a->esz) { + if (asr) { + a->imm =3D (8 << a->esz) - 1; + } else { + do_dupi_z(s, a->rd, 0); + return true; + } + } + gvec_fn(a->esz, vec_full_reg_offset(s, a->rd), + vec_full_reg_offset(s, a->rn), a->imm, vsz, vsz); + } + return true; +} + +static bool trans_ASR_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn) +{ + return do_shift_imm(s, a, true, tcg_gen_gvec_sari); +} + +static bool trans_LSR_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn) +{ + return do_shift_imm(s, a, false, tcg_gen_gvec_shri); +} + +static bool trans_LSL_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn) +{ + return do_shift_imm(s, a, false, tcg_gen_gvec_shli); +} + +static bool do_zzw_ool(DisasContext *s, arg_rrr_esz *a, gen_helper_gvec_3 = *fn) +{ + if (fn =3D=3D NULL) { + return false; + } + if (sve_access_check(s)) { + unsigned vsz =3D vec_full_reg_size(s); + tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd), + vec_full_reg_offset(s, a->rn), + vec_full_reg_offset(s, a->rm), + vsz, vsz, 0, fn); + } + return true; +} + +#define DO_ZZW(NAME, name) \ +static bool trans_##NAME##_zzw(DisasContext *s, arg_rrr_esz *a, \ + uint32_t insn) \ +{ \ + static gen_helper_gvec_3 * const fns[4] =3D { = \ + gen_helper_sve_##name##_zzw_b, gen_helper_sve_##name##_zzw_h, \ + gen_helper_sve_##name##_zzw_s, NULL \ + }; \ + return do_zzw_ool(s, a, fns[a->esz]); \ +} + +DO_ZZW(ASR, asr) +DO_ZZW(LSR, lsr) +DO_ZZW(LSL, lsl) + +#undef DO_ZZW + /* *** SVE Integer Multiply-Add Group */ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 9d5c061165..b24f6b2f1b 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -32,6 +32,11 @@ # A combination of tsz:imm3 -- extract (tsz:imm3) - esize %tszimm_shl 22:2 5:5 !function=3Dtszimm_shl =20 +# Similarly for the tszh/tszl pair at 22/16 for zzi +%tszimm16_esz 22:2 16:5 !function=3Dtszimm_esz +%tszimm16_shr 22:2 16:5 !function=3Dtszimm_shr +%tszimm16_shl 22:2 16:5 !function=3Dtszimm_shl + # Either a copy of rd (at bit 0), or a different source # as propagated via the MOVPRFX instruction. %reg_movprfx 0:5 @@ -43,6 +48,7 @@ =20 &rr_esz rd rn esz &rri rd rn imm +&rri_esz rd rn imm esz &rrr_esz rd rn rm esz &rpr_esz rd pg rn esz &rprr_s rd pg rn rm s @@ -92,6 +98,10 @@ @rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 \ &rpri_esz rn=3D%reg_movprfx esz=3D%tszimm_esz =20 +# Similarly without predicate. +@rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \ + &rri_esz esz=3D%tszimm16_esz + # Basic Load/Store with 9-bit immediate offset @pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \ &rri imm=3D%imm9_16_10 @@ -250,6 +260,22 @@ ADDPL 00000100 011 ..... 01010 ...... ..... = @rd_rn_i6 # SVE stack frame size RDVL 00000100 101 11111 01010 imm:s6 rd:5 =20 +### SVE Bitwise Shift - Unpredicated Group + +# SVE bitwise shift by immediate (unpredicated) +ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... \ + @rd_rn_tszimm imm=3D%tszimm16_shr +LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... \ + @rd_rn_tszimm imm=3D%tszimm16_shr +LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... \ + @rd_rn_tszimm imm=3D%tszimm16_shl + +# SVE bitwise shift by wide elements (unpredicated) +# Note esz !=3D 3 +ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm +LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm +LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm + ### SVE Predicate Logical Operations Group =20 # SVE predicate logical operations --=20 2.17.0 From nobody Wed Oct 29 22:55:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526511292306953.7414766985274; Wed, 16 May 2018 15:54:52 -0700 (PDT) Received: from localhost ([::1]:45487 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ5Jq-0002Ay-Ka for importer@patchew.org; Wed, 16 May 2018 18:54:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41381) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4wT-0007sr-Lk for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ4wQ-0007bx-Dh for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:41 -0400 Received: from mail-pf0-x22e.google.com ([2607:f8b0:400e:c00::22e]:38195) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ4wQ-0007bN-0F for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:38 -0400 Received: by mail-pf0-x22e.google.com with SMTP id o76-v6so1055271pfi.5 for ; Wed, 16 May 2018 15:30:37 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=k3EXmj1zgibPmaPAluYYBePwXnlNWmp/AhopEEu/1oQ=; b=BaqDzAeLSpS02V6np8+xyHnl0OODiL8F/Sl4lyUXgTmwcsQCkIJmhAzF4s+pU4o24P X+Vao/TuMMx4fWDjiASv3I0b4u0wioV+0Gi1Emkgz+qXRAXTq7hdVjGmZLMZAHXpzzmG D2nWM67ubD6T7PLsHg93mvjTXZN9MYgyVXj5Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=k3EXmj1zgibPmaPAluYYBePwXnlNWmp/AhopEEu/1oQ=; b=DsewYefce06agsQTDfgfkZC+3mj3oD0PMl9eK2gr6W30wvVPb7u3cU6SLci4Tapumq 9IjckZHOZhiRSmzsPGElDwIJaBoSbeVf/t63DN4Q2ILUf1xMTuPqwjbx8zaNPkDj9mNS 4jHAQwkpffCgWIa4a31SS1jhpLMkSQW0M7qAdywvVjx+THBw4AnI4Vw93IW4MTUgcsSt bHn3aQHYMgJypkQb3KIdthXqu8i2RZW8EIJ+9jRPqcc1/a4sACKRveagXFHtE7JVch8a suH7QLqA/Tqen3jyvJGwyNEeGyZ2t3RM9cOgD8wyBVtCkiuYMCqOn+Chl32bES77c05l OgZw== X-Gm-Message-State: ALKqPwdLi01ChW3rtDzxbykMzL0tr8vhExvMT8zkLgjygcoSoVSK0X/W 64fyertuojrnx4ZKsNizzoghmA3vS1c= X-Google-Smtp-Source: AB8JxZowGXcF8MmAqw72hHKU7XfUQjyAFd3qu6/BGVQiV8Y1Wgc8k79Neb1f+ZMtvYeVVs/1GDk0ZA== X-Received: by 2002:a65:648a:: with SMTP id e10-v6mr2187782pgv.34.1526509836652; Wed, 16 May 2018 15:30:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:29:59 -0700 Message-Id: <20180516223007.10256-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22e Subject: [Qemu-devel] [PATCH v3-a 19/27] target/arm: Implement SVE Compute Vector Address Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 5 +++++ target/arm/sve_helper.c | 40 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 36 ++++++++++++++++++++++++++++++++++ target/arm/sve.decode | 12 ++++++++++++ 4 files changed, 93 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 00e3cd48bb..5280d375f9 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -380,6 +380,11 @@ DEF_HELPER_FLAGS_4(sve_lsl_zzw_b, TCG_CALL_NO_RWG, voi= d, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_lsl_zzw_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) DEF_HELPER_FLAGS_4(sve_lsl_zzw_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) =20 +DEF_HELPER_FLAGS_4(sve_adr_p32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_adr_p64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_adr_s32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_adr_u32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index f43640c1eb..7fa8394aec 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -1062,3 +1062,43 @@ void HELPER(sve_index_d)(void *vd, uint64_t start, d[i] =3D start + i * incr; } } + +void HELPER(sve_adr_p32)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 4; + uint32_t sh =3D simd_data(desc); + uint32_t *d =3D vd, *n =3D vn, *m =3D vm; + for (i =3D 0; i < opr_sz; i +=3D 1) { + d[i] =3D n[i] + (m[i] << sh); + } +} + +void HELPER(sve_adr_p64)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t sh =3D simd_data(desc); + uint64_t *d =3D vd, *n =3D vn, *m =3D vm; + for (i =3D 0; i < opr_sz; i +=3D 1) { + d[i] =3D n[i] + (m[i] << sh); + } +} + +void HELPER(sve_adr_s32)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t sh =3D simd_data(desc); + uint64_t *d =3D vd, *n =3D vn, *m =3D vm; + for (i =3D 0; i < opr_sz; i +=3D 1) { + d[i] =3D n[i] + ((uint64_t)(int32_t)m[i] << sh); + } +} + +void HELPER(sve_adr_u32)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t sh =3D simd_data(desc); + uint64_t *d =3D vd, *n =3D vn, *m =3D vm; + for (i =3D 0; i < opr_sz; i +=3D 1) { + d[i] =3D n[i] + ((uint64_t)(uint32_t)m[i] << sh); + } +} diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 2c2218bc31..8924848463 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -893,6 +893,42 @@ static bool trans_RDVL(DisasContext *s, arg_RDVL *a, u= int32_t insn) return true; } =20 +/* + *** SVE Compute Vector Address Group + */ + +static bool do_adr(DisasContext *s, arg_rrri *a, gen_helper_gvec_3 *fn) +{ + if (sve_access_check(s)) { + unsigned vsz =3D vec_full_reg_size(s); + tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd), + vec_full_reg_offset(s, a->rn), + vec_full_reg_offset(s, a->rm), + vsz, vsz, a->imm, fn); + } + return true; +} + +static bool trans_ADR_p32(DisasContext *s, arg_rrri *a, uint32_t insn) +{ + return do_adr(s, a, gen_helper_sve_adr_p32); +} + +static bool trans_ADR_p64(DisasContext *s, arg_rrri *a, uint32_t insn) +{ + return do_adr(s, a, gen_helper_sve_adr_p64); +} + +static bool trans_ADR_s32(DisasContext *s, arg_rrri *a, uint32_t insn) +{ + return do_adr(s, a, gen_helper_sve_adr_s32); +} + +static bool trans_ADR_u32(DisasContext *s, arg_rrri *a, uint32_t insn) +{ + return do_adr(s, a, gen_helper_sve_adr_u32); +} + /* *** SVE Predicate Logical Operations Group */ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index b24f6b2f1b..691876de4e 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -48,6 +48,7 @@ =20 &rr_esz rd rn esz &rri rd rn imm +&rrri rd rn rm imm &rri_esz rd rn imm esz &rrr_esz rd rn rm esz &rpr_esz rd pg rn esz @@ -75,6 +76,9 @@ # Three operand, vector element size @rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz =20 +# Three operand with "memory" size, aka immediate left shift +@rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri + # Two register operand, with governing predicate, vector element size @rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \ &rprr_esz rn=3D%reg_movprfx @@ -276,6 +280,14 @@ ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ....= . @rd_rn_rm LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm =20 +### SVE Compute Vector Address Group + +# SVE vector address generation +ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz= _rm +ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz= _rm +ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz= _rm +ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz= _rm + ### SVE Predicate Logical Operations Group =20 # SVE predicate logical operations --=20 2.17.0 From nobody Wed Oct 29 22:55:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526510857700134.48439963824808; Wed, 16 May 2018 15:47:37 -0700 (PDT) Received: from localhost ([::1]:44878 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ5Cp-00041x-Qs for importer@patchew.org; Wed, 16 May 2018 18:47:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41376) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4wT-0007so-Kd for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ4wR-0007dk-PP for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:41 -0400 Received: from mail-pg0-x22c.google.com ([2607:f8b0:400e:c05::22c]:35982) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ4wR-0007cy-H1 for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:39 -0400 Received: by mail-pg0-x22c.google.com with SMTP id z70-v6so911585pgz.3 for ; Wed, 16 May 2018 15:30:39 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hSZfuMgwOE/1SE9Di94Lbj8Vw7/sXGYNvbfcgxGsF0A=; b=hMpqvJhsIzV59Telyep6ka/aB04PaHdSg9Xn/XMrGT7JhjVZya8S1QVJdbWyWEx4Ad Jv8/GmYdqNo11SKY5b1MXUMrEBGhmSkfHRuTd0+agopvPk0w2c2yrD32FKnzsAkVL/83 NBJx6UMO94UJr1cehOiGc15p3Mrsa3fWTZUUg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hSZfuMgwOE/1SE9Di94Lbj8Vw7/sXGYNvbfcgxGsF0A=; b=If4iRUgqKsLaKFfMW2ZXrtKvSO3aupoPLFhWAa4RV+U0BSgUAHZsALl6wVcC41D0PS 2UnJYuNwJaXeFJOkvLa21P0Ss7iiLC3gjIRthtMfAqBZDi5BXAobEHZ1/pJN4gnaWIjG 0FuHoPOSm+YmTWBvqFy8Al5z+nRiYBNEoBhbg3dXao/3aOhkfQJWN7DZKHHhflt8eXJV gSVYMRvEj5/iZZCVsXSsHaNJkxvTntuhqor8o0MsT2FS4jZ2Ys84+VBGKumEJ6CVIiRM c9ttkPgY4s+OwyGNh0uFYz7lOfHBPRGtvRENTQbcDG1PpuQ2/WVqaZ5UV9yYZa0ynC7m On6w== X-Gm-Message-State: ALKqPwfRteU4YvsBQcjwq4xlVpzF8SDlZAgMiutZmWIurEgbHO/ePXsK 7/aAlZOIVKIjW3WohhBuk2O1vPTDlmw= X-Google-Smtp-Source: AB8JxZoA0h+Ucnd8eqaOPnD77+6lGvYOpDo8bCKLT9sTtAQA2O/yRPDTeO2KX0weJo3/4fdVEZzcVA== X-Received: by 2002:a63:7f1a:: with SMTP id a26-v6mr2101381pgd.371.1526509838142; Wed, 16 May 2018 15:30:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:30:00 -0700 Message-Id: <20180516223007.10256-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22c Subject: [Qemu-devel] [PATCH v3-a 20/27] target/arm: Implement SVE floating-point exponential accelerator X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 4 ++ target/arm/sve_helper.c | 90 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 24 ++++++++++ target/arm/sve.decode | 7 +++ 4 files changed, 125 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 5280d375f9..e2925ff8ec 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -385,6 +385,10 @@ DEF_HELPER_FLAGS_4(sve_adr_p64, TCG_CALL_NO_RWG, void,= ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_adr_s32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_adr_u32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_3(sve_fexpa_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_fexpa_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_fexpa_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 7fa8394aec..6ffb126821 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -1102,3 +1102,93 @@ void HELPER(sve_adr_u32)(void *vd, void *vn, void *v= m, uint32_t desc) d[i] =3D n[i] + ((uint64_t)(uint32_t)m[i] << sh); } } + +void HELPER(sve_fexpa_h)(void *vd, void *vn, uint32_t desc) +{ + /* These constants are cut-and-paste directly from the ARM pseudocode.= */ + static const uint16_t coeff[] =3D { + 0x0000, 0x0016, 0x002d, 0x0045, 0x005d, 0x0075, 0x008e, 0x00a8, + 0x00c2, 0x00dc, 0x00f8, 0x0114, 0x0130, 0x014d, 0x016b, 0x0189, + 0x01a8, 0x01c8, 0x01e8, 0x0209, 0x022b, 0x024e, 0x0271, 0x0295, + 0x02ba, 0x02e0, 0x0306, 0x032e, 0x0356, 0x037f, 0x03a9, 0x03d4, + }; + intptr_t i, opr_sz =3D simd_oprsz(desc) / 2; + uint16_t *d =3D vd, *n =3D vn; + + for (i =3D 0; i < opr_sz; i++) { + uint16_t nn =3D n[i]; + intptr_t idx =3D extract32(nn, 0, 5); + uint16_t exp =3D extract32(nn, 5, 5); + d[i] =3D coeff[idx] | (exp << 10); + } +} + +void HELPER(sve_fexpa_s)(void *vd, void *vn, uint32_t desc) +{ + /* These constants are cut-and-paste directly from the ARM pseudocode.= */ + static const uint32_t coeff[] =3D { + 0x000000, 0x0164d2, 0x02cd87, 0x043a29, + 0x05aac3, 0x071f62, 0x08980f, 0x0a14d5, + 0x0b95c2, 0x0d1adf, 0x0ea43a, 0x1031dc, + 0x11c3d3, 0x135a2b, 0x14f4f0, 0x16942d, + 0x1837f0, 0x19e046, 0x1b8d3a, 0x1d3eda, + 0x1ef532, 0x20b051, 0x227043, 0x243516, + 0x25fed7, 0x27cd94, 0x29a15b, 0x2b7a3a, + 0x2d583f, 0x2f3b79, 0x3123f6, 0x3311c4, + 0x3504f3, 0x36fd92, 0x38fbaf, 0x3aff5b, + 0x3d08a4, 0x3f179a, 0x412c4d, 0x4346cd, + 0x45672a, 0x478d75, 0x49b9be, 0x4bec15, + 0x4e248c, 0x506334, 0x52a81e, 0x54f35b, + 0x5744fd, 0x599d16, 0x5bfbb8, 0x5e60f5, + 0x60ccdf, 0x633f89, 0x65b907, 0x68396a, + 0x6ac0c7, 0x6d4f30, 0x6fe4ba, 0x728177, + 0x75257d, 0x77d0df, 0x7a83b3, 0x7d3e0c, + }; + intptr_t i, opr_sz =3D simd_oprsz(desc) / 4; + uint32_t *d =3D vd, *n =3D vn; + + for (i =3D 0; i < opr_sz; i++) { + uint32_t nn =3D n[i]; + intptr_t idx =3D extract32(nn, 0, 6); + uint32_t exp =3D extract32(nn, 6, 8); + d[i] =3D coeff[idx] | (exp << 23); + } +} + +void HELPER(sve_fexpa_d)(void *vd, void *vn, uint32_t desc) +{ + /* These constants are cut-and-paste directly from the ARM pseudocode.= */ + static const uint64_t coeff[] =3D { + 0x0000000000000ull, 0x02C9A3E778061ull, 0x059B0D3158574ull, + 0x0874518759BC8ull, 0x0B5586CF9890Full, 0x0E3EC32D3D1A2ull, + 0x11301D0125B51ull, 0x1429AAEA92DE0ull, 0x172B83C7D517Bull, + 0x1A35BEB6FCB75ull, 0x1D4873168B9AAull, 0x2063B88628CD6ull, + 0x2387A6E756238ull, 0x26B4565E27CDDull, 0x29E9DF51FDEE1ull, + 0x2D285A6E4030Bull, 0x306FE0A31B715ull, 0x33C08B26416FFull, + 0x371A7373AA9CBull, 0x3A7DB34E59FF7ull, 0x3DEA64C123422ull, + 0x4160A21F72E2Aull, 0x44E086061892Dull, 0x486A2B5C13CD0ull, + 0x4BFDAD5362A27ull, 0x4F9B2769D2CA7ull, 0x5342B569D4F82ull, + 0x56F4736B527DAull, 0x5AB07DD485429ull, 0x5E76F15AD2148ull, + 0x6247EB03A5585ull, 0x6623882552225ull, 0x6A09E667F3BCDull, + 0x6DFB23C651A2Full, 0x71F75E8EC5F74ull, 0x75FEB564267C9ull, + 0x7A11473EB0187ull, 0x7E2F336CF4E62ull, 0x82589994CCE13ull, + 0x868D99B4492EDull, 0x8ACE5422AA0DBull, 0x8F1AE99157736ull, + 0x93737B0CDC5E5ull, 0x97D829FDE4E50ull, 0x9C49182A3F090ull, + 0xA0C667B5DE565ull, 0xA5503B23E255Dull, 0xA9E6B5579FDBFull, + 0xAE89F995AD3ADull, 0xB33A2B84F15FBull, 0xB7F76F2FB5E47ull, + 0xBCC1E904BC1D2ull, 0xC199BDD85529Cull, 0xC67F12E57D14Bull, + 0xCB720DCEF9069ull, 0xD072D4A07897Cull, 0xD5818DCFBA487ull, + 0xDA9E603DB3285ull, 0xDFC97337B9B5Full, 0xE502EE78B3FF6ull, + 0xEA4AFA2A490DAull, 0xEFA1BEE615A27ull, 0xF50765B6E4540ull, + 0xFA7C1819E90D8ull, + }; + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t *d =3D vd, *n =3D vn; + + for (i =3D 0; i < opr_sz; i++) { + uint64_t nn =3D n[i]; + intptr_t idx =3D extract32(nn, 0, 6); + uint64_t exp =3D extract32(nn, 6, 11); + d[i] =3D coeff[idx] | (exp << 52); + } +} diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 8924848463..54d774b5e0 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -929,6 +929,30 @@ static bool trans_ADR_u32(DisasContext *s, arg_rrri *a= , uint32_t insn) return do_adr(s, a, gen_helper_sve_adr_u32); } =20 +/* + *** SVE Integer Misc - Unpredicated Group + */ + +static bool trans_FEXPA(DisasContext *s, arg_rr_esz *a, uint32_t insn) +{ + static gen_helper_gvec_2 * const fns[4] =3D { + NULL, + gen_helper_sve_fexpa_h, + gen_helper_sve_fexpa_s, + gen_helper_sve_fexpa_d, + }; + if (a->esz =3D=3D 0) { + return false; + } + if (sve_access_check(s)) { + unsigned vsz =3D vec_full_reg_size(s); + tcg_gen_gvec_2_ool(vec_full_reg_offset(s, a->rd), + vec_full_reg_offset(s, a->rn), + vsz, vsz, 0, fns[a->esz]); + } + return true; +} + /* *** SVE Predicate Logical Operations Group */ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 691876de4e..cd53b95831 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -66,6 +66,7 @@ =20 # Two operand @pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz +@rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz =20 # Three operand with unused vector element size @rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz e= sz=3D0 @@ -288,6 +289,12 @@ ADR_u32 00000100 01 1 ..... 1010 .. ..... ....= . @rd_rn_msz_rm ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz= _rm ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz= _rm =20 +### SVE Integer Misc - Unpredicated Group + +# SVE floating-point exponential accelerator +# Note esz !=3D 0 +FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn + ### SVE Predicate Logical Operations Group =20 # SVE predicate logical operations --=20 2.17.0 From nobody Wed Oct 29 22:55:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15265114114567.771003100202279; Wed, 16 May 2018 15:56:51 -0700 (PDT) Received: from localhost ([::1]:45749 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ5Lm-0003oz-N2 for importer@patchew.org; Wed, 16 May 2018 18:56:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41395) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4wU-0007sv-A0 for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ4wS-0007gV-Tc for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:42 -0400 Received: from mail-pl0-x236.google.com ([2607:f8b0:400e:c01::236]:45807) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ4wS-0007ez-OA for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:40 -0400 Received: by mail-pl0-x236.google.com with SMTP id bi12-v6so1235769plb.12 for ; Wed, 16 May 2018 15:30:40 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SkJdca9df8jMesnr9raKZw5iQRhGtTAn4Z6Ps+A956I=; b=ZHCfuWvWCHDMHTUfQub04lLmhDM4XD7NiFDQdInkUDH+ciOIrY9OXYWtY3xCx+X0SN nASiHqtZXFj+IAMul0xQtORF6wyfY5IaMIzMuUt6zCdpMy6Yv1O9a+rtRk9fChxKseIb ngld9ANJZIEisauYWsIlTI0+0ve2a0iKYgXb8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SkJdca9df8jMesnr9raKZw5iQRhGtTAn4Z6Ps+A956I=; b=VPbKmoIcYaRgg7IpgKYAPQU8h5aBGwiVASfHkaKg2aIOlNdbVV0ZjXdTBWkffI7R4k Z+CzXJXTlvujJoLQqTjKu57N1EHYlYhJrEIkNwTScgtzwOGESQifMewCSK2nq/wh35wL FHIq/qiGp1c7IIJMcFdco3VYBfIPd7U7DBS/k5TvwvCuUD2/5+oXcpwJlkekIAluOm0+ FMBLTcWw/lfMhFPjfnQZD7ItrTIwHgoaLSrzNyy1WYmn1pj4wL7qxv1HG5+eWDzYKoev SyNqgfvC0PRbOrfppXjr6pEszZjAtQ/kAAVpoAZnTGRhrlQLTD9eJZqvGYirBmt5MSz+ 957w== X-Gm-Message-State: ALKqPwfkpeJxJJ6/Na1GkNm1sNXEtujysOvKLJ/Kn50+N/ZhdFfmu5St eQKuPnjZ8vNMXk8Trjcbc9jGbWvDOFg= X-Google-Smtp-Source: AB8JxZqft+vhRBogNtIm5BxX8UHN0POKIzJYF1S93iVhbhbYavif9tXNG3JFMmtNF+Ze1V628zYoAw== X-Received: by 2002:a17:902:41:: with SMTP id 59-v6mr2696729pla.345.1526509839484; Wed, 16 May 2018 15:30:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:30:01 -0700 Message-Id: <20180516223007.10256-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::236 Subject: [Qemu-devel] [PATCH v3-a 21/27] target/arm: Implement SVE floating-point trig select coefficient X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 4 ++++ target/arm/sve_helper.c | 43 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 21 +++++++++++++++++++ target/arm/sve.decode | 4 ++++ 4 files changed, 72 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index e2925ff8ec..4f1bd5a62f 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -389,6 +389,10 @@ DEF_HELPER_FLAGS_3(sve_fexpa_h, TCG_CALL_NO_RWG, void,= ptr, ptr, i32) DEF_HELPER_FLAGS_3(sve_fexpa_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(sve_fexpa_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_4(sve_ftssel_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_ftssel_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_ftssel_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 6ffb126821..85a0639e3a 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -23,6 +23,7 @@ #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" +#include "fpu/softfloat.h" =20 =20 /* Note that vector data is stored in host-endian 64-bit chunks, @@ -1192,3 +1193,45 @@ void HELPER(sve_fexpa_d)(void *vd, void *vn, uint32_= t desc) d[i] =3D coeff[idx] | (exp << 52); } } + +void HELPER(sve_ftssel_h)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 2; + uint16_t *d =3D vd, *n =3D vn, *m =3D vm; + for (i =3D 0; i < opr_sz; i +=3D 1) { + uint16_t nn =3D n[i]; + uint16_t mm =3D m[i]; + if (mm & 1) { + nn =3D float16_one; + } + d[i] =3D nn ^ (mm & 2) << 14; + } +} + +void HELPER(sve_ftssel_s)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 4; + uint32_t *d =3D vd, *n =3D vn, *m =3D vm; + for (i =3D 0; i < opr_sz; i +=3D 1) { + uint32_t nn =3D n[i]; + uint32_t mm =3D m[i]; + if (mm & 1) { + nn =3D float32_one; + } + d[i] =3D nn ^ (mm & 2) << 30; + } +} + +void HELPER(sve_ftssel_d)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t *d =3D vd, *n =3D vn, *m =3D vm; + for (i =3D 0; i < opr_sz; i +=3D 1) { + uint64_t nn =3D n[i]; + uint64_t mm =3D m[i]; + if (mm & 1) { + nn =3D float64_one; + } + d[i] =3D nn ^ (mm & 2) << 62; + } +} diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 54d774b5e0..ea8d2c4112 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -953,6 +953,27 @@ static bool trans_FEXPA(DisasContext *s, arg_rr_esz *a= , uint32_t insn) return true; } =20 +static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + static gen_helper_gvec_3 * const fns[4] =3D { + NULL, + gen_helper_sve_ftssel_h, + gen_helper_sve_ftssel_s, + gen_helper_sve_ftssel_d, + }; + if (a->esz =3D=3D 0) { + return false; + } + if (sve_access_check(s)) { + unsigned vsz =3D vec_full_reg_size(s); + tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd), + vec_full_reg_offset(s, a->rn), + vec_full_reg_offset(s, a->rm), + vsz, vsz, 0, fns[a->esz]); + } + return true; +} + /* *** SVE Predicate Logical Operations Group */ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index cd53b95831..224dfdd1e9 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -295,6 +295,10 @@ ADR_p64 00000100 11 1 ..... 1010 .. ..... ....= . @rd_rn_msz_rm # Note esz !=3D 0 FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn =20 +# SVE floating-point trig select coefficient +# Note esz !=3D 0 +FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm + ### SVE Predicate Logical Operations Group =20 # SVE predicate logical operations --=20 2.17.0 From nobody Wed Oct 29 22:55:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526510628728793.0287074616131; Wed, 16 May 2018 15:43:48 -0700 (PDT) Received: from localhost ([::1]:44845 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ599-0000tk-Le for importer@patchew.org; Wed, 16 May 2018 18:43:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41450) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4wX-0007wB-5J for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ4wU-0007j8-OH for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:45 -0400 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:45740) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ4wU-0007iP-FV for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:42 -0400 Received: by mail-pg0-x243.google.com with SMTP id w3-v6so886312pgv.12 for ; Wed, 16 May 2018 15:30:42 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=h3k5Lx2BpD0Bum1sIuKXKWkJNyfw0mObCfVucUuPQp4=; b=iKrHbBLs8I+XbBRjw123bRKly0K56cifBGuU3Vxmk4tl1MEUvGRsHIB1D4r8wWEN9Z 1OCL/owUacY8DLF4Ofo3GdhFZ7K1/K3thg72HUNmreXyjGmd7ATTH6gW341lvhDCecvc fQAe5CRkNPhRq+bhqBMhFAlwKfhax8s9BFcQE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=h3k5Lx2BpD0Bum1sIuKXKWkJNyfw0mObCfVucUuPQp4=; b=q01+SSGSPjCNOQlKt2mdryBWLT83hW0coTj14m2OmQ5halb9szGQs51IA3BRyrzHgy PrsQq1QogeK7qA7ha896wd7r5z50NNd9NaDWcKQzUFs6NBYce334UwvodavedDGwTj/6 z0Ja6RVXpOVnHL3NWzKwfTu/iSvaIB3qf9W/JgWhPCA75ugvPRZOjK9Pv7FLKLoZqf+B ZIWLHVn4AfL2Bh3CkRLOIwBSO+ii/jA3QTrtMVdqjrBwjDTl2vu189LO5kZLj9rwNb0V RAPBX5rGA/GUpaOxP5NT/UjzY5sshSK5cDu1Cy303eqFhLz53WZrKytRicVR/8zrLwQo YDPw== X-Gm-Message-State: ALKqPwfGdSSfvExXtiBR6RU/oEk2fmFmITLsQzzTewpcbj0f3gGx+10S SyMl3WrB0Uv+adIyyTzFqx6dDPPAJx4= X-Google-Smtp-Source: AB8JxZqg3rZYuRKW9WA3sjxlUv9HR0BXhj3znXvSfV2ywudv1ZbUzK4xOFGubVv23foZB4ZqY0Jt9Q== X-Received: by 2002:a62:f20d:: with SMTP id m13-v6mr2780394pfh.170.1526509840841; Wed, 16 May 2018 15:30:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:30:02 -0700 Message-Id: <20180516223007.10256-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v3-a 22/27] target/arm: Implement SVE Element Count Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 11 ++ target/arm/sve_helper.c | 136 ++++++++++++++++++ target/arm/translate-sve.c | 288 +++++++++++++++++++++++++++++++++++++ target/arm/sve.decode | 31 +++- 4 files changed, 465 insertions(+), 1 deletion(-) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 4f1bd5a62f..2831e1643b 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -393,6 +393,17 @@ DEF_HELPER_FLAGS_4(sve_ftssel_h, TCG_CALL_NO_RWG, void= , ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_ftssel_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_ftssel_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_4(sve_sqaddi_b, TCG_CALL_NO_RWG, void, ptr, ptr, s32, i32) +DEF_HELPER_FLAGS_4(sve_sqaddi_h, TCG_CALL_NO_RWG, void, ptr, ptr, s32, i32) +DEF_HELPER_FLAGS_4(sve_sqaddi_s, TCG_CALL_NO_RWG, void, ptr, ptr, s64, i32) +DEF_HELPER_FLAGS_4(sve_sqaddi_d, TCG_CALL_NO_RWG, void, ptr, ptr, s64, i32) + +DEF_HELPER_FLAGS_4(sve_uqaddi_b, TCG_CALL_NO_RWG, void, ptr, ptr, s32, i32) +DEF_HELPER_FLAGS_4(sve_uqaddi_h, TCG_CALL_NO_RWG, void, ptr, ptr, s32, i32) +DEF_HELPER_FLAGS_4(sve_uqaddi_s, TCG_CALL_NO_RWG, void, ptr, ptr, s64, i32) +DEF_HELPER_FLAGS_4(sve_uqaddi_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(sve_uqsubi_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) + DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 85a0639e3a..979aa5c409 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -1235,3 +1235,139 @@ void HELPER(sve_ftssel_d)(void *vd, void *vn, void = *vm, uint32_t desc) d[i] =3D nn ^ (mm & 2) << 62; } } + +/* + * Signed saturating addition with scalar operand. + */ + +void HELPER(sve_sqaddi_b)(void *d, void *a, int32_t b, uint32_t desc) +{ + intptr_t i, oprsz =3D simd_oprsz(desc); + + for (i =3D 0; i < oprsz; i +=3D sizeof(int8_t)) { + int r =3D *(int8_t *)(a + i) + b; + if (r > INT8_MAX) { + r =3D INT8_MAX; + } else if (r < INT8_MIN) { + r =3D INT8_MIN; + } + *(int8_t *)(d + i) =3D r; + } +} + +void HELPER(sve_sqaddi_h)(void *d, void *a, int32_t b, uint32_t desc) +{ + intptr_t i, oprsz =3D simd_oprsz(desc); + + for (i =3D 0; i < oprsz; i +=3D sizeof(int16_t)) { + int r =3D *(int16_t *)(a + i) + b; + if (r > INT16_MAX) { + r =3D INT16_MAX; + } else if (r < INT16_MIN) { + r =3D INT16_MIN; + } + *(int16_t *)(d + i) =3D r; + } +} + +void HELPER(sve_sqaddi_s)(void *d, void *a, int64_t b, uint32_t desc) +{ + intptr_t i, oprsz =3D simd_oprsz(desc); + + for (i =3D 0; i < oprsz; i +=3D sizeof(int32_t)) { + int64_t r =3D *(int32_t *)(a + i) + b; + if (r > INT32_MAX) { + r =3D INT32_MAX; + } else if (r < INT32_MIN) { + r =3D INT32_MIN; + } + *(int32_t *)(d + i) =3D r; + } +} + +void HELPER(sve_sqaddi_d)(void *d, void *a, int64_t b, uint32_t desc) +{ + intptr_t i, oprsz =3D simd_oprsz(desc); + + for (i =3D 0; i < oprsz; i +=3D sizeof(int64_t)) { + int64_t ai =3D *(int64_t *)(a + i); + int64_t r =3D ai + b; + if (((r ^ ai) & ~(ai ^ b)) < 0) { + /* Signed overflow. */ + r =3D (r < 0 ? INT64_MAX : INT64_MIN); + } + *(int64_t *)(d + i) =3D r; + } +} + +/* + * Unsigned saturating addition with scalar operand. + */ + +void HELPER(sve_uqaddi_b)(void *d, void *a, int32_t b, uint32_t desc) +{ + intptr_t i, oprsz =3D simd_oprsz(desc); + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint8_t)) { + int r =3D *(uint8_t *)(a + i) + b; + if (r > UINT8_MAX) { + r =3D UINT8_MAX; + } else if (r < 0) { + r =3D 0; + } + *(uint8_t *)(d + i) =3D r; + } +} + +void HELPER(sve_uqaddi_h)(void *d, void *a, int32_t b, uint32_t desc) +{ + intptr_t i, oprsz =3D simd_oprsz(desc); + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint16_t)) { + int r =3D *(uint16_t *)(a + i) + b; + if (r > UINT16_MAX) { + r =3D UINT16_MAX; + } else if (r < 0) { + r =3D 0; + } + *(uint16_t *)(d + i) =3D r; + } +} + +void HELPER(sve_uqaddi_s)(void *d, void *a, int64_t b, uint32_t desc) +{ + intptr_t i, oprsz =3D simd_oprsz(desc); + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint32_t)) { + int64_t r =3D *(uint32_t *)(a + i) + b; + if (r > UINT32_MAX) { + r =3D UINT32_MAX; + } else if (r < 0) { + r =3D 0; + } + *(uint32_t *)(d + i) =3D r; + } +} + +void HELPER(sve_uqaddi_d)(void *d, void *a, uint64_t b, uint32_t desc) +{ + intptr_t i, oprsz =3D simd_oprsz(desc); + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint64_t)) { + uint64_t r =3D *(uint64_t *)(a + i) + b; + if (r < b) { + r =3D UINT64_MAX; + } + *(uint64_t *)(d + i) =3D r; + } +} + +void HELPER(sve_uqsubi_d)(void *d, void *a, uint64_t b, uint32_t desc) +{ + intptr_t i, oprsz =3D simd_oprsz(desc); + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint64_t)) { + uint64_t ai =3D *(uint64_t *)(a + i); + *(uint64_t *)(d + i) =3D (ai < b ? 0 : ai - b); + } +} diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index ea8d2c4112..2a0bf6b47c 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -57,6 +57,11 @@ static int tszimm_shl(int x) return x - (8 << tszimm_esz(x)); } =20 +static inline int plus1(int x) +{ + return x + 1; +} + /* * Include the generated decoder. */ @@ -1497,6 +1502,289 @@ static bool trans_PNEXT(DisasContext *s, arg_rr_esz= *a, uint32_t insn) return do_pfirst_pnext(s, a, gen_helper_sve_pnext); } =20 +/* + *** SVE Element Count Group + */ + +/* Perform an inline saturating addition of a 32-bit value within + * a 64-bit register. The second operand is known to be positive, + * which halves the comparisions we must perform to bound the result. + */ +static void do_sat_addsub_32(TCGv_i64 reg, TCGv_i64 val, bool u, bool d) +{ + int64_t ibound; + TCGv_i64 bound; + TCGCond cond; + + /* Use normal 64-bit arithmetic to detect 32-bit overflow. */ + if (u) { + tcg_gen_ext32u_i64(reg, reg); + } else { + tcg_gen_ext32s_i64(reg, reg); + } + if (d) { + tcg_gen_sub_i64(reg, reg, val); + ibound =3D (u ? 0 : INT32_MIN); + cond =3D TCG_COND_LT; + } else { + tcg_gen_add_i64(reg, reg, val); + ibound =3D (u ? UINT32_MAX : INT32_MAX); + cond =3D TCG_COND_GT; + } + bound =3D tcg_const_i64(ibound); + tcg_gen_movcond_i64(cond, reg, reg, bound, bound, reg); + tcg_temp_free_i64(bound); +} + +/* Similarly with 64-bit values. */ +static void do_sat_addsub_64(TCGv_i64 reg, TCGv_i64 val, bool u, bool d) +{ + TCGv_i64 t0 =3D tcg_temp_new_i64(); + TCGv_i64 t1 =3D tcg_temp_new_i64(); + TCGv_i64 t2; + + if (u) { + if (d) { + tcg_gen_sub_i64(t0, reg, val); + tcg_gen_movi_i64(t1, 0); + tcg_gen_movcond_i64(TCG_COND_LTU, reg, reg, val, t1, t0); + } else { + tcg_gen_add_i64(t0, reg, val); + tcg_gen_movi_i64(t1, -1); + tcg_gen_movcond_i64(TCG_COND_LTU, reg, t0, reg, t1, t0); + } + } else { + if (d) { + /* Detect signed overflow for subtraction. */ + tcg_gen_xor_i64(t0, reg, val); + tcg_gen_sub_i64(t1, reg, val); + tcg_gen_xor_i64(reg, reg, t0); + tcg_gen_and_i64(t0, t0, reg); + + /* Bound the result. */ + tcg_gen_movi_i64(reg, INT64_MIN); + t2 =3D tcg_const_i64(0); + tcg_gen_movcond_i64(TCG_COND_LT, reg, t0, t2, reg, t1); + } else { + /* Detect signed overflow for addition. */ + tcg_gen_xor_i64(t0, reg, val); + tcg_gen_add_i64(reg, reg, val); + tcg_gen_xor_i64(t1, reg, val); + tcg_gen_andc_i64(t0, t1, t0); + + /* Bound the result. */ + tcg_gen_movi_i64(t1, INT64_MAX); + t2 =3D tcg_const_i64(0); + tcg_gen_movcond_i64(TCG_COND_LT, reg, t0, t2, t1, reg); + } + tcg_temp_free_i64(t2); + } + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); +} + +/* Similarly with a vector and a scalar operand. */ +static void do_sat_addsub_vec(DisasContext *s, int esz, int rd, int rn, + TCGv_i64 val, bool u, bool d) +{ + unsigned vsz =3D vec_full_reg_size(s); + TCGv_ptr dptr, nptr; + TCGv_i32 t32, desc; + TCGv_i64 t64; + + dptr =3D tcg_temp_new_ptr(); + nptr =3D tcg_temp_new_ptr(); + tcg_gen_addi_ptr(dptr, cpu_env, vec_full_reg_offset(s, rd)); + tcg_gen_addi_ptr(nptr, cpu_env, vec_full_reg_offset(s, rn)); + desc =3D tcg_const_i32(simd_desc(vsz, vsz, 0)); + + switch (esz) { + case MO_8: + t32 =3D tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(t32, val); + if (d) { + tcg_gen_neg_i32(t32, t32); + } + if (u) { + gen_helper_sve_uqaddi_b(dptr, nptr, t32, desc); + } else { + gen_helper_sve_sqaddi_b(dptr, nptr, t32, desc); + } + tcg_temp_free_i32(t32); + break; + + case MO_16: + t32 =3D tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(t32, val); + if (d) { + tcg_gen_neg_i32(t32, t32); + } + if (u) { + gen_helper_sve_uqaddi_h(dptr, nptr, t32, desc); + } else { + gen_helper_sve_sqaddi_h(dptr, nptr, t32, desc); + } + tcg_temp_free_i32(t32); + break; + + case MO_32: + t64 =3D tcg_temp_new_i64(); + if (d) { + tcg_gen_neg_i64(t64, val); + } else { + tcg_gen_mov_i64(t64, val); + } + if (u) { + gen_helper_sve_uqaddi_s(dptr, nptr, t64, desc); + } else { + gen_helper_sve_sqaddi_s(dptr, nptr, t64, desc); + } + tcg_temp_free_i64(t64); + break; + + case MO_64: + if (u) { + if (d) { + gen_helper_sve_uqsubi_d(dptr, nptr, val, desc); + } else { + gen_helper_sve_uqaddi_d(dptr, nptr, val, desc); + } + } else if (d) { + t64 =3D tcg_temp_new_i64(); + tcg_gen_neg_i64(t64, val); + gen_helper_sve_sqaddi_d(dptr, nptr, t64, desc); + tcg_temp_free_i64(t64); + } else { + gen_helper_sve_sqaddi_d(dptr, nptr, val, desc); + } + break; + + default: + g_assert_not_reached(); + } + + tcg_temp_free_ptr(dptr); + tcg_temp_free_ptr(nptr); + tcg_temp_free_i32(desc); +} + +static bool trans_CNT_r(DisasContext *s, arg_CNT_r *a, uint32_t insn) +{ + if (sve_access_check(s)) { + unsigned fullsz =3D vec_full_reg_size(s); + unsigned numelem =3D decode_pred_count(fullsz, a->pat, a->esz); + tcg_gen_movi_i64(cpu_reg(s, a->rd), numelem * a->imm); + } + return true; +} + +static bool trans_INCDEC_r(DisasContext *s, arg_incdec_cnt *a, uint32_t in= sn) +{ + if (sve_access_check(s)) { + unsigned fullsz =3D vec_full_reg_size(s); + unsigned numelem =3D decode_pred_count(fullsz, a->pat, a->esz); + int inc =3D numelem * a->imm * (a->d ? -1 : 1); + TCGv_i64 reg =3D cpu_reg(s, a->rd); + + tcg_gen_addi_i64(reg, reg, inc); + } + return true; +} + +static bool trans_SINCDEC_r_32(DisasContext *s, arg_incdec_cnt *a, + uint32_t insn) +{ + if (!sve_access_check(s)) { + return true; + } + + unsigned fullsz =3D vec_full_reg_size(s); + unsigned numelem =3D decode_pred_count(fullsz, a->pat, a->esz); + int inc =3D numelem * a->imm; + TCGv_i64 reg =3D cpu_reg(s, a->rd); + + /* Use normal 64-bit arithmetic to detect 32-bit overflow. */ + if (inc =3D=3D 0) { + if (a->u) { + tcg_gen_ext32u_i64(reg, reg); + } else { + tcg_gen_ext32s_i64(reg, reg); + } + } else { + TCGv_i64 t =3D tcg_const_i64(inc); + do_sat_addsub_32(reg, t, a->u, a->d); + tcg_temp_free_i64(t); + } + return true; +} + +static bool trans_SINCDEC_r_64(DisasContext *s, arg_incdec_cnt *a, + uint32_t insn) +{ + if (!sve_access_check(s)) { + return true; + } + + unsigned fullsz =3D vec_full_reg_size(s); + unsigned numelem =3D decode_pred_count(fullsz, a->pat, a->esz); + int inc =3D numelem * a->imm; + TCGv_i64 reg =3D cpu_reg(s, a->rd); + + if (inc !=3D 0) { + TCGv_i64 t =3D tcg_const_i64(inc); + do_sat_addsub_64(reg, t, a->u, a->d); + tcg_temp_free_i64(t); + } + return true; +} + +static bool trans_INCDEC_v(DisasContext *s, arg_incdec2_cnt *a, uint32_t i= nsn) +{ + if (a->esz =3D=3D 0) { + return false; + } + + unsigned fullsz =3D vec_full_reg_size(s); + unsigned numelem =3D decode_pred_count(fullsz, a->pat, a->esz); + int inc =3D numelem * a->imm; + + if (inc !=3D 0) { + if (sve_access_check(s)) { + TCGv_i64 t =3D tcg_const_i64(a->d ? -inc : inc); + tcg_gen_gvec_adds(a->esz, vec_full_reg_offset(s, a->rd), + vec_full_reg_offset(s, a->rn), + t, fullsz, fullsz); + tcg_temp_free_i64(t); + } + } else { + do_mov_z(s, a->rd, a->rn); + } + return true; +} + +static bool trans_SINCDEC_v(DisasContext *s, arg_incdec2_cnt *a, + uint32_t insn) +{ + if (a->esz =3D=3D 0) { + return false; + } + + unsigned fullsz =3D vec_full_reg_size(s); + unsigned numelem =3D decode_pred_count(fullsz, a->pat, a->esz); + int inc =3D numelem * a->imm; + + if (inc !=3D 0) { + if (sve_access_check(s)) { + TCGv_i64 t =3D tcg_const_i64(inc); + do_sat_addsub_vec(s, a->esz, a->rd, a->rn, t, a->u, a->d); + tcg_temp_free_i64(t); + } + } else { + do_mov_z(s, a->rd, a->rn); + } + return true; +} + /* *** SVE Memory - 32-bit Gather and Unsized Contiguous Group */ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 224dfdd1e9..b6890d0410 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -22,6 +22,7 @@ ########################################################################### # Named fields. These are primarily for disjoint fields. =20 +%imm4_16_p1 16:4 !function=3Dplus1 %imm6_22_5 22:1 5:5 %imm9_16_10 16:s6 10:3 =20 @@ -56,6 +57,9 @@ &rprr_esz rd pg rn rm esz &rprrr_esz rd pg rn rm ra esz &rpri_esz rd pg rn imm esz +&ptrue rd esz pat s +&incdec_cnt rd pat esz imm d u +&incdec2_cnt rd rn pat esz imm d u =20 ########################################################################### # Named instruction formats. These are generally used to @@ -113,6 +117,13 @@ @rd_rn_i9 ........ ........ ...... rn:5 rd:5 \ &rri imm=3D%imm9_16_10 =20 +# One register, pattern, and uint4+1. +# User must fill in U and D. +@incdec_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ + &incdec_cnt imm=3D%imm4_16_p1 +@incdec2_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ + &incdec2_cnt imm=3D%imm4_16_p1 rn=3D%reg_movprfx + ########################################################################### # Instruction patterns. Grouped according to the SVE encodingindex.xhtml. =20 @@ -299,7 +310,25 @@ FEXPA 00000100 .. 1 00000 101110 ..... .....= @rd_rn # Note esz !=3D 0 FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm =20 -### SVE Predicate Logical Operations Group +### SVE Element Count Group + +# SVE element count +CNT_r 00000100 .. 10 .... 1110 0 0 ..... ..... @incdec_cnt d= =3D0 u=3D1 + +# SVE inc/dec register by element count +INCDEC_r 00000100 .. 11 .... 1110 0 d:1 ..... ..... @incdec_cn= t u=3D1 + +# SVE saturating inc/dec register by element count +SINCDEC_r_32 00000100 .. 10 .... 1111 d:1 u:1 ..... ..... @incdec_cnt +SINCDEC_r_64 00000100 .. 11 .... 1111 d:1 u:1 ..... ..... @incdec_cnt + +# SVE inc/dec vector by element count +# Note this requires esz !=3D 0. +INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... ..... @incdec2_cn= t u=3D1 + +# SVE saturating inc/dec vector by element count +# Note these require esz !=3D 0. +SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_c= nt =20 # SVE predicate logical operations AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_= pm_s --=20 2.17.0 From nobody Wed Oct 29 22:55:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526511115471440.51257527557357; Wed, 16 May 2018 15:51:55 -0700 (PDT) Received: from localhost ([::1]:45153 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ5Gy-0007m9-2M for importer@patchew.org; Wed, 16 May 2018 18:51:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41457) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4wX-0007wb-CM for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ4wW-0007kF-Ac for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:45 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:44469) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ4wW-0007jg-4h for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:44 -0400 Received: by mail-pf0-x241.google.com with SMTP id q22-v6so1047896pff.11 for ; Wed, 16 May 2018 15:30:44 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BEjxDmQze6EQ4PzVRaaLNekGTTeM3A4GM6iFc1co+Hs=; b=IwZdBhIKAwcNc90m9pcvEo7DLvIyY0zquTGlijoXyY+8eQaxnumJCduqlW4ZU5sbsQ DONu+RG6DSnb1w4P2RvFrQGe7zSnrzwYuKOItwEvkLcyrTZ02FnJphOF0jAoMfZSRc3c /337UJZabnUqlKC8i1nk7r4Gvx3buC6+cZvYc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BEjxDmQze6EQ4PzVRaaLNekGTTeM3A4GM6iFc1co+Hs=; b=t7w+1tMha9NwlkB2wenEOlS5u5a/l1+U+ahGCnqfNDr1gkpKfQHWehr+Kas1utK1tO wkkzR3o2jadYHwGEzxiH0SZqBfUWie0JzbfQ3qrbfI8HSyYVQsxnaSDfmDDxF1C0U9Yr PEDiNITpA2+QZkl7H/jHvz57dYjLzjYBF3BrUw/WnhiiddPTi88EuldRKJodYDWS+r51 EKqtjgjz6SIyi6O0R3wgGxLRhCOFtF3nV5Za/b9pREhK8ChHkr3mPaByZWZvI5TM76Jf 0itvHQ+GRxZqL4EA97nhdXgL94fPlroYAJejSqR0Yf8YXXi6FpZUwg8kcKGGt0/74ULa LnBw== X-Gm-Message-State: ALKqPweaRbS4qC5vxJvRemBhJRm73JRud35jVvUggDDmPoqg4GlQehlS YHBCjmerpwPnJkY6l8ig0/xQ9dmHOgs= X-Google-Smtp-Source: AB8JxZrBzVs8JKUKnBCtPl/fstBrR51VNq4AVkpEFhjMBIaKuGSsNxfciwIoFcjjvyzRrQBjBXbNYw== X-Received: by 2002:a65:47c8:: with SMTP id f8-v6mr2152625pgs.430.1526509842802; Wed, 16 May 2018 15:30:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:30:03 -0700 Message-Id: <20180516223007.10256-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v3-a 23/27] target/arm: Implement SVE Bitwise Immediate Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 49 ++++++++++++++++++++++++++++++++++++++ target/arm/sve.decode | 17 +++++++++++++ 2 files changed, 66 insertions(+) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 2a0bf6b47c..9d7c18c48d 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -1785,6 +1785,55 @@ static bool trans_SINCDEC_v(DisasContext *s, arg_inc= dec2_cnt *a, return true; } =20 +/* + *** SVE Bitwise Immediate Group + */ + +static bool do_zz_dbm(DisasContext *s, arg_rr_dbm *a, GVecGen2iFn *gvec_fn) +{ + uint64_t imm; + if (!logic_imm_decode_wmask(&imm, extract32(a->dbm, 12, 1), + extract32(a->dbm, 0, 6), + extract32(a->dbm, 6, 6))) { + return false; + } + if (sve_access_check(s)) { + unsigned vsz =3D vec_full_reg_size(s); + gvec_fn(MO_64, vec_full_reg_offset(s, a->rd), + vec_full_reg_offset(s, a->rn), imm, vsz, vsz); + } + return true; +} + +static bool trans_AND_zzi(DisasContext *s, arg_rr_dbm *a, uint32_t insn) +{ + return do_zz_dbm(s, a, tcg_gen_gvec_andi); +} + +static bool trans_ORR_zzi(DisasContext *s, arg_rr_dbm *a, uint32_t insn) +{ + return do_zz_dbm(s, a, tcg_gen_gvec_ori); +} + +static bool trans_EOR_zzi(DisasContext *s, arg_rr_dbm *a, uint32_t insn) +{ + return do_zz_dbm(s, a, tcg_gen_gvec_xori); +} + +static bool trans_DUPM(DisasContext *s, arg_DUPM *a, uint32_t insn) +{ + uint64_t imm; + if (!logic_imm_decode_wmask(&imm, extract32(a->dbm, 12, 1), + extract32(a->dbm, 0, 6), + extract32(a->dbm, 6, 6))) { + return false; + } + if (sve_access_check(s)) { + do_dupi_z(s, a->rd, imm); + } + return true; +} + /* *** SVE Memory - 32-bit Gather and Unsized Contiguous Group */ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index b6890d0410..a3277a0d21 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -49,6 +49,7 @@ =20 &rr_esz rd rn esz &rri rd rn imm +&rr_dbm rd rn dbm &rrri rd rn rm imm &rri_esz rd rn imm esz &rrr_esz rd rn rm esz @@ -111,6 +112,10 @@ @rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \ &rri_esz esz=3D%tszimm16_esz =20 +# Two register operand, one encoded bitmask. +@rdn_dbm ........ .. .... dbm:13 rd:5 \ + &rr_dbm rn=3D%reg_movprfx + # Basic Load/Store with 9-bit immediate offset @pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \ &rri imm=3D%imm9_16_10 @@ -330,6 +335,18 @@ INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... = ..... @incdec2_cnt u=3D1 # Note these require esz !=3D 0. SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_c= nt =20 +### SVE Bitwise Immediate Group + +# SVE bitwise logical with immediate (unpredicated) +ORR_zzi 00000101 00 0000 ............. ..... @rdn_dbm +EOR_zzi 00000101 01 0000 ............. ..... @rdn_dbm +AND_zzi 00000101 10 0000 ............. ..... @rdn_dbm + +# SVE broadcast bitmask immediate +DUPM 00000101 11 0000 dbm:13 rd:5 + +### SVE Predicate Logical Operations Group + # SVE predicate logical operations AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_= pm_s BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_= pm_s --=20 2.17.0 From nobody Wed Oct 29 22:55:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526511256293644.2749222955798; Wed, 16 May 2018 15:54:16 -0700 (PDT) Received: from localhost ([::1]:45471 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ5JE-0001d2-3g for importer@patchew.org; Wed, 16 May 2018 18:54:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41495) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4wZ-0007zc-Jm for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ4wX-0007lb-Sf for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:47 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:45741) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ4wX-0007kq-HH for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:45 -0400 Received: by mail-pg0-x244.google.com with SMTP id w3-v6so886350pgv.12 for ; Wed, 16 May 2018 15:30:45 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5G3npuaUGGTDzTHF/+K7xrkhnr6K2y2tGIFOkbvCuNU=; b=W2ghgSfy1B8vH/XmjV6P0qUurM7NHKpIx837RLP1FLDRFS3vWxFjD/3pVCjci1uJkN QTZ1Fh8JS16UkUz8//Fybydtqz+DuGSizfzPjE+39966KxvUyK6VHYzPMWgnDoTAC7mh sO7/GHTpUJkcRlSlRk9PySqiHrabB7Tzh6Bek= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5G3npuaUGGTDzTHF/+K7xrkhnr6K2y2tGIFOkbvCuNU=; b=DC/O4oMRhFQrf9bshRaSSZBmEyt7mG71F+xx5c9N2NMZ98b/PLdZEqDuKxUOE14DMK AtZOj08vOlBH6wAf+h/NEAeovcTIMPoxYGghp95+2uY7s03xro+Jesi/+YMxYOJ2C7on uaFCiPo3rQGvZyhzZA1GwsiGMxJHRx8n5szzc6g40/Th8k1F8j+SRAK4d1yduYqtsVqF biybsgskNyccu1iaPLPXb0Jct40IEz6QqwZReJLcxVDFHdBEolSXjwdWFKPcUi/ihMHx xzIbJEeU2lGZg1tFUA0b68qxx2AXPkMDBANtjzjTWYL+HZevygZ9aRM2th2dfM6sLmfb 9hsQ== X-Gm-Message-State: ALKqPwfYKXig4MpKl7IhS0yZ09+sFbsO9RMnowFL3+wd2306S975h/Y7 Wirgjka9lDgtK2nBpOP5F0PSDKBOYH4= X-Google-Smtp-Source: AB8JxZpPTrW7EE5N5PH62ow2An2U3fSnsgeb3J/fSuf77v7xZJiuYFIBV8hLPH9FciLsdoS9nn3MxQ== X-Received: by 2002:a62:6756:: with SMTP id b83-v6mr2786961pfc.76.1526509844114; Wed, 16 May 2018 15:30:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:30:04 -0700 Message-Id: <20180516223007.10256-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v3-a 24/27] target/arm: Implement SVE Integer Wide Immediate - Predicated Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 10 ++++ target/arm/sve_helper.c | 108 +++++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 88 ++++++++++++++++++++++++++++++ target/arm/sve.decode | 19 ++++++- 4 files changed, 224 insertions(+), 1 deletion(-) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 2831e1643b..79493ab647 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -404,6 +404,16 @@ DEF_HELPER_FLAGS_4(sve_uqaddi_s, TCG_CALL_NO_RWG, void= , ptr, ptr, s64, i32) DEF_HELPER_FLAGS_4(sve_uqaddi_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) DEF_HELPER_FLAGS_4(sve_uqsubi_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) =20 +DEF_HELPER_FLAGS_5(sve_cpy_m_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i64,= i32) +DEF_HELPER_FLAGS_5(sve_cpy_m_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i64,= i32) +DEF_HELPER_FLAGS_5(sve_cpy_m_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i64,= i32) +DEF_HELPER_FLAGS_5(sve_cpy_m_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i64,= i32) + +DEF_HELPER_FLAGS_4(sve_cpy_z_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(sve_cpy_z_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(sve_cpy_z_s, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(sve_cpy_z_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) + DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 979aa5c409..8c7ea989b1 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -1371,3 +1371,111 @@ void HELPER(sve_uqsubi_d)(void *d, void *a, uint64_= t b, uint32_t desc) *(uint64_t *)(d + i) =3D (ai < b ? 0 : ai - b); } } + +/* Two operand predicated copy immediate with merge. All valid immediates + * can fit within 17 signed bits in the simd_data field. + */ +void HELPER(sve_cpy_m_b)(void *vd, void *vn, void *vg, + uint64_t mm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t *d =3D vd, *n =3D vn; + uint8_t *pg =3D vg; + + mm =3D dup_const(MO_8, mm); + for (i =3D 0; i < opr_sz; i +=3D 1) { + uint64_t nn =3D n[i]; + uint64_t pp =3D expand_pred_b(pg[H1(i)]); + d[i] =3D (mm & pp) | (nn & ~pp); + } +} + +void HELPER(sve_cpy_m_h)(void *vd, void *vn, void *vg, + uint64_t mm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t *d =3D vd, *n =3D vn; + uint8_t *pg =3D vg; + + mm =3D dup_const(MO_16, mm); + for (i =3D 0; i < opr_sz; i +=3D 1) { + uint64_t nn =3D n[i]; + uint64_t pp =3D expand_pred_h(pg[H1(i)]); + d[i] =3D (mm & pp) | (nn & ~pp); + } +} + +void HELPER(sve_cpy_m_s)(void *vd, void *vn, void *vg, + uint64_t mm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t *d =3D vd, *n =3D vn; + uint8_t *pg =3D vg; + + mm =3D dup_const(MO_32, mm); + for (i =3D 0; i < opr_sz; i +=3D 1) { + uint64_t nn =3D n[i]; + uint64_t pp =3D expand_pred_s(pg[H1(i)]); + d[i] =3D (mm & pp) | (nn & ~pp); + } +} + +void HELPER(sve_cpy_m_d)(void *vd, void *vn, void *vg, + uint64_t mm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t *d =3D vd, *n =3D vn; + uint8_t *pg =3D vg; + + for (i =3D 0; i < opr_sz; i +=3D 1) { + uint64_t nn =3D n[i]; + d[i] =3D (pg[H1(i)] & 1 ? mm : nn); + } +} + +void HELPER(sve_cpy_z_b)(void *vd, void *vg, uint64_t val, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t *d =3D vd; + uint8_t *pg =3D vg; + + val =3D dup_const(MO_8, val); + for (i =3D 0; i < opr_sz; i +=3D 1) { + d[i] =3D val & expand_pred_b(pg[H1(i)]); + } +} + +void HELPER(sve_cpy_z_h)(void *vd, void *vg, uint64_t val, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t *d =3D vd; + uint8_t *pg =3D vg; + + val =3D dup_const(MO_16, val); + for (i =3D 0; i < opr_sz; i +=3D 1) { + d[i] =3D val & expand_pred_h(pg[H1(i)]); + } +} + +void HELPER(sve_cpy_z_s)(void *vd, void *vg, uint64_t val, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t *d =3D vd; + uint8_t *pg =3D vg; + + val =3D dup_const(MO_32, val); + for (i =3D 0; i < opr_sz; i +=3D 1) { + d[i] =3D val & expand_pred_s(pg[H1(i)]); + } +} + +void HELPER(sve_cpy_z_d)(void *vd, void *vg, uint64_t val, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t *d =3D vd; + uint8_t *pg =3D vg; + + for (i =3D 0; i < opr_sz; i +=3D 1) { + d[i] =3D (pg[H1(i)] & 1 ? val : 0); + } +} diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 9d7c18c48d..9bdd61ff84 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -62,6 +62,12 @@ static inline int plus1(int x) return x + 1; } =20 +/* The SH bit is in bit 8. Extract the low 8 and shift. */ +static inline int expand_imm_sh8s(int x) +{ + return (int8_t)x << (x & 0x100 ? 8 : 0); +} + /* * Include the generated decoder. */ @@ -1834,6 +1840,88 @@ static bool trans_DUPM(DisasContext *s, arg_DUPM *a,= uint32_t insn) return true; } =20 +/* + *** SVE Integer Wide Immediate - Predicated Group + */ + +/* Implement all merging copies. This is used for CPY (immediate), + * FCPY, CPY (scalar), CPY (SIMD&FP scalar). + */ +static void do_cpy_m(DisasContext *s, int esz, int rd, int rn, int pg, + TCGv_i64 val) +{ + typedef void gen_cpy(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_i32); + static gen_cpy * const fns[4] =3D { + gen_helper_sve_cpy_m_b, gen_helper_sve_cpy_m_h, + gen_helper_sve_cpy_m_s, gen_helper_sve_cpy_m_d, + }; + unsigned vsz =3D vec_full_reg_size(s); + TCGv_i32 desc =3D tcg_const_i32(simd_desc(vsz, vsz, 0)); + TCGv_ptr t_zd =3D tcg_temp_new_ptr(); + TCGv_ptr t_zn =3D tcg_temp_new_ptr(); + TCGv_ptr t_pg =3D tcg_temp_new_ptr(); + + tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, rd)); + tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, rn)); + tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); + + fns[esz](t_zd, t_zn, t_pg, val, desc); + + tcg_temp_free_ptr(t_zd); + tcg_temp_free_ptr(t_zn); + tcg_temp_free_ptr(t_pg); + tcg_temp_free_i32(desc); +} + +static bool trans_FCPY(DisasContext *s, arg_FCPY *a, uint32_t insn) +{ + if (a->esz =3D=3D 0) { + return false; + } + if (sve_access_check(s)) { + /* Decode the VFP immediate. */ + uint64_t imm =3D vfp_expand_imm(a->esz, a->imm); + TCGv_i64 t_imm =3D tcg_const_i64(imm); + do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, t_imm); + tcg_temp_free_i64(t_imm); + } + return true; +} + +static bool trans_CPY_m_i(DisasContext *s, arg_rpri_esz *a, uint32_t insn) +{ + if (a->esz =3D=3D 0 && extract32(insn, 13, 1)) { + return false; + } + if (sve_access_check(s)) { + TCGv_i64 t_imm =3D tcg_const_i64(a->imm); + do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, t_imm); + tcg_temp_free_i64(t_imm); + } + return true; +} + +static bool trans_CPY_z_i(DisasContext *s, arg_CPY_z_i *a, uint32_t insn) +{ + static gen_helper_gvec_2i * const fns[4] =3D { + gen_helper_sve_cpy_z_b, gen_helper_sve_cpy_z_h, + gen_helper_sve_cpy_z_s, gen_helper_sve_cpy_z_d, + }; + + if (a->esz =3D=3D 0 && extract32(insn, 13, 1)) { + return false; + } + if (sve_access_check(s)) { + unsigned vsz =3D vec_full_reg_size(s); + TCGv_i64 t_imm =3D tcg_const_i64(a->imm); + tcg_gen_gvec_2i_ool(vec_full_reg_offset(s, a->rd), + pred_full_reg_offset(s, a->pg), + t_imm, vsz, vsz, 0, fns[a->esz]); + tcg_temp_free_i64(t_imm); + } + return true; +} + /* *** SVE Memory - 32-bit Gather and Unsized Contiguous Group */ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index a3277a0d21..4ee7c78cda 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -22,7 +22,7 @@ ########################################################################### # Named fields. These are primarily for disjoint fields. =20 -%imm4_16_p1 16:4 !function=3Dplus1 +%imm4_16_p1 16:4 !function=3Dplus1 %imm6_22_5 22:1 5:5 %imm9_16_10 16:s6 10:3 =20 @@ -38,6 +38,9 @@ %tszimm16_shr 22:2 16:5 !function=3Dtszimm_shr %tszimm16_shl 22:2 16:5 !function=3Dtszimm_shl =20 +# Signed 8-bit immediate, optionally shifted left by 8. +%sh8_i8s 5:9 !function=3Dexpand_imm_sh8s + # Either a copy of rd (at bit 0), or a different source # as propagated via the MOVPRFX instruction. %reg_movprfx 0:5 @@ -112,6 +115,11 @@ @rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \ &rri_esz esz=3D%tszimm16_esz =20 +# Two register operand, one immediate operand, with 4-bit predicate. +# User must fill in imm. +@rdn_pg4 ........ esz:2 .. pg:4 ... ........ rd:5 \ + &rpri_esz rn=3D%reg_movprfx + # Two register operand, one encoded bitmask. @rdn_dbm ........ .. .... dbm:13 rd:5 \ &rr_dbm rn=3D%reg_movprfx @@ -345,6 +353,15 @@ AND_zzi 00000101 10 0000 ............. ..... = @rdn_dbm # SVE broadcast bitmask immediate DUPM 00000101 11 0000 dbm:13 rd:5 =20 +### SVE Integer Wide Immediate - Predicated Group + +# SVE copy floating-point immediate (predicated) +FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4 + +# SVE copy integer immediate (predicated) +CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=3D%= sh8_i8s +CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=3D%= sh8_i8s + ### SVE Predicate Logical Operations Group =20 # SVE predicate logical operations --=20 2.17.0 From nobody Wed Oct 29 22:55:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526510807304490.77575334590927; Wed, 16 May 2018 15:46:47 -0700 (PDT) Received: from localhost ([::1]:44867 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ5C2-0003P2-H3 for importer@patchew.org; Wed, 16 May 2018 18:46:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41542) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4wc-00082h-EE for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ4wZ-0007n1-6c for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:50 -0400 Received: from mail-pl0-x22a.google.com ([2607:f8b0:400e:c01::22a]:36190) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ4wY-0007lz-VY for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:47 -0400 Received: by mail-pl0-x22a.google.com with SMTP id v24-v6so1253272plo.3 for ; Wed, 16 May 2018 15:30:46 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Nu2Z04m2JIvLCArqaHpvuvbfzz8tyPfHosNGNEIZ27E=; b=Eb6v8PTuuyfMWq8qrk7qtF+MRpaJzr6pK810mGvmWBe2bZtjKVypKFbI4O+iPQRDpm msvHnKVXLWWbxI+aXB0dgyFvd8Zq1HdvnIFal2cJxWWRcNXHVvld6CgexPwzo25m3fpN 7RyU9j4pEepldzaPRBHbYe0Px6J437i7f6TJo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Nu2Z04m2JIvLCArqaHpvuvbfzz8tyPfHosNGNEIZ27E=; b=rd7mG4Vc2aaIlJO+xQTLVlpY8SoUcZh2QAjNDMb32ZGblMktp4nhCmTmrSZ8uCab+S B+wumwS9NtgbDm6SFteA3igdjQNs3m0ZQ6ybHdMsvncjMksJZCpfJzhW3APgxBXpWhMU juxSr+9MPnQEToptDJBCj8GgCXJjmZ/ij3EyrhJkoXCYmxGS+HgWD6QdApVuK4jsaazt Y3VW31wH4OtAqANaZJ+/K7LEQ3kKHmsjGXk7X4ciT0ztr8cUo1751KPZajuoo2RFe5VC dAj8lZhGn5dY4CWQKwPhYeBYhMJHspXTNzazsmcwzGaWfclcy3DbLI5guv3kGNMDhUTV bl2A== X-Gm-Message-State: ALKqPwcrI8pjjNEaQd+ViwskFw6HacNAlmjtp8lDgHeXdmw2A13gP4Fj H41qGiRV68VWU3ndEGuAEiVmVcaaA9Q= X-Google-Smtp-Source: AB8JxZqSdRO29wCo7n6qfhqFGpoDZ0BzI4EuZFRzAi9SMmfXu5uuAC5YBt3KQ+bTglvn8zocz995Lg== X-Received: by 2002:a17:902:8f93:: with SMTP id z19-v6mr2677646plo.166.1526509845614; Wed, 16 May 2018 15:30:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:30:05 -0700 Message-Id: <20180516223007.10256-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::22a Subject: [Qemu-devel] [PATCH v3-a 25/27] target/arm: Implement SVE Permute - Extract Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 2 + target/arm/sve_helper.c | 81 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 34 ++++++++++++++++ target/arm/sve.decode | 7 ++++ 4 files changed, 124 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 79493ab647..94f4356ce9 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -414,6 +414,8 @@ DEF_HELPER_FLAGS_4(sve_cpy_z_h, TCG_CALL_NO_RWG, void, = ptr, ptr, i64, i32) DEF_HELPER_FLAGS_4(sve_cpy_z_s, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) DEF_HELPER_FLAGS_4(sve_cpy_z_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) =20 +DEF_HELPER_FLAGS_4(sve_ext, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 8c7ea989b1..b825e44cb5 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -1479,3 +1479,84 @@ void HELPER(sve_cpy_z_d)(void *vd, void *vg, uint64_= t val, uint32_t desc) d[i] =3D (pg[H1(i)] & 1 ? val : 0); } } + +/* Big-endian hosts need to frob the byte indicies. If the copy + * happens to be 8-byte aligned, then no frobbing necessary. + */ +static void swap_memmove(void *vd, void *vs, size_t n) +{ + uintptr_t d =3D (uintptr_t)vd; + uintptr_t s =3D (uintptr_t)vs; + uintptr_t o =3D (d | s | n) & 7; + size_t i; + +#ifndef HOST_WORDS_BIGENDIAN + o =3D 0; +#endif + switch (o) { + case 0: + memmove(vd, vs, n); + break; + + case 4: + if (d < s || d >=3D s + n) { + for (i =3D 0; i < n; i +=3D 4) { + *(uint32_t *)H1_4(d + i) =3D *(uint32_t *)H1_4(s + i); + } + } else { + for (i =3D n; i > 0; ) { + i -=3D 4; + *(uint32_t *)H1_4(d + i) =3D *(uint32_t *)H1_4(s + i); + } + } + break; + + case 2: + case 6: + if (d < s || d >=3D s + n) { + for (i =3D 0; i < n; i +=3D 2) { + *(uint16_t *)H1_2(d + i) =3D *(uint16_t *)H1_2(s + i); + } + } else { + for (i =3D n; i > 0; ) { + i -=3D 2; + *(uint16_t *)H1_2(d + i) =3D *(uint16_t *)H1_2(s + i); + } + } + break; + + default: + if (d < s || d >=3D s + n) { + for (i =3D 0; i < n; i++) { + *(uint8_t *)H1(d + i) =3D *(uint8_t *)H1(s + i); + } + } else { + for (i =3D n; i > 0; ) { + i -=3D 1; + *(uint8_t *)H1(d + i) =3D *(uint8_t *)H1(s + i); + } + } + break; + } +} + +void HELPER(sve_ext)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t opr_sz =3D simd_oprsz(desc); + size_t n_ofs =3D simd_data(desc); + size_t n_siz =3D opr_sz - n_ofs; + + if (vd !=3D vm) { + swap_memmove(vd, vn + n_ofs, n_siz); + swap_memmove(vd + n_siz, vm, n_ofs); + } else if (vd !=3D vn) { + swap_memmove(vd + n_siz, vd, n_ofs); + swap_memmove(vd, vn + n_ofs, n_siz); + } else { + /* vd =3D=3D vn =3D=3D vm. Need temp space. */ + ARMVectorReg tmp; + swap_memmove(&tmp, vm, n_ofs); + swap_memmove(vd, vd + n_ofs, n_siz); + memcpy(vd + n_siz, &tmp, n_ofs); + } +} diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 9bdd61ff84..c48d4b530a 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -1922,6 +1922,40 @@ static bool trans_CPY_z_i(DisasContext *s, arg_CPY_z= _i *a, uint32_t insn) return true; } =20 +/* + *** SVE Permute Extract Group + */ + +static bool trans_EXT(DisasContext *s, arg_EXT *a, uint32_t insn) +{ + if (!sve_access_check(s)) { + return true; + } + + unsigned vsz =3D vec_full_reg_size(s); + unsigned n_ofs =3D a->imm >=3D vsz ? 0 : a->imm; + unsigned n_siz =3D vsz - n_ofs; + unsigned d =3D vec_full_reg_offset(s, a->rd); + unsigned n =3D vec_full_reg_offset(s, a->rn); + unsigned m =3D vec_full_reg_offset(s, a->rm); + + /* Use host vector move insns if we have appropriate sizes + * and no unfortunate overlap. + */ + if (m !=3D d + && n_ofs =3D=3D size_for_gvec(n_ofs) + && n_siz =3D=3D size_for_gvec(n_siz) + && (d !=3D n || n_siz <=3D n_ofs)) { + tcg_gen_gvec_mov(0, d, n + n_ofs, n_siz, n_siz); + if (n_ofs !=3D 0) { + tcg_gen_gvec_mov(0, d + n_siz, m, n_ofs, n_ofs); + } + } else { + tcg_gen_gvec_3_ool(d, n, m, vsz, vsz, n_ofs, gen_helper_sve_ext); + } + return true; +} + /* *** SVE Memory - 32-bit Gather and Unsized Contiguous Group */ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 4ee7c78cda..4761d1921e 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -24,6 +24,7 @@ =20 %imm4_16_p1 16:4 !function=3Dplus1 %imm6_22_5 22:1 5:5 +%imm8_16_10 16:5 10:3 %imm9_16_10 16:s6 10:3 =20 # A combination of tsz:imm3 -- extract esize. @@ -362,6 +363,12 @@ FCPY 00000101 .. 01 .... 110 imm:8 ..... = @rdn_pg4 CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=3D%= sh8_i8s CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=3D%= sh8_i8s =20 +### SVE Permute - Extract Group + +# SVE extract vector (immediate offset) +EXT 00000101 001 ..... 000 ... rm:5 rd:5 \ + &rrri rn=3D%reg_movprfx imm=3D%imm8_16_10 + ### SVE Predicate Logical Operations Group =20 # SVE predicate logical operations --=20 2.17.0 From nobody Wed Oct 29 22:55:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526511518015475.77232421603276; Wed, 16 May 2018 15:58:38 -0700 (PDT) Received: from localhost ([::1]:45925 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ5NV-00056E-Bg for importer@patchew.org; Wed, 16 May 2018 18:58:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41543) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4wc-00082n-FJ for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ4wa-0007nw-DB for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:50 -0400 Received: from mail-pl0-x22b.google.com ([2607:f8b0:400e:c01::22b]:36191) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ4wa-0007na-7G for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:48 -0400 Received: by mail-pl0-x22b.google.com with SMTP id v24-v6so1253312plo.3 for ; Wed, 16 May 2018 15:30:48 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dg1WBnCOa5f1mNYqPGqrKxWSClxIHHeHmUJedBN44r0=; b=CZIvaRbguCkXUfaByVoEcmgsOJzzWsWv8dGNlEZ6bu/jbtICxcr6ywcwIGkHjvYGIr PCaj2hi8sGpTotOEMqMFa6A55cGIY1wY0rqcehLirfJdPm8llfJKJWwh7X43pXYdMwLP 2iAIPTQO2QPOypKMXLg0sVw1dsyCNweLV685s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dg1WBnCOa5f1mNYqPGqrKxWSClxIHHeHmUJedBN44r0=; b=XE8IZBcaba38PciNzwW3ixR10MnGgGKPCaTVKKp2T49dRa47FyqMI0giNrfa0d5Enq OiQ3T5lmRl8tKf51Axo0c/7drPTbJtb5DpaLOqsV/NFvZabdJIq3iJQFH/MiO0nVklfF sUBQxRSkiSLl8AYJxPWgyYmGVPxpuSqkhuxFn5qUi4OPTwHqyGpanxxDTfOuht2iCcRY 8Q27qCRbwZYRPYpxE/6ykbI8xAvx1jrOww8caHNj7sQJT7VYzyl9CXSbY94aZMKGXmTF HCTZ/VU7rF8fgxG7JdXHa1y7cYzDr5nv5Tok7Gr/iwKHC3MqxS/dzloagBUP0RhCEuff qQRg== X-Gm-Message-State: ALKqPwcEOi7jhXX0gZfBH8hmkrvTL2t8Y/BNakS2U8noaq1tR0kYcjv1 4jIZ0nfCHLqQfy922fuQgJCKKNM05SI= X-Google-Smtp-Source: AB8JxZowraG2b05PUc2J+JVBx55V0oG1XMRpVNeEXzEcU2ZxkcqVdm1oH7TZ1uifUEQWXUPjWVQQNA== X-Received: by 2002:a17:902:c5:: with SMTP id a63-v6mr2702580pla.149.1526509846994; Wed, 16 May 2018 15:30:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:30:06 -0700 Message-Id: <20180516223007.10256-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::22b Subject: [Qemu-devel] [PATCH v3-a 26/27] target/arm: Extend vec_reg_offset to larger sizes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Rearrange the arithmetic so that we are agnostic about the total size of the vector and the size of the element. This will allow us to index up to the 32nd byte and with 16-byte elements. Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index dd9c09f89b..5a97ae2b59 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -67,18 +67,18 @@ static inline void assert_fp_access_checked(DisasContex= t *s) static inline int vec_reg_offset(DisasContext *s, int regno, int element, TCGMemOp size) { - int offs =3D 0; + int element_size =3D 1 << size; + int offs =3D element * element_size; #ifdef HOST_WORDS_BIGENDIAN /* This is complicated slightly because vfp.zregs[n].d[0] is * still the low half and vfp.zregs[n].d[1] the high half * of the 128 bit vector, even on big endian systems. - * Calculate the offset assuming a fully bigendian 128 bits, - * then XOR to account for the order of the two 64 bit halves. + * Calculate the offset assuming a fully little-endian 128 bits, + * then XOR to account for the order of the 64 bit units. */ - offs +=3D (16 - ((element + 1) * (1 << size))); - offs ^=3D 8; -#else - offs +=3D element * (1 << size); + if (element_size < 8) { + offs ^=3D 8 - element_size; + } #endif offs +=3D offsetof(CPUARMState, vfp.zregs[regno]); assert_fp_access_checked(s); --=20 2.17.0 From nobody Wed Oct 29 22:55:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152651104161285.80806964331657; Wed, 16 May 2018 15:50:41 -0700 (PDT) Received: from localhost ([::1]:45128 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ5Fk-0006lq-4h for importer@patchew.org; Wed, 16 May 2018 18:50:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41576) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ4wd-00084C-Nf for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ4wb-0007qY-RF for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:51 -0400 Received: from mail-pl0-x230.google.com ([2607:f8b0:400e:c01::230]:34356) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ4wb-0007pG-IT for qemu-devel@nongnu.org; Wed, 16 May 2018 18:30:49 -0400 Received: by mail-pl0-x230.google.com with SMTP id ay10-v6so1254853plb.1 for ; Wed, 16 May 2018 15:30:49 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8/cK1CKnbZW3yoUTbzCwG4b0r7T0TlVA6vycAYRYfkI=; b=M5rkjGvmRzsePvk3xbpHfPqaCff3u2TAfrsaIIN3j4KzosQzoCEpNx6jHYwQ3q+PTv DtE1PThCiJmQjfhhSuFazgMzBRSYp+8s/dDK6owoIB6pcLnVhWHXiJBarQiL7k6DtpYk G2FoNSekuJm5hT1R5pGwEto5bpydRXgq+1MXA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8/cK1CKnbZW3yoUTbzCwG4b0r7T0TlVA6vycAYRYfkI=; b=BBAXyVS368LuUVC9Tmn1VuFN36WR2masDQ29Q4hBb0QON25fZ4BeJqwz3xavb02P4D yAoFgGWD9f7M4FuHA4SAGL7lHH/y10emsWFLE8mumSUfCv/9dYTxfwx6M69VJHdjMWbZ XYGn4E3Qcid3fE8DQ/2kxO4WGHRqk8mN+I3jhfZzlH2Qj21xQa473pJr4HMWMF1BjGoT +bg4r5f2758NVwCexAipxVhPwm6x0T4vusXmXKpB5qyQ7EWTnEVZYKuwqlqwfb4k8sZf 7Bec41RqtNglozpGB0GodjbMCSk/kGK8cqF1LewkrUUhltbpQhy7PLwOHGCCvU6K0OHg +vJw== X-Gm-Message-State: ALKqPwf/0ZlRSmrP+j3i1n1HIsNyA0Pq5j92j3eU1yVK9ahhF9RVa7An MTG2pdtAOhgQtnCgAbnjKtzF2HPssro= X-Google-Smtp-Source: AB8JxZo0Byj5s1Cj3lze9LM3rBAkgUpHZ2IdMJp8E+twPkc//bEcf5Xeovzd45xZiQD2SeqQRFMOXg== X-Received: by 2002:a17:902:710f:: with SMTP id a15-v6mr2759432pll.171.1526509848236; Wed, 16 May 2018 15:30:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:30:07 -0700 Message-Id: <20180516223007.10256-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516223007.10256-1-richard.henderson@linaro.org> References: <20180516223007.10256-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::230 Subject: [Qemu-devel] [PATCH v3-a 27/27] target/arm: Implement SVE Permute - Unpredicated Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 23 +++++++ target/arm/sve_helper.c | 114 +++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 133 +++++++++++++++++++++++++++++++++++++ target/arm/sve.decode | 27 ++++++++ 4 files changed, 297 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 94f4356ce9..0c9aad575e 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -416,6 +416,29 @@ DEF_HELPER_FLAGS_4(sve_cpy_z_d, TCG_CALL_NO_RWG, void,= ptr, ptr, i64, i32) =20 DEF_HELPER_FLAGS_4(sve_ext, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_4(sve_insr_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(sve_insr_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(sve_insr_s, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(sve_insr_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) + +DEF_HELPER_FLAGS_3(sve_rev_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_rev_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_rev_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_rev_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve_tbl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_tbl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_tbl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_tbl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(sve_sunpk_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_sunpk_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_sunpk_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(sve_uunpk_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_uunpk_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_uunpk_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index b825e44cb5..58c0fda333 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -1560,3 +1560,117 @@ void HELPER(sve_ext)(void *vd, void *vn, void *vm, = uint32_t desc) memcpy(vd + n_siz, &tmp, n_ofs); } } + +#define DO_INSR(NAME, TYPE, H) \ +void HELPER(NAME)(void *vd, void *vn, uint64_t val, uint32_t desc) \ +{ \ + intptr_t opr_sz =3D simd_oprsz(desc); \ + swap_memmove(vd + sizeof(TYPE), vn, opr_sz - sizeof(TYPE)); \ + *(TYPE *)(vd + H(0)) =3D val; \ +} + +DO_INSR(sve_insr_b, uint8_t, H1) +DO_INSR(sve_insr_h, uint16_t, H1_2) +DO_INSR(sve_insr_s, uint32_t, H1_4) +DO_INSR(sve_insr_d, uint64_t, ) + +#undef DO_INSR + +void HELPER(sve_rev_b)(void *vd, void *vn, uint32_t desc) +{ + intptr_t i, j, opr_sz =3D simd_oprsz(desc); + for (i =3D 0, j =3D opr_sz - 8; i < opr_sz / 2; i +=3D 8, j -=3D 8) { + uint64_t f =3D *(uint64_t *)(vn + i); + uint64_t b =3D *(uint64_t *)(vn + j); + *(uint64_t *)(vd + i) =3D bswap64(b); + *(uint64_t *)(vd + j) =3D bswap64(f); + } +} + +static inline uint64_t hswap64(uint64_t h) +{ + uint64_t m =3D 0x0000ffff0000ffffull; + h =3D rol64(h, 32); + return ((h & m) << 16) | ((h >> 16) & m); +} + +void HELPER(sve_rev_h)(void *vd, void *vn, uint32_t desc) +{ + intptr_t i, j, opr_sz =3D simd_oprsz(desc); + for (i =3D 0, j =3D opr_sz - 8; i < opr_sz / 2; i +=3D 8, j -=3D 8) { + uint64_t f =3D *(uint64_t *)(vn + i); + uint64_t b =3D *(uint64_t *)(vn + j); + *(uint64_t *)(vd + i) =3D hswap64(b); + *(uint64_t *)(vd + j) =3D hswap64(f); + } +} + +void HELPER(sve_rev_s)(void *vd, void *vn, uint32_t desc) +{ + intptr_t i, j, opr_sz =3D simd_oprsz(desc); + for (i =3D 0, j =3D opr_sz - 8; i < opr_sz / 2; i +=3D 8, j -=3D 8) { + uint64_t f =3D *(uint64_t *)(vn + i); + uint64_t b =3D *(uint64_t *)(vn + j); + *(uint64_t *)(vd + i) =3D rol64(b, 32); + *(uint64_t *)(vd + j) =3D rol64(f, 32); + } +} + +void HELPER(sve_rev_d)(void *vd, void *vn, uint32_t desc) +{ + intptr_t i, j, opr_sz =3D simd_oprsz(desc); + for (i =3D 0, j =3D opr_sz - 8; i < opr_sz / 2; i +=3D 8, j -=3D 8) { + uint64_t f =3D *(uint64_t *)(vn + i); + uint64_t b =3D *(uint64_t *)(vn + j); + *(uint64_t *)(vd + i) =3D b; + *(uint64_t *)(vd + j) =3D f; + } +} + +#define DO_TBL(NAME, TYPE, H) \ +void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \ +{ \ + intptr_t i, opr_sz =3D simd_oprsz(desc); \ + uintptr_t elem =3D opr_sz / sizeof(TYPE); \ + TYPE *d =3D vd, *n =3D vn, *m =3D vm; \ + ARMVectorReg tmp; \ + if (unlikely(vd =3D=3D vn)) { \ + n =3D memcpy(&tmp, vn, opr_sz); \ + } \ + for (i =3D 0; i < elem; i++) { \ + TYPE j =3D m[H(i)]; \ + d[H(i)] =3D j < elem ? n[H(j)] : 0; \ + } \ +} + +DO_TBL(sve_tbl_b, uint8_t, H1) +DO_TBL(sve_tbl_h, uint16_t, H2) +DO_TBL(sve_tbl_s, uint32_t, H4) +DO_TBL(sve_tbl_d, uint64_t, ) + +#undef TBL + +#define DO_UNPK(NAME, TYPED, TYPES, HD, HS) \ +void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \ +{ \ + intptr_t i, opr_sz =3D simd_oprsz(desc); \ + TYPED *d =3D vd; \ + TYPES *n =3D vn; \ + ARMVectorReg tmp; \ + if (unlikely(vn - vd < opr_sz)) { \ + n =3D memcpy(&tmp, n, opr_sz / 2); \ + } \ + for (i =3D 0; i < opr_sz / sizeof(TYPED); i++) { \ + d[HD(i)] =3D n[HS(i)]; \ + } \ +} + +DO_UNPK(sve_sunpk_h, int16_t, int8_t, H2, H1) +DO_UNPK(sve_sunpk_s, int32_t, int16_t, H4, H2) +DO_UNPK(sve_sunpk_d, int64_t, int32_t, , H4) + +DO_UNPK(sve_uunpk_h, uint16_t, uint8_t, H2, H1) +DO_UNPK(sve_uunpk_s, uint32_t, uint16_t, H4, H2) +DO_UNPK(sve_uunpk_d, uint64_t, uint32_t, , H4) + +#undef DO_UNPK diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index c48d4b530a..388cce9924 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -1956,6 +1956,139 @@ static bool trans_EXT(DisasContext *s, arg_EXT *a, = uint32_t insn) return true; } =20 +/* + *** SVE Permute - Unpredicated Group + */ + +static bool trans_DUP_s(DisasContext *s, arg_DUP_s *a, uint32_t insn) +{ + if (sve_access_check(s)) { + unsigned vsz =3D vec_full_reg_size(s); + tcg_gen_gvec_dup_i64(a->esz, vec_full_reg_offset(s, a->rd), + vsz, vsz, cpu_reg_sp(s, a->rn)); + } + return true; +} + +static bool trans_DUP_x(DisasContext *s, arg_DUP_x *a, uint32_t insn) +{ + if ((a->imm & 0x1f) =3D=3D 0) { + return false; + } + if (sve_access_check(s)) { + unsigned vsz =3D vec_full_reg_size(s); + unsigned dofs =3D vec_full_reg_offset(s, a->rd); + unsigned esz, index; + + esz =3D ctz32(a->imm); + index =3D a->imm >> (esz + 1); + + if ((index << esz) < vsz) { + unsigned nofs =3D vec_reg_offset(s, a->rn, index, esz); + tcg_gen_gvec_dup_mem(esz, dofs, nofs, vsz, vsz); + } else { + tcg_gen_gvec_dup64i(dofs, vsz, vsz, 0); + } + } + return true; +} + +static void do_insr_i64(DisasContext *s, arg_rrr_esz *a, TCGv_i64 val) +{ + typedef void gen_insr(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_i32); + static gen_insr * const fns[4] =3D { + gen_helper_sve_insr_b, gen_helper_sve_insr_h, + gen_helper_sve_insr_s, gen_helper_sve_insr_d, + }; + unsigned vsz =3D vec_full_reg_size(s); + TCGv_i32 desc =3D tcg_const_i32(simd_desc(vsz, vsz, 0)); + TCGv_ptr t_zd =3D tcg_temp_new_ptr(); + TCGv_ptr t_zn =3D tcg_temp_new_ptr(); + + tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, a->rd)); + tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn)); + + fns[a->esz](t_zd, t_zn, val, desc); + + tcg_temp_free_ptr(t_zd); + tcg_temp_free_ptr(t_zn); + tcg_temp_free_i32(desc); +} + +static bool trans_INSR_f(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + if (sve_access_check(s)) { + TCGv_i64 t =3D tcg_temp_new_i64(); + tcg_gen_ld_i64(t, cpu_env, vec_reg_offset(s, a->rm, 0, MO_64)); + do_insr_i64(s, a, t); + tcg_temp_free_i64(t); + } + return true; +} + +static bool trans_INSR_r(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + if (sve_access_check(s)) { + do_insr_i64(s, a, cpu_reg(s, a->rm)); + } + return true; +} + +static bool trans_REV_v(DisasContext *s, arg_rr_esz *a, uint32_t insn) +{ + static gen_helper_gvec_2 * const fns[4] =3D { + gen_helper_sve_rev_b, gen_helper_sve_rev_h, + gen_helper_sve_rev_s, gen_helper_sve_rev_d + }; + + if (sve_access_check(s)) { + unsigned vsz =3D vec_full_reg_size(s); + tcg_gen_gvec_2_ool(vec_full_reg_offset(s, a->rd), + vec_full_reg_offset(s, a->rn), + vsz, vsz, 0, fns[a->esz]); + } + return true; +} + +static bool trans_TBL(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + static gen_helper_gvec_3 * const fns[4] =3D { + gen_helper_sve_tbl_b, gen_helper_sve_tbl_h, + gen_helper_sve_tbl_s, gen_helper_sve_tbl_d + }; + + if (sve_access_check(s)) { + unsigned vsz =3D vec_full_reg_size(s); + tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd), + vec_full_reg_offset(s, a->rn), + vec_full_reg_offset(s, a->rm), + vsz, vsz, 0, fns[a->esz]); + } + return true; +} + +static bool trans_UNPK(DisasContext *s, arg_UNPK *a, uint32_t insn) +{ + static gen_helper_gvec_2 * const fns[4][2] =3D { + { NULL, NULL }, + { gen_helper_sve_sunpk_h, gen_helper_sve_uunpk_h }, + { gen_helper_sve_sunpk_s, gen_helper_sve_uunpk_s }, + { gen_helper_sve_sunpk_d, gen_helper_sve_uunpk_d }, + }; + + if (a->esz =3D=3D 0) { + return false; + } + if (sve_access_check(s)) { + unsigned vsz =3D vec_full_reg_size(s); + tcg_gen_gvec_2_ool(vec_full_reg_offset(s, a->rd), + vec_full_reg_offset(s, a->rn) + + (a->h ? vsz / 2 : 0), + vsz, vsz, 0, fns[a->esz][a->u]); + } + return true; +} + /* *** SVE Memory - 32-bit Gather and Unsized Contiguous Group */ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 4761d1921e..7ffd7962c8 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -24,6 +24,7 @@ =20 %imm4_16_p1 16:4 !function=3Dplus1 %imm6_22_5 22:1 5:5 +%imm7_22_16 22:2 16:5 %imm8_16_10 16:5 10:3 %imm9_16_10 16:s6 10:3 =20 @@ -85,6 +86,8 @@ =20 # Three operand, vector element size @rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz +@rdn_rm ........ esz:2 ...... ...... rm:5 rd:5 \ + &rrr_esz rn=3D%reg_movprfx =20 # Three operand with "memory" size, aka immediate left shift @rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri @@ -369,6 +372,30 @@ CPY_z_i 00000101 .. 01 .... 00 . ........ ....= . @rdn_pg4 imm=3D%sh8_i8s EXT 00000101 001 ..... 000 ... rm:5 rd:5 \ &rrri rn=3D%reg_movprfx imm=3D%imm8_16_10 =20 +### SVE Permute - Unpredicated Group + +# SVE broadcast general register +DUP_s 00000101 .. 1 00000 001110 ..... ..... @rd_rn + +# SVE broadcast indexed element +DUP_x 00000101 .. 1 ..... 001000 rn:5 rd:5 \ + &rri imm=3D%imm7_22_16 + +# SVE insert SIMD&FP scalar register +INSR_f 00000101 .. 1 10100 001110 ..... ..... @rdn_rm + +# SVE insert general register +INSR_r 00000101 .. 1 00100 001110 ..... ..... @rdn_rm + +# SVE reverse vector elements +REV_v 00000101 .. 1 11000 001110 ..... ..... @rd_rn + +# SVE vector table lookup +TBL 00000101 .. 1 ..... 001100 ..... ..... @rd_rn_rm + +# SVE unpack vector elements +UNPK 00000101 esz:2 1100 u:1 h:1 001110 rn:5 rd:5 + ### SVE Predicate Logical Operations Group =20 # SVE predicate logical operations --=20 2.17.0