From nobody Sat Nov 1 07:48:31 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15264973921781013.4479718354362; Wed, 16 May 2018 12:03:12 -0700 (PDT) Received: from localhost ([::1]:34233 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ1hf-0003OA-AU for importer@patchew.org; Wed, 16 May 2018 15:03:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53674) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fJ1X5-0003BD-N4 for qemu-devel@nongnu.org; Wed, 16 May 2018 14:52:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fJ1X4-0000m4-GR for qemu-devel@nongnu.org; Wed, 16 May 2018 14:52:15 -0400 Received: from mail-wr0-x242.google.com ([2a00:1450:400c:c0c::242]:40832) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fJ1X4-0000lp-6v for qemu-devel@nongnu.org; Wed, 16 May 2018 14:52:14 -0400 Received: by mail-wr0-x242.google.com with SMTP id v60-v6so2764386wrc.7 for ; Wed, 16 May 2018 11:52:14 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id e18-v6sm523932ljk.57.2018.05.16.11.52.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 11:52:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iRC/FDHhvlq4gwj0oZNPD+PlwUqTwlPKLzatOjkoW9g=; b=FVSXmGg+eEh0lXnDn8o06mloGVGvnOgoORwKUtZXToGva96SHl1C2LDqEsSKiMdyE6 PeEKZO1iLxFdP+agbQ3k/Wo2WyBsYOX2+HoaHVmJKsMXiFsjv3Z0a0Myk+uEmYZNibye d7vz2Xrz6bQiyuZGx5wrauURaqI/rYfzVco7UTvUH7F9tY22Hv3y0Y0T97mNrsMoV0AE x5AMkt6bFSTe+iM0Ko8PaQvvn80f44PIrBY8Qdwb3Y+BBG/yLQCjTE/wuWTP3gcrxui3 Secp1QpYecePx//2/ZMt1LY3Z/FOERL47l2q1JTPxefwuD6vnFJ3FOqtv12A9MclDXeh +t4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iRC/FDHhvlq4gwj0oZNPD+PlwUqTwlPKLzatOjkoW9g=; b=LGS8bQ6zkzP3tbW+zFsDY0Unx1Nm1bBWQ4iqu9VBCS5JETyDyrlnhMH69gCorcD0o8 8IRnXLwctIQfAOQ0FANVEc56ikvDRYCPGkwRZJjaEgsDew/DTnpjsXT31jYylb4MANkE Bjg2DvrDvaF2Kg6VG5sJCmb/UCZ/64O9kfwrJDYLILfyojyUcnKYA9tDKhNFGbqfI0ha /iHc0Oh3aMQjuniqxsVmp0AQiQoM3XwWe3gGxC92z26pQfaGIj+b5eUqkG4EFEv93whh +1bQm3DaU/FaSMsbZ2Uy0gb4mv+3p1tZmWXG4noh1s5HxpB4fanxKK95iOB7lvxDqI8A fWnA== X-Gm-Message-State: ALKqPwcGXYvV7ZKNgVjFbVWR7wOwrXtdI6JdhPQTya6hs4BMMPuQhIcR tOu/T+nOmn0H0AX7OGvmkplhQA== X-Google-Smtp-Source: AB8JxZo2JAbXicWDP0+rAqGs/fGKk2oud7ORKKrRm0eqDrng5UBHcbNF0zDLFxKG1lQ9YmmUq0hgeQ== X-Received: by 2002:a19:2a08:: with SMTP id f8-v6mr15509818lfl.141.1526496732660; Wed, 16 May 2018 11:52:12 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 20:51:23 +0200 Message-Id: <20180516185146.30708-16-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180516185146.30708-1-edgar.iglesias@gmail.com> References: <20180516185146.30708-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [PATCH v3 15/38] target-microblaze: Break out trap_userspace() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, sstabellini@kernel.org, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, frederic.konrad@adacore.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Break out trap_userspace() to avoid open coding it everywhere. For privileged insns, we now always stop translation of the current insn for cores without exceptions. Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/microblaze/translate.c | 76 +++++++++++++++------------------------= ---- 1 file changed, 27 insertions(+), 49 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 12cb345f64..8f72cf39fb 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -179,6 +179,22 @@ static void write_carryi(DisasContext *dc, bool carry) tcg_temp_free_i32(t0); } =20 +/* + * Returns true if the insn is illegal in userspace. + * If exceptions are enabled, an exception is raised. + */ +static bool trap_userspace(DisasContext *dc, bool cond) +{ + int mem_index =3D cpu_mmu_index(&dc->cpu->env, false); + bool cond_user =3D cond && mem_index =3D=3D MMU_USER_IDX; + + if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) { + tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); + t_gen_raise_exception(dc, EXCP_HW_EXCP); + } + return cond_user; +} + /* True if ALU operand b is a small immediate that may deserve faster treatment. */ static inline int dec_alu_op_b_is_small_imm(DisasContext *dc) @@ -432,7 +448,6 @@ static void dec_msr(DisasContext *dc) CPUState *cs =3D CPU(dc->cpu); TCGv_i32 t0, t1; unsigned int sr, to, rn; - int mem_index =3D cpu_mmu_index(&dc->cpu->env, false); =20 sr =3D dc->imm & ((1 << 14) - 1); to =3D dc->imm & (1 << 14); @@ -452,10 +467,7 @@ static void dec_msr(DisasContext *dc) return; } =20 - if ((dc->tb_flags & MSR_EE_FLAG) - && mem_index =3D=3D MMU_USER_IDX && (dc->imm !=3D 4 && dc->imm= !=3D 0)) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + if (trap_userspace(dc, dc->imm !=3D 4 && dc->imm !=3D 0)) { return; } =20 @@ -480,13 +492,8 @@ static void dec_msr(DisasContext *dc) return; } =20 - if (to) { - if ((dc->tb_flags & MSR_EE_FLAG) - && mem_index =3D=3D MMU_USER_IDX) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); - return; - } + if (trap_userspace(dc, to)) { + return; } =20 #if !defined(CONFIG_USER_ONLY) @@ -738,7 +745,6 @@ static void dec_bit(DisasContext *dc) CPUState *cs =3D CPU(dc->cpu); TCGv_i32 t0; unsigned int op; - int mem_index =3D cpu_mmu_index(&dc->cpu->env, false); =20 op =3D dc->ir & ((1 << 9) - 1); switch (op) { @@ -784,22 +790,12 @@ static void dec_bit(DisasContext *dc) case 0x76: /* wdc. */ LOG_DIS("wdc r%d\n", dc->ra); - if ((dc->tb_flags & MSR_EE_FLAG) - && mem_index =3D=3D MMU_USER_IDX) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); - return; - } + trap_userspace(dc, true); break; case 0x68: /* wic. */ LOG_DIS("wic r%d\n", dc->ra); - if ((dc->tb_flags & MSR_EE_FLAG) - && mem_index =3D=3D MMU_USER_IDX) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); - return; - } + trap_userspace(dc, true); break; case 0xe0: if ((dc->tb_flags & MSR_EE_FLAG) @@ -1199,7 +1195,6 @@ static void dec_bcc(DisasContext *dc) static void dec_br(DisasContext *dc) { unsigned int dslot, link, abs, mbar; - int mem_index =3D cpu_mmu_index(&dc->cpu->env, false); =20 dslot =3D dc->ir & (1 << 20); abs =3D dc->ir & (1 << 19); @@ -1254,9 +1249,7 @@ static void dec_br(DisasContext *dc) if (!(dc->tb_flags & IMM_FLAG) && (dc->imm =3D=3D 8 || dc->imm= =3D=3D 0x18)) t_gen_raise_exception(dc, EXCP_BREAK); if (dc->imm =3D=3D 0) { - if ((dc->tb_flags & MSR_EE_FLAG) && mem_index =3D=3D MMU_U= SER_IDX) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + if (trap_userspace(dc, true)) { return; } =20 @@ -1331,12 +1324,15 @@ static inline void do_rte(DisasContext *dc) static void dec_rts(DisasContext *dc) { unsigned int b_bit, i_bit, e_bit; - int mem_index =3D cpu_mmu_index(&dc->cpu->env, false); =20 i_bit =3D dc->ir & (1 << 21); b_bit =3D dc->ir & (1 << 22); e_bit =3D dc->ir & (1 << 23); =20 + if (trap_userspace(dc, i_bit || b_bit || e_bit)) { + return; + } + dc->delayed_branch =3D 2; dc->tb_flags |=3D D_FLAG; tcg_gen_st_i32(tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG)), @@ -1344,27 +1340,12 @@ static void dec_rts(DisasContext *dc) =20 if (i_bit) { LOG_DIS("rtid ir=3D%x\n", dc->ir); - if ((dc->tb_flags & MSR_EE_FLAG) - && mem_index =3D=3D MMU_USER_IDX) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); - } dc->tb_flags |=3D DRTI_FLAG; } else if (b_bit) { LOG_DIS("rtbd ir=3D%x\n", dc->ir); - if ((dc->tb_flags & MSR_EE_FLAG) - && mem_index =3D=3D MMU_USER_IDX) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); - } dc->tb_flags |=3D DRTB_FLAG; } else if (e_bit) { LOG_DIS("rted ir=3D%x\n", dc->ir); - if ((dc->tb_flags & MSR_EE_FLAG) - && mem_index =3D=3D MMU_USER_IDX) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); - } dc->tb_flags |=3D DRTE_FLAG; } else LOG_DIS("rts ir=3D%x\n", dc->ir); @@ -1503,16 +1484,13 @@ static void dec_null(DisasContext *dc) /* Insns connected to FSL or AXI stream attached devices. */ static void dec_stream(DisasContext *dc) { - int mem_index =3D cpu_mmu_index(&dc->cpu->env, false); TCGv_i32 t_id, t_ctrl; int ctrl; =20 LOG_DIS("%s%s imm=3D%x\n", dc->rd ? "get" : "put", dc->type_b ? "" : "d", dc->imm); =20 - if ((dc->tb_flags & MSR_EE_FLAG) && (mem_index =3D=3D MMU_USER_IDX)) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + if (trap_userspace(dc, true)) { return; } =20 --=20 2.14.1