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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id g11-v6sm941419pgq.62.2018.05.15.15.25.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 15:25:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8WVCgIbaq/jdNQA6d+Wa1CN7e/ZoYkChVYLL1VI8a6s=; b=FvAH2FlJ24p7UqSez5AzYqmFezOP/NiGp+wyN09Wc5YqWK48C3SkajB0qZzetHG4il mRtQI3HlbzViwiCYnwRzU4wUdQLNhnLPePGzAx99XQTumwQihGxy7XgF1bY7VdnFLhP7 L4U0XGI25Qgj7cqswyjn7q+V0YM95RshxUU1A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8WVCgIbaq/jdNQA6d+Wa1CN7e/ZoYkChVYLL1VI8a6s=; b=m1YrxMjj0hDQQTT9kRv1Ak+1RZkcrOIPVq2zhnUB0YGw5SrHH2b82ZqjTaFdt5tyBe YutGC2wimthJRDUzX4zzLSh4tnE11lunVATeD+Bfe68QizmpLVK6Turxfg1P7mIz2zYI C7OERdslg3UQ88v1ENNh0fgPhc4BK3Wd+z3tf0LskvoolTgEz4dLntAfRw4KcnPHloqT b8pY6ssvaX2wZw2SfVzOwXPNSLJa5x2ZbsXXttuDZRK0LIGIAvMxeB3JT3XvIa2NbGsK E1T6nkuuAbVeKAeXyaANeKMowIabDi+olaL+Ce4A0GwFu+6WDLBh8+JJa4eu1frUCvGy /Ebg== X-Gm-Message-State: ALKqPwfjRnEBWh9yKOnCArS/H+Gw1wi/aeDjUbPPlB6IAyoS22wHVOBy cr5hHUgtFqkF0g5N7Nv780VGcK5A+OY= X-Google-Smtp-Source: AB8JxZpMw1Yt7P2nqSyTqpc0PpF/CfrOIFZfdziEH4xVz3et2XAADaFxhG1sHD0BBbynqd0QwOrdxA== X-Received: by 2002:a63:380e:: with SMTP id f14-v6mr6728854pga.242.1526423159515; Tue, 15 May 2018 15:25:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 15:25:23 -0700 Message-Id: <20180515222540.9988-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515222540.9988-1-richard.henderson@linaro.org> References: <20180515222540.9988-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v6 11/28] fpu/softfloat: Partial support for ARM Alternative half-precision X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Alex Benn=C3=A9e For float16 ARM supports an alternative half-precision format which sacrifices the ability to represent NaN/Inf in return for a higher dynamic range. The new FloatFmt flag, arm_althp, is then used to modify the behaviour of canonicalize and round_canonical with respect to representation and exception raising. Usage of this new flag waits until we re-factor float-to-float conversions. Reviewed-by: Peter Maydell Signed-off-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- v3 - squash NaN to 0 if destination is AHP F16 v4 - handle inf -> ahp max in float_to_float not round_canonical - assert no nan and inf for ahp in round_canonical - check ahp before snan in float_to_float v5 - split out canonicalize and round_canonical changes from the rest --- fpu/softfloat.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 41253c6749..64e1ad4f98 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -220,8 +220,10 @@ typedef struct { * frac_shift: shift to normalise the fraction with DECOMPOSED_BINARY_PO= INT * The following are computed based the size of fraction * frac_lsb: least significant bit of fraction - * fram_lsbm1: the bit bellow the least significant bit (for rounding) + * frac_lsbm1: the bit below the least significant bit (for rounding) * round_mask/roundeven_mask: masks used for rounding + * The following optional modifiers are available: + * arm_althp: handle ARM Alternative Half Precision */ typedef struct { int exp_size; @@ -233,6 +235,7 @@ typedef struct { uint64_t frac_lsbm1; uint64_t round_mask; uint64_t roundeven_mask; + bool arm_althp; } FloatFmt; =20 /* Expand fields based on the size of exponent and fraction */ @@ -324,7 +327,7 @@ static inline float64 float64_pack_raw(FloatParts p) static FloatParts canonicalize(FloatParts part, const FloatFmt *parm, float_status *status) { - if (part.exp =3D=3D parm->exp_max) { + if (part.exp =3D=3D parm->exp_max && !parm->arm_althp) { if (part.frac =3D=3D 0) { part.cls =3D float_class_inf; } else { @@ -413,7 +416,15 @@ static FloatParts round_canonical(FloatParts p, float_= status *s, } frac >>=3D frac_shift; =20 - if (unlikely(exp >=3D exp_max)) { + if (parm->arm_althp) { + /* ARM Alt HP eschews Inf and NaN for a wider exponent. */ + if (unlikely(exp > exp_max)) { + /* Overflow. Return the maximum normal. */ + flags =3D float_flag_invalid; + exp =3D exp_max; + frac =3D -1; + } + } else if (unlikely(exp >=3D exp_max)) { flags |=3D float_flag_overflow | float_flag_inexact; if (overflow_norm) { exp =3D exp_max - 1; @@ -464,12 +475,14 @@ static FloatParts round_canonical(FloatParts p, float= _status *s, =20 case float_class_inf: do_inf: + assert(!parm->arm_althp); exp =3D exp_max; frac =3D 0; break; =20 case float_class_qnan: case float_class_snan: + assert(!parm->arm_althp); exp =3D exp_max; frac >>=3D parm->frac_shift; break; --=20 2.17.0