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From: Peter Maydell <peter.maydell@linaro.org>
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Subject: [Qemu-devel] [PULL 13/16] target/arm: Implement FMOV (immediate)
for fp16
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From: Alex Benn=C3=A9e <alex.bennee@linaro.org>
All the hard work is already done by vfp_expand_imm, we just need to
make sure we pick up the correct size.
Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180512003217.9105-11-richard.henderson@linaro.org
[rth: Merge unallocated_encoding check with TCGMemOp conversion.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-a64.c | 20 +++++++++++++++++---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 9dacb583ae..35997969b4 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -5674,11 +5674,25 @@ static void disas_fp_imm(DisasContext *s, uint32_t =
insn)
{
int rd =3D extract32(insn, 0, 5);
int imm8 =3D extract32(insn, 13, 8);
- int is_double =3D extract32(insn, 22, 2);
+ int type =3D extract32(insn, 22, 2);
uint64_t imm;
TCGv_i64 tcg_res;
+ TCGMemOp sz;
=20
- if (is_double > 1) {
+ switch (type) {
+ case 0:
+ sz =3D MO_32;
+ break;
+ case 1:
+ sz =3D MO_64;
+ break;
+ case 3:
+ sz =3D MO_16;
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+ break;
+ }
+ /* fallthru */
+ default:
unallocated_encoding(s);
return;
}
@@ -5687,7 +5701,7 @@ static void disas_fp_imm(DisasContext *s, uint32_t in=
sn)
return;
}
=20
- imm =3D vfp_expand_imm(MO_32 + is_double, imm8);
+ imm =3D vfp_expand_imm(sz, imm8);
=20
tcg_res =3D tcg_const_i64(imm);
write_fp_dreg(s, rd, tcg_res);
--=20
2.17.0