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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id y2-v6sm14512457pgp.92.2018.05.14.15.12.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 May 2018 15:12:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/eGeUttM52eudQ5TkxSYzl7bDNiiGBDFDqUuWF7ZJu0=; b=PDrBgN8mttkQhEeVsJ8cF+pl9Uh1C85TtECdJP14WvAzINkIT5cG+JAWvaWvv+8m/8 /AYlMKpUNsl8CYQYJZHJiPC2pv0xzzEb+pZtn+cz3GrAcat9nfr8m+GFVMUvw6jAU0r6 DAdWh5QBKAfPUkfeW2rTm3cy2CVU6PZzyUoRg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/eGeUttM52eudQ5TkxSYzl7bDNiiGBDFDqUuWF7ZJu0=; b=Hmrh+UCOnbuesEYFOHbR6zWHubdn9yLjyyuNhJKOXmYPVTKfu273/o8PGf/D9qwjpy +vqq/OBmOBxj3Zr4Oe6SPpNAl5sgSL1GaXTOIeji9Um3RxbdoMFszzZ9zjody2/0EJSn GCeLS5LUdik8A7gAKpOiZPcvOZ8QPB9OTInJFoIt++oA51IvRD42ZIZ38Ho+HoqFNuMo 0E9Xr8t6FzZxcPmIwnZTzDHjdzY9XgJFv/4UNXEblaNMMlIIQIC9gUrNCCvNDg41GMBp HUg8yooxJnhCzrwc4BGG2tQyhff7DaljBn3LWDNhfvpC46aQxqwGWXYkyyDgLYwZAKsS ++8g== X-Gm-Message-State: ALKqPwf7QVd6WnakvDk4bzITeCeML0jkTuleYWzPytzVcjxDAaGjT1z/ 13VV4dgA3dvkbHi9Jwp2jwYA2d5KvsE= X-Google-Smtp-Source: AB8JxZqF7lnqtIPwOBuu1zi/K49EOGyKw02PlFWzHy4VUT3StgpIIr0bABvwQ0UZEH6FEBOMYTYd/A== X-Received: by 2002:a17:902:7288:: with SMTP id d8-v6mr11624458pll.218.1526335943603; Mon, 14 May 2018 15:12:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 May 2018 15:11:52 -0700 Message-Id: <20180514221219.7091-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180514221219.7091-1-richard.henderson@linaro.org> References: <20180514221219.7091-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH v5 01/28] fpu/softfloat: Fix conversion from uint64 to float128 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org, Petr Tesarik Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Petr Tesarik The significand is passed to normalizeRoundAndPackFloat128() as high first, low second. The current code passes the integer first, so the result is incorrectly shifted left by 64 bits. This bug affects the emulation of s390x instruction CXLGBR (convert from logical 64-bit binary-integer operand to extended BFP result). Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Petr Tesarik Message-Id: <20180511071052.1443-1-ptesarik@suse.com> Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Tested-by: Alex Benn=C3=A9e --- fpu/softfloat.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index bc0f52fa54..d07419324a 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -3147,7 +3147,7 @@ float128 uint64_to_float128(uint64_t a, float_status = *status) if (a =3D=3D 0) { return float128_zero; } - return normalizeRoundAndPackFloat128(0, 0x406E, a, 0, status); + return normalizeRoundAndPackFloat128(0, 0x406E, 0, a, status); } =20 =20 --=20 2.17.0 From nobody Wed Oct 29 23:02:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526336270141942.0024713016579; Mon, 14 May 2018 15:17:50 -0700 (PDT) Received: from localhost ([::1]:49902 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILmm-0003f2-Kh for importer@patchew.org; Mon, 14 May 2018 18:17:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52373) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILhk-0007nM-Ef for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fILhi-0007Ku-Iy for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:28 -0400 Received: from mail-pl0-x243.google.com ([2607:f8b0:400e:c01::243]:46770) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fILhi-0007Jj-9E for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:26 -0400 Received: by mail-pl0-x243.google.com with SMTP id 30-v6so3308922pld.13 for ; Mon, 14 May 2018 15:12:26 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id y2-v6sm14512457pgp.92.2018.05.14.15.12.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 May 2018 15:12:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VenDa8tHdyNBHcmt5bnMZDmY8bNh2PQHuQqyvWp2pMY=; b=WohpFkAcq05POrNffnXj2V8fJy0pVhcbyNhEI0mRWw2/nHZt0+rUfwwsqyD/GVKHH2 FgYW2VmA3QX2NBMyjHaJZaE5TpJkvv4DaRlMkmehEp3p4ellWhmtgsU6fiQgsgpa35FW IkmMbW0chbK6hcU5l5m3jdJsMzATLJy6ObnJI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VenDa8tHdyNBHcmt5bnMZDmY8bNh2PQHuQqyvWp2pMY=; b=nSc8G1V1L7R7lSus+d15Y1XkqbcZ857UjJd621SnIkEfTUQ29uh9/SUUtPTmRFrHPz 4CcJk4bREYNCToQffuKW6SWEKSNJNTCwqcexxRU6qwTKl94s1q3JraAm2kXig9iJSvLy +dKGWLBx+ih6nQtMnww4BxzgmBe3d5JSlcDL/F8n8+d4KNaHdz/Vrb7Vc+vHUU3d61qE 6ckSNAPzI52aJeXOHFI4PYUEZn99YJ+4ipEQGORtpWu9cVhPYLA5gzvOZTLE99Yxo5O/ wtRJwExyvFyc9qL7eroJmHV1kWhlxSkvD9q2BZfSPj6lMxdsqKOh+X5NKTIxKWTULv0A Ed9Q== X-Gm-Message-State: ALKqPweOaOm3UjKRC4oWHcndvN9wbNX7B7Frg/TPZ9/H5+xlWBmqD6kV qR3suoZ+7+hrflS6MbNBNiHFvWUIHRA= X-Google-Smtp-Source: AB8JxZrSEtwRyZjmCyFpIqk1v8Jt7cbFQ3SeG8tqzLtj+VuuGdkzSl9F0fTr/P0in7uB/ig72hsnbw== X-Received: by 2002:a17:902:b949:: with SMTP id h9-v6mr11550052pls.146.1526335944926; Mon, 14 May 2018 15:12:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 May 2018 15:11:53 -0700 Message-Id: <20180514221219.7091-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180514221219.7091-1-richard.henderson@linaro.org> References: <20180514221219.7091-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v5 02/28] fpu/softfloat: Merge NO_SIGNALING_NANS definitions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Move the ifdef inside the relevant functions instead of duplicating the function declarations. Reviewed-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- fpu/softfloat-specialize.h | 100 +++++++++++++++---------------------- 1 file changed, 40 insertions(+), 60 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 27834af0de..58b05718c8 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -233,17 +233,6 @@ typedef struct { uint64_t high, low; } commonNaNT; =20 -#ifdef NO_SIGNALING_NANS -int float16_is_quiet_nan(float16 a_, float_status *status) -{ - return float16_is_any_nan(a_); -} - -int float16_is_signaling_nan(float16 a_, float_status *status) -{ - return 0; -} -#else /*------------------------------------------------------------------------= ---- | Returns 1 if the half-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -251,12 +240,16 @@ int float16_is_signaling_nan(float16 a_, float_status= *status) =20 int float16_is_quiet_nan(float16 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return float16_is_any_nan(a_); +#else uint16_t a =3D float16_val(a_); if (status->snan_bit_is_one) { return (((a >> 9) & 0x3F) =3D=3D 0x3E) && (a & 0x1FF); } else { return ((a & ~0x8000) >=3D 0x7C80); } +#endif } =20 /*------------------------------------------------------------------------= ---- @@ -266,14 +259,17 @@ int float16_is_quiet_nan(float16 a_, float_status *st= atus) =20 int float16_is_signaling_nan(float16 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return 0; +#else uint16_t a =3D float16_val(a_); if (status->snan_bit_is_one) { return ((a & ~0x8000) >=3D 0x7C80); } else { return (((a >> 9) & 0x3F) =3D=3D 0x3E) && (a & 0x1FF); } -} #endif +} =20 /*------------------------------------------------------------------------= ---- | Returns a quiet NaN if the half-precision floating point value `a' is a @@ -333,17 +329,6 @@ static float16 commonNaNToFloat16(commonNaNT a, float_= status *status) } } =20 -#ifdef NO_SIGNALING_NANS -int float32_is_quiet_nan(float32 a_, float_status *status) -{ - return float32_is_any_nan(a_); -} - -int float32_is_signaling_nan(float32 a_, float_status *status) -{ - return 0; -} -#else /*------------------------------------------------------------------------= ---- | Returns 1 if the single-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -351,12 +336,16 @@ int float32_is_signaling_nan(float32 a_, float_status= *status) =20 int float32_is_quiet_nan(float32 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return float32_is_any_nan(a_); +#else uint32_t a =3D float32_val(a_); if (status->snan_bit_is_one) { return (((a >> 22) & 0x1FF) =3D=3D 0x1FE) && (a & 0x003FFFFF); } else { return ((uint32_t)(a << 1) >=3D 0xFF800000); } +#endif } =20 /*------------------------------------------------------------------------= ---- @@ -366,14 +355,17 @@ int float32_is_quiet_nan(float32 a_, float_status *st= atus) =20 int float32_is_signaling_nan(float32 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return 0; +#else uint32_t a =3D float32_val(a_); if (status->snan_bit_is_one) { return ((uint32_t)(a << 1) >=3D 0xFF800000); } else { return (((a >> 22) & 0x1FF) =3D=3D 0x1FE) && (a & 0x003FFFFF); } -} #endif +} =20 /*------------------------------------------------------------------------= ---- | Returns a quiet NaN if the single-precision floating point value `a' is a @@ -744,17 +736,6 @@ static float32 propagateFloat32NaN(float32 a, float32 = b, float_status *status) } } =20 -#ifdef NO_SIGNALING_NANS -int float64_is_quiet_nan(float64 a_, float_status *status) -{ - return float64_is_any_nan(a_); -} - -int float64_is_signaling_nan(float64 a_, float_status *status) -{ - return 0; -} -#else /*------------------------------------------------------------------------= ---- | Returns 1 if the double-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -762,6 +743,9 @@ int float64_is_signaling_nan(float64 a_, float_status *= status) =20 int float64_is_quiet_nan(float64 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return float64_is_any_nan(a_); +#else uint64_t a =3D float64_val(a_); if (status->snan_bit_is_one) { return (((a >> 51) & 0xFFF) =3D=3D 0xFFE) @@ -769,6 +753,7 @@ int float64_is_quiet_nan(float64 a_, float_status *stat= us) } else { return ((a << 1) >=3D 0xFFF0000000000000ULL); } +#endif } =20 /*------------------------------------------------------------------------= ---- @@ -778,6 +763,9 @@ int float64_is_quiet_nan(float64 a_, float_status *stat= us) =20 int float64_is_signaling_nan(float64 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return 0; +#else uint64_t a =3D float64_val(a_); if (status->snan_bit_is_one) { return ((a << 1) >=3D 0xFFF0000000000000ULL); @@ -785,8 +773,8 @@ int float64_is_signaling_nan(float64 a_, float_status *= status) return (((a >> 51) & 0xFFF) =3D=3D 0xFFE) && (a & LIT64(0x0007FFFFFFFFFFFF)); } -} #endif +} =20 /*------------------------------------------------------------------------= ---- | Returns a quiet NaN if the double-precision floating point value `a' is a @@ -899,17 +887,6 @@ static float64 propagateFloat64NaN(float64 a, float64 = b, float_status *status) } } =20 -#ifdef NO_SIGNALING_NANS -int floatx80_is_quiet_nan(floatx80 a_, float_status *status) -{ - return floatx80_is_any_nan(a_); -} - -int floatx80_is_signaling_nan(floatx80 a_, float_status *status) -{ - return 0; -} -#else /*------------------------------------------------------------------------= ---- | Returns 1 if the extended double-precision floating-point value `a' is a | quiet NaN; otherwise returns 0. This slightly differs from the same @@ -918,6 +895,9 @@ int floatx80_is_signaling_nan(floatx80 a_, float_status= *status) =20 int floatx80_is_quiet_nan(floatx80 a, float_status *status) { +#ifdef NO_SIGNALING_NANS + return floatx80_is_any_nan(a); +#else if (status->snan_bit_is_one) { uint64_t aLow; =20 @@ -929,6 +909,7 @@ int floatx80_is_quiet_nan(floatx80 a, float_status *sta= tus) return ((a.high & 0x7FFF) =3D=3D 0x7FFF) && (LIT64(0x8000000000000000) <=3D ((uint64_t)(a.low << 1))); } +#endif } =20 /*------------------------------------------------------------------------= ---- @@ -939,6 +920,9 @@ int floatx80_is_quiet_nan(floatx80 a, float_status *sta= tus) =20 int floatx80_is_signaling_nan(floatx80 a, float_status *status) { +#ifdef NO_SIGNALING_NANS + return 0; +#else if (status->snan_bit_is_one) { return ((a.high & 0x7FFF) =3D=3D 0x7FFF) && ((a.low << 1) >=3D 0x8000000000000000ULL); @@ -950,8 +934,8 @@ int floatx80_is_signaling_nan(floatx80 a, float_status = *status) && (uint64_t)(aLow << 1) && (a.low =3D=3D aLow); } -} #endif +} =20 /*------------------------------------------------------------------------= ---- | Returns a quiet NaN if the extended double-precision floating point value @@ -1060,17 +1044,6 @@ floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b= , float_status *status) } } =20 -#ifdef NO_SIGNALING_NANS -int float128_is_quiet_nan(float128 a_, float_status *status) -{ - return float128_is_any_nan(a_); -} - -int float128_is_signaling_nan(float128 a_, float_status *status) -{ - return 0; -} -#else /*------------------------------------------------------------------------= ---- | Returns 1 if the quadruple-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -1078,6 +1051,9 @@ int float128_is_signaling_nan(float128 a_, float_stat= us *status) =20 int float128_is_quiet_nan(float128 a, float_status *status) { +#ifdef NO_SIGNALING_NANS + return float128_is_any_nan(a); +#else if (status->snan_bit_is_one) { return (((a.high >> 47) & 0xFFFF) =3D=3D 0xFFFE) && (a.low || (a.high & 0x00007FFFFFFFFFFFULL)); @@ -1085,6 +1061,7 @@ int float128_is_quiet_nan(float128 a, float_status *s= tatus) return ((a.high << 1) >=3D 0xFFFF000000000000ULL) && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); } +#endif } =20 /*------------------------------------------------------------------------= ---- @@ -1094,6 +1071,9 @@ int float128_is_quiet_nan(float128 a, float_status *s= tatus) =20 int float128_is_signaling_nan(float128 a, float_status *status) { +#ifdef NO_SIGNALING_NANS + return 0; +#else if (status->snan_bit_is_one) { return ((a.high << 1) >=3D 0xFFFF000000000000ULL) && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); @@ -1101,8 +1081,8 @@ int float128_is_signaling_nan(float128 a, float_statu= s *status) return (((a.high >> 47) & 0xFFFF) =3D=3D 0xFFFE) && (a.low || (a.high & LIT64(0x00007FFFFFFFFFFF))); } -} #endif +} =20 /*------------------------------------------------------------------------= ---- | Returns a quiet NaN if the quadruple-precision floating point value `a' = is --=20 2.17.0 From nobody Wed Oct 29 23:02:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152633609986524.554174462062065; Mon, 14 May 2018 15:14:59 -0700 (PDT) Received: from localhost ([::1]:49883 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILkA-0001Oq-VK for importer@patchew.org; Mon, 14 May 2018 18:14:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52394) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILhm-0007oZ-0D for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fILhk-0007Ob-7q for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:29 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:39427) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fILhj-0007Ms-VV for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:28 -0400 Received: by mail-pg0-x242.google.com with SMTP id e1-v6so6066289pga.6 for ; Mon, 14 May 2018 15:12:27 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id y2-v6sm14512457pgp.92.2018.05.14.15.12.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 May 2018 15:12:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4TmTQacKaQ7wTQhVbzzcmlNjpPvSpyKeaBJzKv3A39I=; b=XdPzEuQNnOfED3+9kvdKHKdL7p1IhD6hDJ3kACFDuuu2+e/j5CrmZVQxYJQ1m5YtGz 7WSmuArybPuz2X6VEzsZi7iQyjE/kZtEfL9KBHuWCZrSnw3D7Saq76fkSONFVVDDS/ct DqYW8M35rePv+TbfZZFVCPO+tKEz1bMFSbBtM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4TmTQacKaQ7wTQhVbzzcmlNjpPvSpyKeaBJzKv3A39I=; b=otdiz30PZ1mVx1nS3keyvMMu873MN/He4kRGOyQX9HD3mJNeyWBSwcqTNqLDJdcQQP kO0tNeT3vvlwKuPqMI9ear3xrMEDEEYi5KhuLmDIQvWUQqPI4GB+FAuAryqrw/HxUm8K p6gUsDF3vAMRG4wPyGIh9bqqEUXeg6RyC7Pd1Gy5xkdIZT/0lN0+4hA3DXKb+H1M/9vD lRbQDSyoCbEhgtwDzbGFWaaKBq9M/jZbRbbqEz5wA/dsLwv+ybIZLKFbsFrSZx5pmGcf O17PfzSnibGQH6kJeK4raJ3hQCHV2McXg/QyUVWBolpGPK1QjKUBkl5NCeUESXosCbFm QASA== X-Gm-Message-State: ALKqPwdOCxYz198ARc+sG1IP7W0lP8sNOMRhoVIS9QWov7DT0mSxezmO qiJr0z8Pxyg9QfTnvH7VXR3XXwJa66U= X-Google-Smtp-Source: AB8JxZofbGBV0lN4dHgnVYWMqGh4VXVGbfd2JdTXfA3jzonuu94d4YO0aCM93xD6FsTz7xcuKX5jsQ== X-Received: by 2002:a62:3d54:: with SMTP id k81-v6mr12140164pfa.193.1526335946515; Mon, 14 May 2018 15:12:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 May 2018 15:11:54 -0700 Message-Id: <20180514221219.7091-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180514221219.7091-1-richard.henderson@linaro.org> References: <20180514221219.7091-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v5 03/28] fpu/softfloat: Split floatXX_silence_nan from floatXX_maybe_silence_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 The new function assumes that the input is an SNaN and does not double-check. Reviewed-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- fpu/softfloat-specialize.h | 174 +++++++++++++++++++++++++------------ include/fpu/softfloat.h | 5 ++ 2 files changed, 123 insertions(+), 56 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 58b05718c8..4fc9ea4ac0 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -271,22 +271,35 @@ int float16_is_signaling_nan(float16 a_, float_status= *status) #endif } =20 +/*------------------------------------------------------------------------= ---- +| Returns a quiet NaN from a signalling NaN for the half-precision +| floating point value `a'. +*-------------------------------------------------------------------------= ---*/ + +float16 float16_silence_nan(float16 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#else + if (status->snan_bit_is_one) { + return float16_default_nan(status); + } else { + return a | (1 << 9); + } +#endif +} + /*------------------------------------------------------------------------= ---- | Returns a quiet NaN if the half-precision floating point value `a' is a | signaling NaN; otherwise returns `a'. *-------------------------------------------------------------------------= ---*/ -float16 float16_maybe_silence_nan(float16 a_, float_status *status) + +float16 float16_maybe_silence_nan(float16 a, float_status *status) { - if (float16_is_signaling_nan(a_, status)) { - if (status->snan_bit_is_one) { - return float16_default_nan(status); - } else { - uint16_t a =3D float16_val(a_); - a |=3D (1 << 9); - return make_float16(a); - } + if (float16_is_signaling_nan(a, status)) { + return float16_silence_nan(a, status); } - return a_; + return a; } =20 /*------------------------------------------------------------------------= ---- @@ -367,30 +380,40 @@ int float32_is_signaling_nan(float32 a_, float_status= *status) #endif } =20 +/*------------------------------------------------------------------------= ---- +| Returns a quiet NaN from a signalling NaN for the single-precision +| floating point value `a'. +*-------------------------------------------------------------------------= ---*/ + +float32 float32_silence_nan(float32 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#else + if (status->snan_bit_is_one) { +# ifdef TARGET_HPPA + a &=3D ~0x00400000; + a |=3D 0x00200000; + return a; +# else + return float32_default_nan(status); +# endif + } else { + return a | (1 << 22); + } +#endif +} /*------------------------------------------------------------------------= ---- | Returns a quiet NaN if the single-precision floating point value `a' is a | signaling NaN; otherwise returns `a'. *-------------------------------------------------------------------------= ---*/ =20 -float32 float32_maybe_silence_nan(float32 a_, float_status *status) +float32 float32_maybe_silence_nan(float32 a, float_status *status) { - if (float32_is_signaling_nan(a_, status)) { - if (status->snan_bit_is_one) { -#ifdef TARGET_HPPA - uint32_t a =3D float32_val(a_); - a &=3D ~0x00400000; - a |=3D 0x00200000; - return make_float32(a); -#else - return float32_default_nan(status); -#endif - } else { - uint32_t a =3D float32_val(a_); - a |=3D (1 << 22); - return make_float32(a); - } + if (float32_is_signaling_nan(a, status)) { + return float32_silence_nan(a, status); } - return a_; + return a; } =20 /*------------------------------------------------------------------------= ---- @@ -776,30 +799,41 @@ int float64_is_signaling_nan(float64 a_, float_status= *status) #endif } =20 +/*------------------------------------------------------------------------= ---- +| Returns a quiet NaN from a signalling NaN for the double-precision +| floating point value `a'. +*-------------------------------------------------------------------------= ---*/ + +float64 float64_silence_nan(float64 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#else + if (status->snan_bit_is_one) { +# ifdef TARGET_HPPA + a &=3D ~0x0008000000000000ULL; + a |=3D 0x0004000000000000ULL; + return a; +# else + return float64_default_nan(status); +# endif + } else { + return a | LIT64(0x0008000000000000); + } +#endif +} + /*------------------------------------------------------------------------= ---- | Returns a quiet NaN if the double-precision floating point value `a' is a | signaling NaN; otherwise returns `a'. *-------------------------------------------------------------------------= ---*/ =20 -float64 float64_maybe_silence_nan(float64 a_, float_status *status) +float64 float64_maybe_silence_nan(float64 a, float_status *status) { - if (float64_is_signaling_nan(a_, status)) { - if (status->snan_bit_is_one) { -#ifdef TARGET_HPPA - uint64_t a =3D float64_val(a_); - a &=3D ~0x0008000000000000ULL; - a |=3D 0x0004000000000000ULL; - return make_float64(a); -#else - return float64_default_nan(status); -#endif - } else { - uint64_t a =3D float64_val(a_); - a |=3D LIT64(0x0008000000000000); - return make_float64(a); - } + if (float64_is_signaling_nan(a, status)) { + return float64_silence_nan(a, status); } - return a_; + return a; } =20 /*------------------------------------------------------------------------= ---- @@ -937,6 +971,25 @@ int floatx80_is_signaling_nan(floatx80 a, float_status= *status) #endif } =20 +/*------------------------------------------------------------------------= ---- +| Returns a quiet NaN from a signalling NaN for the extended double-precis= ion +| floating point value `a'. +*-------------------------------------------------------------------------= ---*/ + +floatx80 floatx80_silence_nan(floatx80 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#else + if (status->snan_bit_is_one) { + return floatx80_default_nan(status); + } else { + a.low |=3D LIT64(0xC000000000000000); + return a; + } +#endif +} + /*------------------------------------------------------------------------= ---- | Returns a quiet NaN if the extended double-precision floating point value | `a' is a signaling NaN; otherwise returns `a'. @@ -945,12 +998,7 @@ int floatx80_is_signaling_nan(floatx80 a, float_status= *status) floatx80 floatx80_maybe_silence_nan(floatx80 a, float_status *status) { if (floatx80_is_signaling_nan(a, status)) { - if (status->snan_bit_is_one) { - a =3D floatx80_default_nan(status); - } else { - a.low |=3D LIT64(0xC000000000000000); - return a; - } + return floatx80_silence_nan(a, status); } return a; } @@ -1084,6 +1132,25 @@ int float128_is_signaling_nan(float128 a, float_stat= us *status) #endif } =20 +/*------------------------------------------------------------------------= ---- +| Returns a quiet NaN from a signalling NaN for the quadruple-precision +| floating point value `a'. +*-------------------------------------------------------------------------= ---*/ + +float128 float128_silence_nan(float128 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#else + if (status->snan_bit_is_one) { + return float128_default_nan(status); + } else { + a.high |=3D LIT64(0x0000800000000000); + return a; + } +#endif +} + /*------------------------------------------------------------------------= ---- | Returns a quiet NaN if the quadruple-precision floating point value `a' = is | a signaling NaN; otherwise returns `a'. @@ -1092,12 +1159,7 @@ int float128_is_signaling_nan(float128 a, float_stat= us *status) float128 float128_maybe_silence_nan(float128 a, float_status *status) { if (float128_is_signaling_nan(a, status)) { - if (status->snan_bit_is_one) { - a =3D float128_default_nan(status); - } else { - a.high |=3D LIT64(0x0000800000000000); - return a; - } + return float128_silence_nan(a, status); } return a; } diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 36626a501b..43962dc3f5 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -257,6 +257,7 @@ int float16_compare_quiet(float16, float16, float_statu= s *status); =20 int float16_is_quiet_nan(float16, float_status *status); int float16_is_signaling_nan(float16, float_status *status); +float16 float16_silence_nan(float16, float_status *status); float16 float16_maybe_silence_nan(float16, float_status *status); =20 static inline int float16_is_any_nan(float16 a) @@ -368,6 +369,7 @@ float32 float32_minnummag(float32, float32, float_statu= s *status); float32 float32_maxnummag(float32, float32, float_status *status); int float32_is_quiet_nan(float32, float_status *status); int float32_is_signaling_nan(float32, float_status *status); +float32 float32_silence_nan(float32, float_status *status); float32 float32_maybe_silence_nan(float32, float_status *status); float32 float32_scalbn(float32, int, float_status *status); =20 @@ -497,6 +499,7 @@ float64 float64_minnummag(float64, float64, float_statu= s *status); float64 float64_maxnummag(float64, float64, float_status *status); int float64_is_quiet_nan(float64 a, float_status *status); int float64_is_signaling_nan(float64, float_status *status); +float64 float64_silence_nan(float64, float_status *status); float64 float64_maybe_silence_nan(float64, float_status *status); float64 float64_scalbn(float64, int, float_status *status); =20 @@ -600,6 +603,7 @@ int floatx80_compare(floatx80, floatx80, float_status *= status); int floatx80_compare_quiet(floatx80, floatx80, float_status *status); int floatx80_is_quiet_nan(floatx80, float_status *status); int floatx80_is_signaling_nan(floatx80, float_status *status); +floatx80 floatx80_silence_nan(floatx80, float_status *status); floatx80 floatx80_maybe_silence_nan(floatx80, float_status *status); floatx80 floatx80_scalbn(floatx80, int, float_status *status); =20 @@ -811,6 +815,7 @@ int float128_compare(float128, float128, float_status *= status); int float128_compare_quiet(float128, float128, float_status *status); int float128_is_quiet_nan(float128, float_status *status); int float128_is_signaling_nan(float128, float_status *status); +float128 float128_silence_nan(float128, float_status *status); float128 float128_maybe_silence_nan(float128, float_status *status); float128 float128_scalbn(float128, int, float_status *status); =20 --=20 2.17.0 From nobody Wed Oct 29 23:02:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526336312409836.4965558456554; Mon, 14 May 2018 15:18:32 -0700 (PDT) Received: from localhost ([::1]:49906 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILnY-0004EO-EG for importer@patchew.org; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id y2-v6sm14512457pgp.92.2018.05.14.15.12.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 May 2018 15:12:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ebFxh3+eguD7gF5K8+FfZvuBwarnBxL0aNh5uRBWCAs=; b=cD6+Nu783+P3CV39HIkihsJG14Lpep8gWzTnWD3crTjqZolahDVU1wfb74Z29WYqjS OGqaE1hwT7rYxjO//2TTGjmsryKwcpVXVaidiJfaVH3HlCbuy/Jw9+FXuXaSp7VM9Zpc 2rDWMVRyY5vbV0/2Ktt1maSyzg1ijdKqImdvg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ebFxh3+eguD7gF5K8+FfZvuBwarnBxL0aNh5uRBWCAs=; b=gmJbuwpDqG3prz69dE2i//iyps9APLS8BYl6iU8VuVytS05jMLWT5HcSLic1T5PxOD 9WfG87XY6lMujBjhazbWsrJvthGByAA9WpYVAER7MZwVU9PzxLa7vYqUYky1az5Sv+TZ h9uCNPNk+UZbl69W1CGb3CGbWrYwVt07+O3CL5AvAdJA0UlDBMeudv0M0jWG7BJIfvr+ hrH9dOv0J/tk0E2MBUxulQm7hqvSP5nG0jhMv4YE9uhYI9qCrwe5fXQIGBl5bgVfzdc3 d8+DD+VhSlcFX/z2N2jbRuN366JaoA2tNTmtyoGDCDTth4MzoPayh5GvQRRxuVoioUwy 5pBA== X-Gm-Message-State: ALKqPweJfcimnJ/fk/9Yr24seKORFFXKnAH5HgITAkPy8+UCz7x+C+yw KqD9kQceq/ZBlVIyoQC+BMRcZEYalGs= X-Google-Smtp-Source: AB8JxZrBcutDwDlOQVNMb2owIN8lqW+uowcunzDvA5TAsPm2Hsv8FUUq5PBrRe8urLIJj5r0YpwbsA== X-Received: by 2002:a62:3889:: with SMTP id f131-v6mr12184027pfa.173.1526335947560; Mon, 14 May 2018 15:12:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 May 2018 15:11:55 -0700 Message-Id: <20180514221219.7091-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180514221219.7091-1-richard.henderson@linaro.org> References: <20180514221219.7091-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v5 04/28] fpu/softfloat: Move softfloat-specialize.h below FloatParts definition X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 We want to be able to specialize on the canonical representation. Reviewed-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- fpu/softfloat.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index d07419324a..0d17027379 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -95,16 +95,6 @@ this code that are retained. *-------------------------------------------------------------------------= ---*/ #include "fpu/softfloat-macros.h" =20 -/*------------------------------------------------------------------------= ---- -| Functions and definitions to determine: (1) whether tininess for underf= low -| is detected before or after rounding by default, (2) what (if anything) -| happens when exceptions are raised, (3) how signaling NaNs are distingui= shed -| from quiet NaNs, (4) the default generated quiet NaNs, and (5) how NaNs -| are propagated from function inputs to output. These details are target- -| specific. -*-------------------------------------------------------------------------= ---*/ -#include "softfloat-specialize.h" - /*------------------------------------------------------------------------= ---- | Returns the fraction bits of the half-precision floating-point value `a'. *-------------------------------------------------------------------------= ---*/ @@ -322,6 +312,16 @@ static inline float64 float64_pack_raw(FloatParts p) return make_float64(pack_raw(float64_params, p)); } =20 +/*------------------------------------------------------------------------= ---- +| Functions and definitions to determine: (1) whether tininess for underf= low +| is detected before or after rounding by default, (2) what (if anything) +| happens when exceptions are raised, (3) how signaling NaNs are distingui= shed +| from quiet NaNs, (4) the default generated quiet NaNs, and (5) how NaNs +| are propagated from function inputs to output. These details are target- +| specific. +*-------------------------------------------------------------------------= ---*/ +#include "softfloat-specialize.h" + /* Canonicalize EXP and FRAC, setting CLS. */ static FloatParts canonicalize(FloatParts part, const FloatFmt *parm, float_status *status) --=20 2.17.0 From nobody Wed Oct 29 23:02:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526336182228160.10987826733458; Mon, 14 May 2018 15:16:22 -0700 (PDT) Received: from localhost ([::1]:49895 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILlV-0002ZJ-Ar for importer@patchew.org; Mon, 14 May 2018 18:16:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52407) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILhn-0007pw-3l for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fILhm-0007T6-3g for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:31 -0400 Received: from mail-pl0-x243.google.com ([2607:f8b0:400e:c01::243]:39313) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fILhl-0007S0-Un for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:30 -0400 Received: by mail-pl0-x243.google.com with SMTP id c19-v6so8153090pls.6 for ; Mon, 14 May 2018 15:12:29 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id y2-v6sm14512457pgp.92.2018.05.14.15.12.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 May 2018 15:12:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VrjybWtyS9x1dk/X8ACHYXOClLJ40q5WBHgCIV0De2Q=; b=WqRcg4+Vqe4G0yuI0aKgKT2BmRX4A9RqASLhRtXu+IbKKTIKDTTfXh+DSG4cZI9cj+ iqxxspLnx9sqBRh5nUGffIQ1mhQRiBk6V5gZfyfiaaUw3Z8wrlA1uB8/2zsql+NyPhq1 jUe2PjaTiYRVOeWhsVUDHoiZgAPFbA1jhtKv0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VrjybWtyS9x1dk/X8ACHYXOClLJ40q5WBHgCIV0De2Q=; b=H7V7FAceuMvTJftyRO52qIDV0lgyx0gl3ECkJFCuPANMnAYc0Ai2wHpBJL4RXEPOMY meealf2P8u3xz1qeaEGGTXKube+rVXrDUHWrJwCihD8VTmYdb05fQOisQt4glyG8hH5B k+ZzWBS1o3x/MhZZdGOStqQhTYaXOQ3+MTbT8N+nng9AotpeoAzXQbF7EZruaBjSdD6i F3c4I59zpLcZnMt40KFaBQhrWd1kpVY8zCCVRRUuYakSuI/nQGoCTU+IzsCC5bx3esxZ x/igb3Ev2L2bUZeI6fR0DT+OvRnDUJ9H6HB3WYNB41mwTIVnaWuCYEQRWsJ1moGjhu/1 4oKg== X-Gm-Message-State: ALKqPwf1gxqbHoDk3EBwGFkNSyZl43DyVdBSDybr0/hCocsz/Vg88Ygr qYX7FSYxQYMfsEPf6VTBXwJ4aKrTF88= X-Google-Smtp-Source: AB8JxZqJjwN/nezLJkajlZX8/4WoHG/BAu9+IT7YuW6TdT+CpVWPHrjuMknkHhWmdi4M1rFXE8/KIQ== X-Received: by 2002:a17:902:b68f:: with SMTP id c15-v6mr11566196pls.201.1526335948782; Mon, 14 May 2018 15:12:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 May 2018 15:11:56 -0700 Message-Id: <20180514221219.7091-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180514221219.7091-1-richard.henderson@linaro.org> References: <20180514221219.7091-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v5 05/28] fpu/softfloat: Canonicalize NaN fraction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Shift the NaN fraction to a canonical position, much like we do for the fraction of normal numbers. This will facilitate manipulation of NaNs within the shared code paths. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Tested-by: Alex Benn=C3=A9e --- fpu/softfloat.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 0d17027379..607c4a78d5 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -330,10 +330,11 @@ static FloatParts canonicalize(FloatParts part, const= FloatFmt *parm, if (part.frac =3D=3D 0) { part.cls =3D float_class_inf; } else { + part.frac <<=3D parm->frac_shift; #ifdef NO_SIGNALING_NANS part.cls =3D float_class_qnan; #else - int64_t msb =3D part.frac << (parm->frac_shift + 2); + int64_t msb =3D part.frac << 2; if ((msb < 0) =3D=3D status->snan_bit_is_one) { part.cls =3D float_class_snan; } else { @@ -480,6 +481,7 @@ static FloatParts round_canonical(FloatParts p, float_s= tatus *s, case float_class_qnan: case float_class_snan: exp =3D exp_max; + frac >>=3D parm->frac_shift; break; =20 default: @@ -503,6 +505,7 @@ static float16 float16_round_pack_canonical(FloatParts = p, float_status *s) case float_class_dnan: return float16_default_nan(s); case float_class_msnan: + p.frac >>=3D float16_params.frac_shift; return float16_maybe_silence_nan(float16_pack_raw(p), s); default: p =3D round_canonical(p, s, &float16_params); @@ -521,6 +524,7 @@ static float32 float32_round_pack_canonical(FloatParts = p, float_status *s) case float_class_dnan: return float32_default_nan(s); case float_class_msnan: + p.frac >>=3D float32_params.frac_shift; return float32_maybe_silence_nan(float32_pack_raw(p), s); default: p =3D round_canonical(p, s, &float32_params); @@ -539,6 +543,7 @@ static float64 float64_round_pack_canonical(FloatParts = p, float_status *s) case float_class_dnan: return float64_default_nan(s); case float_class_msnan: + p.frac >>=3D float64_params.frac_shift; return float64_maybe_silence_nan(float64_pack_raw(p), s); default: p =3D round_canonical(p, s, &float64_params); --=20 2.17.0 From nobody Wed Oct 29 23:02:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526336373224928.2067675155093; Mon, 14 May 2018 15:19:33 -0700 (PDT) Received: from localhost ([::1]:49911 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILoa-00054c-A7 for importer@patchew.org; Mon, 14 May 2018 18:19:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52423) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILho-0007rT-JT for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fILhn-0007Vn-Ja for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:32 -0400 Received: from mail-pl0-x244.google.com ([2607:f8b0:400e:c01::244]:42494) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fILhn-0007Ug-DX for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:31 -0400 Received: by mail-pl0-x244.google.com with SMTP id u6-v6so8148774pls.9 for ; Mon, 14 May 2018 15:12:31 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id y2-v6sm14512457pgp.92.2018.05.14.15.12.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 May 2018 15:12:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sMFvxehNW2WjX/2qTbv+EhzKGZ6dKWsMD6UmFGMjN8k=; b=Xw4oWvHSUvr/S9d3lFMZDuiXtbPqogZB9Fn0mY4PYEoNT3ytPLUBUdA7GMw6MNwSne 1pZ68NXADgioiUqmScfeT5fzxiiBlCO4riEE6lJpUiVv2bwG3z3yWc/GytLdOYn1P774 +npjrGV3nbZJ7Q8AdUZF7nwjpoUAY0/QOD0BY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sMFvxehNW2WjX/2qTbv+EhzKGZ6dKWsMD6UmFGMjN8k=; b=RZEBFj80ur4yjCrg4TUAtEeE3UjuXjFKmGNFH4XTRm8ANxIVWSy4Ru6ezRVQ4UtoPt mhsqKIp9LVsxuD6ouVLd8ICwEbINmDnduQklifU/bamIyTnHMmahKPfOMO9y7NOw0THY 12oz2plDrNJscBjsNutxQplrBFduOX8Gk4jWzdYwa8oMMthSf1r5fOq6zXuIYYDfrxvt 82EywN3Ut2vLWM0X0cEpaSnYNosNQT5GxoSR+bUDWfSt3exr4Cl6nN/UIaAahmnPkVGl LLSK0VvZcknAyCARY+MuzThqXXUvqBgq5U8/fwyOcSu1UaqOTkbbEZdTzK24wzlq8M+6 waHw== X-Gm-Message-State: ALKqPwf/fAdVhcpwjNJVH2YMyZPQ+xVpLoAqDnk4SFP1aOaQvK+wDcP2 gWiIUHyqvMe9QEc9AyLmXn/HpN4ncqg= X-Google-Smtp-Source: AB8JxZqmaaZda0xaFS+1t7WCNMJ1scav6aAzYxE3X0HhM0o0iQ/LrQC6SUHet8zMPlVRMZv6RkEaeg== X-Received: by 2002:a17:902:10c:: with SMTP id 12-v6mr11712846plb.252.1526335950252; Mon, 14 May 2018 15:12:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 May 2018 15:11:57 -0700 Message-Id: <20180514221219.7091-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180514221219.7091-1-richard.henderson@linaro.org> References: <20180514221219.7091-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v5 06/28] fpu/softfloat: Introduce parts_is_snan_frac X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Tested-by: Alex Benn=C3=A9e --- fpu/softfloat-specialize.h | 15 +++++++++++++++ fpu/softfloat.c | 12 ++---------- 2 files changed, 17 insertions(+), 10 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 4fc9ea4ac0..515cb12cfa 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -86,6 +86,21 @@ this code that are retained. #define NO_SIGNALING_NANS 1 #endif =20 +/*------------------------------------------------------------------------= ---- +| For the deconstructed floating-point with fraction FRAC, return true +| if the fraction represents a signalling NaN; otherwise false. +*-------------------------------------------------------------------------= ---*/ + +static bool parts_is_snan_frac(uint64_t frac, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + return false; +#else + flag msb =3D extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1); + return msb =3D=3D status->snan_bit_is_one; +#endif +} + /*------------------------------------------------------------------------= ---- | The pattern for a default generated half-precision NaN. *-------------------------------------------------------------------------= ---*/ diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 607c4a78d5..19f40d6932 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -331,16 +331,8 @@ static FloatParts canonicalize(FloatParts part, const = FloatFmt *parm, part.cls =3D float_class_inf; } else { part.frac <<=3D parm->frac_shift; -#ifdef NO_SIGNALING_NANS - part.cls =3D float_class_qnan; -#else - int64_t msb =3D part.frac << 2; - if ((msb < 0) =3D=3D status->snan_bit_is_one) { - part.cls =3D float_class_snan; - } else { - part.cls =3D float_class_qnan; - } -#endif + part.cls =3D (parts_is_snan_frac(part.frac, status) + ? float_class_snan : float_class_qnan); } } else if (part.exp =3D=3D 0) { if (likely(part.frac =3D=3D 0)) { --=20 2.17.0 From nobody Wed Oct 29 23:02:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 152633665292562.91454804211821; Mon, 14 May 2018 15:24:12 -0700 (PDT) Received: from localhost ([::1]:49943 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILsv-0000ZF-Ue for importer@patchew.org; Mon, 14 May 2018 18:24:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52445) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILhs-0007vk-Uf for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fILhp-0007Zo-Bt for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:36 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:37436) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fILhp-0007X8-3R for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:33 -0400 Received: by mail-pf0-x244.google.com with SMTP id e9-v6so6669184pfi.4 for ; Mon, 14 May 2018 15:12:33 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id y2-v6sm14512457pgp.92.2018.05.14.15.12.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 May 2018 15:12:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+vvqSgQxe1wFpwzrd9m3dE4eIudcFO3NRIbmpaTbg/g=; b=LDiBklzpaKFGMO4pALYqNQio8vgEi5Riy/nx2nCcwy0eqJflwETXjkzyGysjZVaql7 Qa7fGaulr6lIhYR9yF8jfHdRti2GitqtnVdt6fTVTDjoIbL6YisFzwsgQTPEppChI+LO RDhISdMaA/ZVXNcbijb9jheedoZPOikakf/I4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+vvqSgQxe1wFpwzrd9m3dE4eIudcFO3NRIbmpaTbg/g=; b=FMYe7oA0Isak+QvFxKG1IZZKYMXvcNz6pC5RvVD324PGZhYXjOOVPpIYs9DrWJ0mBJ tuWgk2RqsKUgnKJI++vlPr3Q4TQBR5wg44UYizQo0Jrfg9s5hde0FyXc7bhby3ZJ+++7 aQhhF5Ap1f5ngpS/Va9IdPaaGbEl806lh3LE6hxe2jP72aNproIH/3of82U2u70pvbvm l+JR9JsWwAcmpFnWRYLKYW0bwSQjW1ixzsWrHj6aSpSuH2T1iY8YeRo5EAcLSoZ/9O0O lrirzupvq4Q/ttsM9V0IdzUCRn1RWEmohNo0oOZTs/ggo4ap0Un04qm1qb1dbhBUEcO8 hLIQ== X-Gm-Message-State: ALKqPweOTodElbl1Ak46VjJtLbUM7X8fv8VIbNdotwQTylhT624FrSAp K3S8JvZG0kqDav91L+2xX6hfD7R7TFk= X-Google-Smtp-Source: AB8JxZoIdcATq1lZ6Ymwb+eu33YIG/OlcC/dfyYH24mvAY6Def3HURj7A3WfdU7F+ag6hL/SQbEPvw== X-Received: by 2002:a65:62d0:: with SMTP id m16-v6mr9647295pgv.279.1526335951744; Mon, 14 May 2018 15:12:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 May 2018 15:11:58 -0700 Message-Id: <20180514221219.7091-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180514221219.7091-1-richard.henderson@linaro.org> References: <20180514221219.7091-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v5 07/28] fpu/softfloat: Replace float_class_dnan with parts_default_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" With a canonical representation of NaNs, we can return the default nan directly rather than delay the expansion until the final format is known. Note one case where we uselessly assigned to a.sign, which was overwritten/ignored later when expanding float_class_dnan. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Tested-by: Alex Benn=C3=A9e --- fpu/softfloat-specialize.h | 37 +++++++++++++++++++++++++++++++++++++ fpu/softfloat.c | 38 +++++++++++--------------------------- 2 files changed, 48 insertions(+), 27 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 515cb12cfa..0d3d81a52b 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -101,6 +101,43 @@ static bool parts_is_snan_frac(uint64_t frac, float_st= atus *status) #endif } =20 +/*------------------------------------------------------------------------= ---- +| The pattern for a default generated deconstructed floating-point NaN. +*-------------------------------------------------------------------------= ---*/ + +static FloatParts parts_default_nan(float_status *status) +{ + bool sign =3D 0; + uint64_t frac; + +#if defined(TARGET_SPARC) || defined(TARGET_M68K) + frac =3D (1ULL << DECOMPOSED_BINARY_POINT) - 1; +#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) = || \ + defined(TARGET_S390X) || defined(TARGET_RISCV) + frac =3D 1ULL << (DECOMPOSED_BINARY_POINT - 1); +#elif defined(TARGET_HPPA) + frac =3D 1ULL << (DECOMPOSED_BINARY_POINT - 2); +#else + if (status->snan_bit_is_one) { + frac =3D (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; + } else { +#if defined(TARGET_MIPS) + frac =3D 1ULL << (DECOMPOSED_BINARY_POINT - 1); +#else + frac =3D 1ULL << (DECOMPOSED_BINARY_POINT - 1); + sign =3D 1; +#endif + } +#endif + + return (FloatParts) { + .cls =3D float_class_qnan, + .sign =3D sign, + .exp =3D INT_MAX, + .frac =3D frac + }; +} + /*------------------------------------------------------------------------= ---- | The pattern for a default generated half-precision NaN. *-------------------------------------------------------------------------= ---*/ diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 19f40d6932..51780b718f 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -188,7 +188,6 @@ typedef enum __attribute__ ((__packed__)) { float_class_inf, float_class_qnan, /* all NaNs from here */ float_class_snan, - float_class_dnan, float_class_msnan, /* maybe silenced */ } FloatClass; =20 @@ -494,8 +493,6 @@ static FloatParts float16_unpack_canonical(float16 f, f= loat_status *s) static float16 float16_round_pack_canonical(FloatParts p, float_status *s) { switch (p.cls) { - case float_class_dnan: - return float16_default_nan(s); case float_class_msnan: p.frac >>=3D float16_params.frac_shift; return float16_maybe_silence_nan(float16_pack_raw(p), s); @@ -513,8 +510,6 @@ static FloatParts float32_unpack_canonical(float32 f, f= loat_status *s) static float32 float32_round_pack_canonical(FloatParts p, float_status *s) { switch (p.cls) { - case float_class_dnan: - return float32_default_nan(s); case float_class_msnan: p.frac >>=3D float32_params.frac_shift; return float32_maybe_silence_nan(float32_pack_raw(p), s); @@ -532,8 +527,6 @@ static FloatParts float64_unpack_canonical(float64 f, f= loat_status *s) static float64 float64_round_pack_canonical(FloatParts p, float_status *s) { switch (p.cls) { - case float_class_dnan: - return float64_default_nan(s); case float_class_msnan: p.frac >>=3D float64_params.frac_shift; return float64_maybe_silence_nan(float64_pack_raw(p), s); @@ -566,7 +559,7 @@ static FloatParts return_nan(FloatParts a, float_status= *s) /* fall through */ case float_class_qnan: if (s->default_nan_mode) { - a.cls =3D float_class_dnan; + return parts_default_nan(s); } break; =20 @@ -583,7 +576,7 @@ static FloatParts pick_nan(FloatParts a, FloatParts b, = float_status *s) } =20 if (s->default_nan_mode) { - a.cls =3D float_class_dnan; + return parts_default_nan(s); } else { if (pickNaN(is_qnan(a.cls), is_snan(a.cls), is_qnan(b.cls), is_snan(b.cls), @@ -614,8 +607,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatPa= rts b, FloatParts c, /* Note that this check is after pickNaNMulAdd so that function * has an opportunity to set the Invalid flag. */ - a.cls =3D float_class_dnan; - return a; + which =3D 3; } =20 switch (which) { @@ -628,8 +620,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatPa= rts b, FloatParts c, a =3D c; break; case 3: - a.cls =3D float_class_dnan; - return a; + return parts_default_nan(s); default: g_assert_not_reached(); } @@ -682,7 +673,7 @@ static FloatParts addsub_floats(FloatParts a, FloatPart= s b, bool subtract, if (a.cls =3D=3D float_class_inf) { if (b.cls =3D=3D float_class_inf) { float_raise(float_flag_invalid, s); - a.cls =3D float_class_dnan; + return parts_default_nan(s); } return a; } @@ -828,9 +819,7 @@ static FloatParts mul_floats(FloatParts a, FloatParts b= , float_status *s) if ((a.cls =3D=3D float_class_inf && b.cls =3D=3D float_class_zero) || (a.cls =3D=3D float_class_zero && b.cls =3D=3D float_class_inf)) { s->float_exception_flags |=3D float_flag_invalid; - a.cls =3D float_class_dnan; - a.sign =3D sign; - return a; + return parts_default_nan(s); } /* Multiply by 0 or Inf */ if (a.cls =3D=3D float_class_inf || a.cls =3D=3D float_class_zero) { @@ -908,8 +897,7 @@ static FloatParts muladd_floats(FloatParts a, FloatPart= s b, FloatParts c, =20 if (inf_zero) { s->float_exception_flags |=3D float_flag_invalid; - a.cls =3D float_class_dnan; - return a; + return parts_default_nan(s); } =20 if (flags & float_muladd_negate_c) { @@ -933,12 +921,12 @@ static FloatParts muladd_floats(FloatParts a, FloatPa= rts b, FloatParts c, if (c.cls =3D=3D float_class_inf) { if (p_class =3D=3D float_class_inf && p_sign !=3D c.sign) { s->float_exception_flags |=3D float_flag_invalid; - a.cls =3D float_class_dnan; + return parts_default_nan(s); } else { a.cls =3D float_class_inf; a.sign =3D c.sign ^ sign_flip; + return a; } - return a; } =20 if (p_class =3D=3D float_class_inf) { @@ -1148,8 +1136,7 @@ static FloatParts div_floats(FloatParts a, FloatParts= b, float_status *s) && (a.cls =3D=3D float_class_inf || a.cls =3D=3D float_class_zero)) { s->float_exception_flags |=3D float_flag_invalid; - a.cls =3D float_class_dnan; - return a; + return parts_default_nan(s); } /* Inf / x or 0 / x */ if (a.cls =3D=3D float_class_inf || a.cls =3D=3D float_class_zero) { @@ -1347,7 +1334,6 @@ static int64_t round_to_int_and_pack(FloatParts in, i= nt rmode, switch (p.cls) { case float_class_snan: case float_class_qnan: - case float_class_dnan: case float_class_msnan: s->float_exception_flags =3D orig_flags | float_flag_invalid; return max; @@ -1439,7 +1425,6 @@ static uint64_t round_to_uint_and_pack(FloatParts in,= int rmode, uint64_t max, switch (p.cls) { case float_class_snan: case float_class_qnan: - case float_class_dnan: case float_class_msnan: s->float_exception_flags =3D orig_flags | float_flag_invalid; return max; @@ -1940,8 +1925,7 @@ static FloatParts sqrt_float(FloatParts a, float_stat= us *s, const FloatFmt *p) } if (a.sign) { s->float_exception_flags |=3D float_flag_invalid; - a.cls =3D float_class_dnan; - return a; + return parts_default_nan(s); } if (a.cls =3D=3D float_class_inf) { return a; /* sqrt(+inf) =3D +inf */ --=20 2.17.0 From nobody Wed Oct 29 23:02:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id y2-v6sm14512457pgp.92.2018.05.14.15.12.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 May 2018 15:12:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8MMEeLkuowEda0GJxT77HlfYSnWSRj+TbO/ixCfRrxo=; b=f/BxW1sI2h8tZovSH6t6/MdQx41zMtZEhl38usijRWX+a/T1t3tYghVn87cP34LRnS 9S412Lk0squzBLDhH3bKr82sioUgdqHXCDd9DV7VQEr5pIIpMjBTaRHX+KwaxlZHZavl 1KJRvqECaHQGRtlBh5AB3ysRC2UWO4Tl/WTg4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8MMEeLkuowEda0GJxT77HlfYSnWSRj+TbO/ixCfRrxo=; b=CE0n3qxewflLTQlxBr++OXqnTNBnyMK8zHrauaMvF9squmbU2HhJ2/4xbxPn72fjmh 3lWTuowuS0MsM75kfmLFBvE5zq9mFx72KI8g8I50Ijqn14fzScUAI6Kvu/GdSNBVmIwD w0Q4lXlXzkfmr0sZ7uWkWH7MeEaNqRaiLqhTV0YDF5EBCSuV2tPSlF1/4hQxctgXVYUS dk0UHq8d4yRwUvjHvsnyYelWTLkQ5DTLbaxIPaFRfQV9wkVQ2//mgertx+l4dGlMUwP7 a+XYgQMlw4NYPRDhXmfkIFC1NRSMpjOfpYvSL1xuh1hBhMl8EBGGTUF/qCBF/hn2LVkH FkLA== X-Gm-Message-State: ALKqPwclwHctN4C3OE/N2JCCmRX0oldZXzAAUAgDXzvKFJzVky8ntmMQ i5hI7bBrquYkxWUTDUlW34lh7xh5ObI= X-Google-Smtp-Source: AB8JxZq1Q7IPAw/48dihZsEJnx1v6ZBD1BWYCtQsMXODFxodUTDiUp6t79pVMMxhVjUsO7GAfrUWtQ== X-Received: by 2002:a17:902:8c81:: with SMTP id t1-v6mr11370851plo.310.1526335953029; Mon, 14 May 2018 15:12:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 May 2018 15:11:59 -0700 Message-Id: <20180514221219.7091-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180514221219.7091-1-richard.henderson@linaro.org> References: <20180514221219.7091-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH v5 08/28] fpu/softfloat: Replace float_class_msnan with parts_silence_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" With a canonical representation of NaNs, we can silence an SNaN immediately rather than delay until the final format is known. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Tested-by: Alex Benn=C3=A9e --- fpu/softfloat-specialize.h | 23 ++++++++++++++++++++++ fpu/softfloat.c | 40 ++++++++++---------------------------- 2 files changed, 33 insertions(+), 30 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 0d3d81a52b..571d1df378 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -138,6 +138,29 @@ static FloatParts parts_default_nan(float_status *stat= us) }; } =20 +/*------------------------------------------------------------------------= ---- +| Returns a quiet NaN from a signalling NaN for the deconstructed +| floating-point parts. +*-------------------------------------------------------------------------= ---*/ + +static FloatParts parts_silence_nan(FloatParts a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#elif defined(TARGET_HPPA) + a.frac &=3D ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); + a.frac |=3D 1ULL << (DECOMPOSED_BINARY_POINT - 2); +#else + if (status->snan_bit_is_one) { + return parts_default_nan(status); + } else { + a.frac |=3D 1ULL << (DECOMPOSED_BINARY_POINT - 1); + } +#endif + a.cls =3D float_class_qnan; + return a; +} + /*------------------------------------------------------------------------= ---- | The pattern for a default generated half-precision NaN. *-------------------------------------------------------------------------= ---*/ diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 51780b718f..41253c6749 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -188,7 +188,6 @@ typedef enum __attribute__ ((__packed__)) { float_class_inf, float_class_qnan, /* all NaNs from here */ float_class_snan, - float_class_msnan, /* maybe silenced */ } FloatClass; =20 /* @@ -492,14 +491,7 @@ static FloatParts float16_unpack_canonical(float16 f, = float_status *s) =20 static float16 float16_round_pack_canonical(FloatParts p, float_status *s) { - switch (p.cls) { - case float_class_msnan: - p.frac >>=3D float16_params.frac_shift; - return float16_maybe_silence_nan(float16_pack_raw(p), s); - default: - p =3D round_canonical(p, s, &float16_params); - return float16_pack_raw(p); - } + return float16_pack_raw(round_canonical(p, s, &float16_params)); } =20 static FloatParts float32_unpack_canonical(float32 f, float_status *s) @@ -509,14 +501,7 @@ static FloatParts float32_unpack_canonical(float32 f, = float_status *s) =20 static float32 float32_round_pack_canonical(FloatParts p, float_status *s) { - switch (p.cls) { - case float_class_msnan: - p.frac >>=3D float32_params.frac_shift; - return float32_maybe_silence_nan(float32_pack_raw(p), s); - default: - p =3D round_canonical(p, s, &float32_params); - return float32_pack_raw(p); - } + return float32_pack_raw(round_canonical(p, s, &float32_params)); } =20 static FloatParts float64_unpack_canonical(float64 f, float_status *s) @@ -526,14 +511,7 @@ static FloatParts float64_unpack_canonical(float64 f, = float_status *s) =20 static float64 float64_round_pack_canonical(FloatParts p, float_status *s) { - switch (p.cls) { - case float_class_msnan: - p.frac >>=3D float64_params.frac_shift; - return float64_maybe_silence_nan(float64_pack_raw(p), s); - default: - p =3D round_canonical(p, s, &float64_params); - return float64_pack_raw(p); - } + return float64_pack_raw(round_canonical(p, s, &float64_params)); } =20 /* Simple helpers for checking if what NaN we have */ @@ -555,7 +533,7 @@ static FloatParts return_nan(FloatParts a, float_status= *s) switch (a.cls) { case float_class_snan: s->float_exception_flags |=3D float_flag_invalid; - a.cls =3D float_class_msnan; + a =3D parts_silence_nan(a, s); /* fall through */ case float_class_qnan: if (s->default_nan_mode) { @@ -584,7 +562,9 @@ static FloatParts pick_nan(FloatParts a, FloatParts b, = float_status *s) (a.frac =3D=3D b.frac && a.sign < b.sign))) { a =3D b; } - a.cls =3D float_class_msnan; + if (is_snan(a.cls)) { + return parts_silence_nan(a, s); + } } return a; } @@ -624,8 +604,10 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatP= arts b, FloatParts c, default: g_assert_not_reached(); } - a.cls =3D float_class_msnan; =20 + if (is_snan(a.cls)) { + return parts_silence_nan(a, s); + } return a; } =20 @@ -1334,7 +1316,6 @@ static int64_t round_to_int_and_pack(FloatParts in, i= nt rmode, switch (p.cls) { case float_class_snan: case float_class_qnan: - case float_class_msnan: s->float_exception_flags =3D orig_flags | float_flag_invalid; return max; case float_class_inf: @@ -1425,7 +1406,6 @@ static uint64_t round_to_uint_and_pack(FloatParts in,= int rmode, uint64_t max, switch (p.cls) { case float_class_snan: case float_class_qnan: - case float_class_msnan: s->float_exception_flags =3D orig_flags | float_flag_invalid; return max; case float_class_inf: --=20 2.17.0 From nobody Wed Oct 29 23:02:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v5 09/28] target/arm: Use floatX_silence_nan when we have already checked for SNaN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Tested-by: Alex Benn=C3=A9e --- target/arm/helper-a64.c | 6 +++--- target/arm/helper.c | 12 ++++++------ 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 4f8034c513..6f0eb83661 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -376,7 +376,7 @@ float16 HELPER(frecpx_f16)(float16 a, void *fpstp) float16 nan =3D a; if (float16_is_signaling_nan(a, fpst)) { float_raise(float_flag_invalid, fpst); - nan =3D float16_maybe_silence_nan(a, fpst); + nan =3D float16_silence_nan(a, fpst); } if (fpst->default_nan_mode) { nan =3D float16_default_nan(fpst); @@ -405,7 +405,7 @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp) float32 nan =3D a; if (float32_is_signaling_nan(a, fpst)) { float_raise(float_flag_invalid, fpst); - nan =3D float32_maybe_silence_nan(a, fpst); + nan =3D float32_silence_nan(a, fpst); } if (fpst->default_nan_mode) { nan =3D float32_default_nan(fpst); @@ -434,7 +434,7 @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp) float64 nan =3D a; if (float64_is_signaling_nan(a, fpst)) { float_raise(float_flag_invalid, fpst); - nan =3D float64_maybe_silence_nan(a, fpst); + nan =3D float64_silence_nan(a, fpst); } if (fpst->default_nan_mode) { nan =3D float64_default_nan(fpst); diff --git a/target/arm/helper.c b/target/arm/helper.c index c6fd7f9479..3df5cf30e4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11739,7 +11739,7 @@ float16 HELPER(recpe_f16)(float16 input, void *fpst= p) float16 nan =3D f16; if (float16_is_signaling_nan(f16, fpst)) { float_raise(float_flag_invalid, fpst); - nan =3D float16_maybe_silence_nan(f16, fpst); + nan =3D float16_silence_nan(f16, fpst); } if (fpst->default_nan_mode) { nan =3D float16_default_nan(fpst); @@ -11787,7 +11787,7 @@ float32 HELPER(recpe_f32)(float32 input, void *fpst= p) float32 nan =3D f32; if (float32_is_signaling_nan(f32, fpst)) { float_raise(float_flag_invalid, fpst); - nan =3D float32_maybe_silence_nan(f32, fpst); + nan =3D float32_silence_nan(f32, fpst); } if (fpst->default_nan_mode) { nan =3D float32_default_nan(fpst); @@ -11835,7 +11835,7 @@ float64 HELPER(recpe_f64)(float64 input, void *fpst= p) float64 nan =3D f64; if (float64_is_signaling_nan(f64, fpst)) { float_raise(float_flag_invalid, fpst); - nan =3D float64_maybe_silence_nan(f64, fpst); + nan =3D float64_silence_nan(f64, fpst); } if (fpst->default_nan_mode) { nan =3D float64_default_nan(fpst); @@ -11934,7 +11934,7 @@ float16 HELPER(rsqrte_f16)(float16 input, void *fps= tp) float16 nan =3D f16; if (float16_is_signaling_nan(f16, s)) { float_raise(float_flag_invalid, s); - nan =3D float16_maybe_silence_nan(f16, s); + nan =3D float16_silence_nan(f16, s); } if (s->default_nan_mode) { nan =3D float16_default_nan(s); @@ -11978,7 +11978,7 @@ float32 HELPER(rsqrte_f32)(float32 input, void *fps= tp) float32 nan =3D f32; if (float32_is_signaling_nan(f32, s)) { float_raise(float_flag_invalid, s); - nan =3D float32_maybe_silence_nan(f32, s); + nan =3D float32_silence_nan(f32, s); } if (s->default_nan_mode) { nan =3D float32_default_nan(s); @@ -12021,7 +12021,7 @@ float64 HELPER(rsqrte_f64)(float64 input, void *fps= tp) float64 nan =3D f64; if (float64_is_signaling_nan(f64, s)) { float_raise(float_flag_invalid, s); - nan =3D float64_maybe_silence_nan(f64, s); + nan =3D float64_silence_nan(f64, s); } if (s->default_nan_mode) { nan =3D float64_default_nan(s); --=20 2.17.0 From nobody Wed Oct 29 23:02:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id y2-v6sm14512457pgp.92.2018.05.14.15.12.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 May 2018 15:12:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kgFsjCcIc/1z2LVhH2EQj9VB0xsd4Fb5MP2a+hsVHBk=; b=XyULRLhX/CrL0OnMsZI9FmenjNZs6XzAGCkDXnoOecZPWKkehhZNBqe/3y6zk09nLu 1lIxSLLmqn5Nl4GfjUAwDZ4HfNhFFzLoqrvGHhyjFQP/9z2EBmuRCgf0cftiznRJmHo3 10nEe+xrBLnNTNR0NMeEQDEVRlcl9FnKzZU48= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kgFsjCcIc/1z2LVhH2EQj9VB0xsd4Fb5MP2a+hsVHBk=; b=PyO7Os7qGcQxT2o/uVpAqq3Zty0kBXIRi4LIiq39Tof7Mp8Nu3H5ws+uMq8KaUIHYc Jzsc02eWDZoKKuzvlVyQNOk4SCnAqhg6Y5qYfK+sewgDDx9DeZDUcRo665N/1c/rtC0K 3W9QgCeIOeeGYE3K5oEYVNIFj6Z5y/GsJ+pWm9e/NUFwWjBo0FPyD6kKpV/ah/cunKQb uAElE6oh0nyzvQdZRFN7JZYCx8T8YClarGx4KraO9rHBKWZGUEdeMXHtr9UkZbHgRali ZC71NE6e43KbeRFzt3W9ykxcfzmHU/ZesJcN2sJAFD9/pSrtkyPDFwjJkldOJY1R5NOU 2iyw== X-Gm-Message-State: ALKqPwc2AbA1sbsNA1Y3+ndtQe5+v26Y+xcNycFEKVXCjdwhsapthvHc 15TojAKcnt8M9zCxXIjsmNtRBx3Ifag= X-Google-Smtp-Source: AB8JxZrXSkmW9o5RbeFYU6piehijMombSrRvf/1d0jO13vOG4REsz1INiXAmdpIoI7OuAmgH+CJsZQ== X-Received: by 2002:a63:6f4c:: with SMTP id k73-v6mr2312903pgc.303.1526335955493; Mon, 14 May 2018 15:12:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 May 2018 15:12:01 -0700 Message-Id: <20180514221219.7091-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180514221219.7091-1-richard.henderson@linaro.org> References: <20180514221219.7091-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v5 10/28] target/arm: convert conversion helpers to fpst/ahp_flag X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Alex Benn=C3=A9e Instead of passing env and leaving it up to the helper to get the right fpstatus we pass it explicitly. There was already a get_fpstatus helper for neon for the 32 bit code. We also add an get_ahp_flag() for passing the state of the alternative FP16 format flag. This leaves scope for later tracking the AHP state in translation flags. Signed-off-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- v4 - remove neon_fcvt_*; they are now identical to vfp_fcvt_*. - add flags to vfp_fcvt_* helper decls. - add some missing tcg_temp_free_*. v5 - always use get_fpstatus_ptr(false) for FZ, since FZ16 is supposed to be supressed. --- target/arm/helper.h | 10 +++--- target/arm/translate.h | 12 +++++++ target/arm/helper.c | 56 +++++------------------------ target/arm/translate-a64.c | 38 ++++++++++++++++---- target/arm/translate.c | 74 +++++++++++++++++++++++++++++--------- 5 files changed, 113 insertions(+), 77 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index ce89968b2d..047f3bc1ca 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -187,12 +187,10 @@ DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr) DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr) DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env) =20 -DEF_HELPER_2(vfp_fcvt_f16_to_f32, f32, i32, env) -DEF_HELPER_2(vfp_fcvt_f32_to_f16, i32, f32, env) -DEF_HELPER_2(neon_fcvt_f16_to_f32, f32, i32, env) -DEF_HELPER_2(neon_fcvt_f32_to_f16, i32, f32, env) -DEF_HELPER_FLAGS_2(vfp_fcvt_f16_to_f64, TCG_CALL_NO_RWG, f64, i32, env) -DEF_HELPER_FLAGS_2(vfp_fcvt_f64_to_f16, TCG_CALL_NO_RWG, i32, f64, env) +DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f32, TCG_CALL_NO_RWG, f32, f16, ptr, i3= 2) +DEF_HELPER_FLAGS_3(vfp_fcvt_f32_to_f16, TCG_CALL_NO_RWG, f16, f32, ptr, i3= 2) +DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f64, TCG_CALL_NO_RWG, f64, f16, ptr, i3= 2) +DEF_HELPER_FLAGS_3(vfp_fcvt_f64_to_f16, TCG_CALL_NO_RWG, f16, f64, ptr, i3= 2) =20 DEF_HELPER_4(vfp_muladdd, f64, f64, f64, f64, ptr) DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, ptr) diff --git a/target/arm/translate.h b/target/arm/translate.h index 37a1bba056..45f04244be 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -177,4 +177,16 @@ void arm_free_cc(DisasCompare *cmp); void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); void arm_gen_test_cc(int cc, TCGLabel *label); =20 +/* Return state of Alternate Half-precision flag, caller frees result */ +static inline TCGv_i32 get_ahp_flag(void) +{ + TCGv_i32 ret =3D tcg_temp_new_i32(); + + tcg_gen_ld_i32(ret, cpu_env, + offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR])); + tcg_gen_extract_i32(ret, ret, 26, 1); + + return ret; +} + #endif /* TARGET_ARM_TRANSLATE_H */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 3df5cf30e4..a1c1dc5bbe 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11540,64 +11540,24 @@ uint32_t HELPER(set_neon_rmode)(uint32_t rmode, C= PUARMState *env) } =20 /* Half precision conversions. */ -static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_stat= us *s) +float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_m= ode) { - int ieee =3D (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) =3D=3D 0; - float32 r =3D float16_to_float32(make_float16(a), ieee, s); - if (ieee) { - return float32_maybe_silence_nan(r, s); - } - return r; + return float16_to_float32(a, !ahp_mode, fpstp); } =20 -static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_stat= us *s) +float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_m= ode) { - int ieee =3D (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) =3D=3D 0; - float16 r =3D float32_to_float16(a, ieee, s); - if (ieee) { - r =3D float16_maybe_silence_nan(r, s); - } - return float16_val(r); + return float32_to_float16(a, !ahp_mode, fpstp); } =20 -float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) +float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_m= ode) { - return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status); + return float16_to_float64(a, !ahp_mode, fpstp); } =20 -uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env) +float16 HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_m= ode) { - return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status); -} - -float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) -{ - return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status); -} - -uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env) -{ - return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status); -} - -float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env) -{ - int ieee =3D (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) =3D=3D 0; - float64 r =3D float16_to_float64(make_float16(a), ieee, &env->vfp.fp_s= tatus); - if (ieee) { - return float64_maybe_silence_nan(r, &env->vfp.fp_status); - } - return r; -} - -uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env) -{ - int ieee =3D (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) =3D=3D 0; - float16 r =3D float64_to_float16(a, ieee, &env->vfp.fp_status); - if (ieee) { - r =3D float16_maybe_silence_nan(r, &env->vfp.fp_status); - } - return float16_val(r); + return float64_to_float16(a, !ahp_mode, fpstp); } =20 #define float32_two make_float32(0x40000000) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a0b0c43d12..4db18031bb 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5147,10 +5147,15 @@ static void handle_fp_fcvt(DisasContext *s, int opc= ode, } else { /* Single to half */ TCGv_i32 tcg_rd =3D tcg_temp_new_i32(); - gen_helper_vfp_fcvt_f32_to_f16(tcg_rd, tcg_rn, cpu_env); + TCGv_i32 ahp =3D get_ahp_flag(); + TCGv_ptr fpst =3D get_fpstatus_ptr(false); + + gen_helper_vfp_fcvt_f32_to_f16(tcg_rd, tcg_rn, fpst, ahp); /* write_fp_sreg is OK here because top half of tcg_rd is zero= */ write_fp_sreg(s, rd, tcg_rd); tcg_temp_free_i32(tcg_rd); + tcg_temp_free_i32(ahp); + tcg_temp_free_ptr(fpst); } tcg_temp_free_i32(tcg_rn); break; @@ -5163,9 +5168,13 @@ static void handle_fp_fcvt(DisasContext *s, int opco= de, /* Double to single */ gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, cpu_env); } else { + TCGv_ptr fpst =3D get_fpstatus_ptr(false); + TCGv_i32 ahp =3D get_ahp_flag(); /* Double to half */ - gen_helper_vfp_fcvt_f64_to_f16(tcg_rd, tcg_rn, cpu_env); + gen_helper_vfp_fcvt_f64_to_f16(tcg_rd, tcg_rn, fpst, ahp); /* write_fp_sreg is OK here because top half of tcg_rd is zero= */ + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(ahp); } write_fp_sreg(s, rd, tcg_rd); tcg_temp_free_i32(tcg_rd); @@ -5175,17 +5184,21 @@ static void handle_fp_fcvt(DisasContext *s, int opc= ode, case 0x3: { TCGv_i32 tcg_rn =3D read_fp_sreg(s, rn); + TCGv_ptr tcg_fpst =3D get_fpstatus_ptr(false); + TCGv_i32 tcg_ahp =3D get_ahp_flag(); tcg_gen_ext16u_i32(tcg_rn, tcg_rn); if (dtype =3D=3D 0) { /* Half to single */ TCGv_i32 tcg_rd =3D tcg_temp_new_i32(); - gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, cpu_env); + gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, tcg_fpst, tcg_a= hp); write_fp_sreg(s, rd, tcg_rd); + tcg_temp_free_ptr(tcg_fpst); + tcg_temp_free_i32(tcg_ahp); tcg_temp_free_i32(tcg_rd); } else { /* Half to double */ TCGv_i64 tcg_rd =3D tcg_temp_new_i64(); - gen_helper_vfp_fcvt_f16_to_f64(tcg_rd, tcg_rn, cpu_env); + gen_helper_vfp_fcvt_f16_to_f64(tcg_rd, tcg_rn, tcg_fpst, tcg_a= hp); write_fp_dreg(s, rd, tcg_rd); tcg_temp_free_i64(tcg_rd); } @@ -9053,12 +9066,17 @@ static void handle_2misc_narrow(DisasContext *s, bo= ol scalar, } else { TCGv_i32 tcg_lo =3D tcg_temp_new_i32(); TCGv_i32 tcg_hi =3D tcg_temp_new_i32(); + TCGv_ptr fpst =3D get_fpstatus_ptr(true); + TCGv_i32 ahp =3D get_ahp_flag(); + tcg_gen_extr_i64_i32(tcg_lo, tcg_hi, tcg_op); - gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, cpu_env); - gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, cpu_env); + gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, fpst, ahp); + gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, fpst, ahp); tcg_gen_deposit_i32(tcg_res[pass], tcg_lo, tcg_hi, 16, 16); tcg_temp_free_i32(tcg_lo); tcg_temp_free_i32(tcg_hi); + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(ahp); } break; case 0x56: /* FCVTXN, FCVTXN2 */ @@ -11532,18 +11550,24 @@ static void handle_2misc_widening(DisasContext *s= , int opcode, bool is_q, /* 16 -> 32 bit fp conversion */ int srcelt =3D is_q ? 4 : 0; TCGv_i32 tcg_res[4]; + TCGv_ptr fpst =3D get_fpstatus_ptr(true); + TCGv_i32 ahp =3D get_ahp_flag(); + =20 for (pass =3D 0; pass < 4; pass++) { tcg_res[pass] =3D tcg_temp_new_i32(); =20 read_vec_element_i32(s, tcg_res[pass], rn, srcelt + pass, MO_1= 6); gen_helper_vfp_fcvt_f16_to_f32(tcg_res[pass], tcg_res[pass], - cpu_env); + fpst, ahp); } for (pass =3D 0; pass < 4; pass++) { write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32); tcg_temp_free_i32(tcg_res[pass]); } + + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(ahp); } } =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index 731cf327a1..5ba59e0188 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3824,38 +3824,56 @@ static int disas_vfp_insn(DisasContext *s, uint32_t= insn) gen_vfp_sqrt(dp); break; case 4: /* vcvtb.f32.f16, vcvtb.f64.f16 */ + { + TCGv_ptr fpst =3D get_fpstatus_ptr(false); + TCGv_i32 ahp_mode =3D get_ahp_flag(); tmp =3D gen_vfp_mrs(); tcg_gen_ext16u_i32(tmp, tmp); if (dp) { gen_helper_vfp_fcvt_f16_to_f64(cpu_F0d, tmp, - cpu_env); + fpst, ahp_mode); } else { gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, - cpu_env); + fpst, ahp_mode); } + tcg_temp_free_i32(ahp_mode); + tcg_temp_free_ptr(fpst); tcg_temp_free_i32(tmp); break; + } case 5: /* vcvtt.f32.f16, vcvtt.f64.f16 */ + { + TCGv_ptr fpst =3D get_fpstatus_ptr(false); + TCGv_i32 ahp =3D get_ahp_flag(); tmp =3D gen_vfp_mrs(); tcg_gen_shri_i32(tmp, tmp, 16); if (dp) { gen_helper_vfp_fcvt_f16_to_f64(cpu_F0d, tmp, - cpu_env); + fpst, ahp); } else { gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, - cpu_env); + fpst, ahp); } tcg_temp_free_i32(tmp); + tcg_temp_free_i32(ahp); + tcg_temp_free_ptr(fpst); break; + } case 6: /* vcvtb.f16.f32, vcvtb.f16.f64 */ + { + TCGv_ptr fpst =3D get_fpstatus_ptr(false); + TCGv_i32 ahp =3D get_ahp_flag(); tmp =3D tcg_temp_new_i32(); + if (dp) { gen_helper_vfp_fcvt_f64_to_f16(tmp, cpu_F0d, - cpu_env); + fpst, ahp); } else { gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, - cpu_env); + fpst, ahp); } + tcg_temp_free_i32(ahp); + tcg_temp_free_ptr(fpst); gen_mov_F0_vreg(0, rd); tmp2 =3D gen_vfp_mrs(); tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000); @@ -3863,15 +3881,21 @@ static int disas_vfp_insn(DisasContext *s, uint32_t= insn) tcg_temp_free_i32(tmp2); gen_vfp_msr(tmp); break; + } case 7: /* vcvtt.f16.f32, vcvtt.f16.f64 */ + { + TCGv_ptr fpst =3D get_fpstatus_ptr(true); + TCGv_i32 ahp =3D get_ahp_flag(); tmp =3D tcg_temp_new_i32(); if (dp) { gen_helper_vfp_fcvt_f64_to_f16(tmp, cpu_F0d, - cpu_env); + fpst, ahp); } else { gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, - cpu_env); + fpst, ahp); } + tcg_temp_free_i32(ahp); + tcg_temp_free_ptr(fpst); tcg_gen_shli_i32(tmp, tmp, 16); gen_mov_F0_vreg(0, rd); tmp2 =3D gen_vfp_mrs(); @@ -3880,6 +3904,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) tcg_temp_free_i32(tmp2); gen_vfp_msr(tmp); break; + } case 8: /* cmp */ gen_vfp_cmp(dp); break; @@ -7222,53 +7247,70 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) } break; case NEON_2RM_VCVT_F16_F32: + { + TCGv_ptr fpst; + TCGv_i32 ahp; + if (!arm_dc_feature(s, ARM_FEATURE_VFP_FP16) || q || (rm & 1)) { return 1; } tmp =3D tcg_temp_new_i32(); tmp2 =3D tcg_temp_new_i32(); + fpst =3D get_fpstatus_ptr(true); + ahp =3D get_ahp_flag(); tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 0= )); - gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env); + gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, fpst, ahp= ); tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 1= )); - gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env= ); + gen_helper_vfp_fcvt_f32_to_f16(tmp2, cpu_F0s, fpst, ah= p); tcg_gen_shli_i32(tmp2, tmp2, 16); tcg_gen_or_i32(tmp2, tmp2, tmp); tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 2= )); - gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env); + gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, fpst, ahp= ); tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 3= )); neon_store_reg(rd, 0, tmp2); tmp2 =3D tcg_temp_new_i32(); - gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env= ); + gen_helper_vfp_fcvt_f32_to_f16(tmp2, cpu_F0s, fpst, ah= p); tcg_gen_shli_i32(tmp2, tmp2, 16); tcg_gen_or_i32(tmp2, tmp2, tmp); neon_store_reg(rd, 1, tmp2); tcg_temp_free_i32(tmp); + tcg_temp_free_i32(ahp); + tcg_temp_free_ptr(fpst); break; + } case NEON_2RM_VCVT_F32_F16: + { + TCGv_ptr fpst; + TCGv_i32 ahp; if (!arm_dc_feature(s, ARM_FEATURE_VFP_FP16) || q || (rd & 1)) { return 1; } + fpst =3D get_fpstatus_ptr(true); + ahp =3D get_ahp_flag(); tmp3 =3D tcg_temp_new_i32(); tmp =3D neon_load_reg(rm, 0); tmp2 =3D neon_load_reg(rm, 1); tcg_gen_ext16u_i32(tmp3, tmp); - gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env= ); + gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, fpst, ah= p); tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 0= )); tcg_gen_shri_i32(tmp3, tmp, 16); - gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env= ); + gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, fpst, ah= p); tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 1= )); tcg_temp_free_i32(tmp); tcg_gen_ext16u_i32(tmp3, tmp2); - gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env= ); + gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, fpst, ah= p); tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 2= )); tcg_gen_shri_i32(tmp3, tmp2, 16); - gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env= ); + gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, fpst, ah= p); tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 3= )); tcg_temp_free_i32(tmp2); tcg_temp_free_i32(tmp3); + tcg_temp_free_i32(ahp); + tcg_temp_free_ptr(fpst); break; + } case NEON_2RM_AESE: case NEON_2RM_AESMC: if (!arm_dc_feature(s, ARM_FEATURE_V8_AES) || ((rm | rd) & 1)) { --=20 2.17.0 From nobody Wed Oct 29 23:02:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526336498070951.5488432364457; Mon, 14 May 2018 15:21:38 -0700 (PDT) Received: from localhost ([::1]:49931 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILqb-0006on-8X for importer@patchew.org; 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X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v5 11/28] target/arm: squash FZ16 behaviour for conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Alex Benn=C3=A9e The ARM ARM specifies FZ16 is suppressed for conversions. Rather than pushing this logic into the softfloat code we can simply save the FZ state and temporarily disable it for the softfloat call. Reviewed-by: Peter Maydell Signed-off-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- v4 - float16_to_floatX squished the wrong softfloat bit for FZ16; need to adjust input denormals in this case. --- target/arm/helper.c | 40 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 36 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a1c1dc5bbe..e05c7230d4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11542,22 +11542,54 @@ uint32_t HELPER(set_neon_rmode)(uint32_t rmode, C= PUARMState *env) /* Half precision conversions. */ float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_m= ode) { - return float16_to_float32(a, !ahp_mode, fpstp); + /* Squash FZ16 to 0 for the duration of conversion. In this case, + * it would affect flushing input denormals. + */ + float_status *fpst =3D fpstp; + flag save =3D get_flush_inputs_to_zero(fpst); + set_flush_inputs_to_zero(false, fpst); + float32 r =3D float16_to_float32(a, !ahp_mode, fpst); + set_flush_inputs_to_zero(save, fpst); + return r; } =20 float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_m= ode) { - return float32_to_float16(a, !ahp_mode, fpstp); + /* Squash FZ16 to 0 for the duration of conversion. In this case, + * it would affect flushing output denormals. + */ + float_status *fpst =3D fpstp; + flag save =3D get_flush_to_zero(fpst); + set_flush_to_zero(false, fpst); + float16 r =3D float32_to_float16(a, !ahp_mode, fpst); + set_flush_to_zero(save, fpst); + return r; } =20 float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_m= ode) { - return float16_to_float64(a, !ahp_mode, fpstp); + /* Squash FZ16 to 0 for the duration of conversion. In this case, + * it would affect flushing input denormals. + */ + float_status *fpst =3D fpstp; + flag save =3D get_flush_inputs_to_zero(fpst); + set_flush_inputs_to_zero(false, fpst); + float64 r =3D float16_to_float64(a, !ahp_mode, fpst); + set_flush_inputs_to_zero(save, fpst); + return r; } =20 float16 HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_m= ode) { - return float64_to_float16(a, !ahp_mode, fpstp); + /* Squash FZ16 to 0 for the duration of conversion. In this case, + * it would affect flushing output denormals. + */ + float_status *fpst =3D fpstp; + flag save =3D get_flush_to_zero(fpst); + set_flush_to_zero(false, fpst); + float16 r =3D float64_to_float16(a, !ahp_mode, fpst); + set_flush_to_zero(save, fpst); + return r; } =20 #define float32_two make_float32(0x40000000) --=20 2.17.0 From nobody Wed Oct 29 23:02:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526336482574397.54886041079396; Mon, 14 May 2018 15:21:22 -0700 (PDT) Received: from localhost ([::1]:49930 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILqL-0006Ya-OY for importer@patchew.org; Mon, 14 May 2018 18:21:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52491) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILhw-0007zT-J7 for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fILhv-0007pc-MM for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:40 -0400 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:44297) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fILhv-0007o7-HU for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:39 -0400 Received: by mail-pg0-x241.google.com with SMTP id x145-v6so6057473pgx.11 for ; Mon, 14 May 2018 15:12:39 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id y2-v6sm14512457pgp.92.2018.05.14.15.12.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 May 2018 15:12:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3p1uYPjT+Qh7BPWBI2DONjm1ihiuZReCWqTClVy4o+c=; b=MftfZeHnFRwIvAEpXl6i8nx22jPVEbWx/bZgX4etNf8Di/jK2g4Hcq3qtJHBwEi7RO DVu1Io1OMZlFda4Z/dgzNtiM3gfvAEPbPKBZ4+XBRi8CIv8hPjVpt4jGpqVbueOM7ma8 qiRWSUToNAVBgj9PBPsXJ3NdYTfAQfPSFKkm4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3p1uYPjT+Qh7BPWBI2DONjm1ihiuZReCWqTClVy4o+c=; b=d2Uu5rwY2z7UUFLQZ7RtkZFjRKpB/TPf1fuiLsRAaT6Z8rBm4QKvaPrNs1zu0MncWS gz8FF8gCVo+JuQJyk5iZyRB7rNKq3hgeli0+djWbPUWWQQZ5aFveIiZQgLmrk8+eUX9Y XwmtY3BwDGNhVDkYOqdb3h0KCH8xP64l7PkI2htzBRbmQXRA5NrkSSMDGu35Etd6LFUb M7tpI6Uqjh8aPLzYVBYBMtTQ7AfAteO2uyg1XGZzR7SUIooP/FpYCEKWxM0f8dMCUNVp D/3gDKMA5AaR2ecJ46RqYk4mYLg29/irioTypjSPFCsIVoCtKGzM+RGziQ/+sxkyeiRC FSiQ== X-Gm-Message-State: ALKqPweyUMcYbf6mtxDRu36xFoVN40dNhE6BhLDbCvlhhiFniY7+a2OB hD0/Es11Xv9BQ032zP+GVjZEkRMgo9Q= X-Google-Smtp-Source: AB8JxZr/RJqPg+pbbM/BkOvgyrJGr8bLn46Snb+8JqJbFggtuSk+SWtfd2lk88nZTIcun4FsPBcSag== X-Received: by 2002:a63:5f11:: with SMTP id t17-v6mr8331778pgb.94.1526335958243; Mon, 14 May 2018 15:12:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 May 2018 15:12:03 -0700 Message-Id: <20180514221219.7091-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180514221219.7091-1-richard.henderson@linaro.org> References: <20180514221219.7091-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v5 12/28] target/arm: Remove floatX_maybe_silence_nan from conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is now handled properly by the generic softfloat code. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Tested-by: Alex Benn=C3=A9e --- target/arm/helper-a64.c | 1 - target/arm/helper.c | 12 ++---------- 2 files changed, 2 insertions(+), 11 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 6f0eb83661..f92bdea732 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -466,7 +466,6 @@ float32 HELPER(fcvtx_f64_to_f32)(float64 a, CPUARMState= *env) set_float_rounding_mode(float_round_to_zero, &tstat); set_float_exception_flags(0, &tstat); r =3D float64_to_float32(a, &tstat); - r =3D float32_maybe_silence_nan(r, &tstat); exflags =3D get_float_exception_flags(&tstat); if (exflags & float_flag_inexact) { r =3D make_float32(float32_val(r) | 1); diff --git a/target/arm/helper.c b/target/arm/helper.c index e05c7230d4..db8bbe52a6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11348,20 +11348,12 @@ FLOAT_CONVS(ui, d, 64, u) /* floating point conversion */ float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) { - float64 r =3D float32_to_float64(x, &env->vfp.fp_status); - /* ARM requires that S<->D conversion of any kind of NaN generates - * a quiet NaN by forcing the most significant frac bit to 1. - */ - return float64_maybe_silence_nan(r, &env->vfp.fp_status); + return float32_to_float64(x, &env->vfp.fp_status); } =20 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) { - float32 r =3D float64_to_float32(x, &env->vfp.fp_status); - /* ARM requires that S<->D conversion of any kind of NaN generates - * a quiet NaN by forcing the most significant frac bit to 1. - */ - return float32_maybe_silence_nan(r, &env->vfp.fp_status); + return float64_to_float32(x, &env->vfp.fp_status); } =20 /* VFP3 fixed point conversion. */ --=20 2.17.0 From nobody Wed Oct 29 23:02:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526336685243202.23012615165317; Mon, 14 May 2018 15:24:45 -0700 (PDT) Received: from localhost ([::1]:49945 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILtc-0001EL-8N for importer@patchew.org; Mon, 14 May 2018 18:24:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52506) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILhy-00081F-3a for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fILhw-0007sY-Uf for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:42 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:42032) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fILhw-0007qm-PE for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:40 -0400 Received: by mail-pg0-x242.google.com with SMTP id p9-v6so6060364pgc.9 for ; Mon, 14 May 2018 15:12:40 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v5 13/28] fpu/softfloat: Partial support for ARM Alternative half-precision X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Alex Benn=C3=A9e For float16 ARM supports an alternative half-precision format which sacrifices the ability to represent NaN/Inf in return for a higher dynamic range. The new FloatFmt flag, arm_althp, is then used to modify the behaviour of canonicalize and round_canonical with respect to representation and exception raising. Usage of this new flag waits until we re-factor float-to-float conversions. Signed-off-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Tested-by: Alex Benn=C3=A9e --- v3 - squash NaN to 0 if destination is AHP F16 v4 - handle inf -> ahp max in float_to_float not round_canonical - assert no nan and inf for ahp in round_canonical - check ahp before snan in float_to_float v5 - split out canonicalize and round_canonical changes from the rest --- fpu/softfloat.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 41253c6749..55d0d01ec3 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -220,8 +220,10 @@ typedef struct { * frac_shift: shift to normalise the fraction with DECOMPOSED_BINARY_PO= INT * The following are computed based the size of fraction * frac_lsb: least significant bit of fraction - * fram_lsbm1: the bit bellow the least significant bit (for rounding) + * frac_lsbm1: the bit bellow the least significant bit (for rounding) * round_mask/roundeven_mask: masks used for rounding + * The following optional modifiers are available: + * arm_althp: handle ARM Alternative Half Precision */ typedef struct { int exp_size; @@ -233,6 +235,7 @@ typedef struct { uint64_t frac_lsbm1; uint64_t round_mask; uint64_t roundeven_mask; + bool arm_althp; } FloatFmt; =20 /* Expand fields based on the size of exponent and fraction */ @@ -324,7 +327,7 @@ static inline float64 float64_pack_raw(FloatParts p) static FloatParts canonicalize(FloatParts part, const FloatFmt *parm, float_status *status) { - if (part.exp =3D=3D parm->exp_max) { + if (part.exp =3D=3D parm->exp_max && !parm->arm_althp) { if (part.frac =3D=3D 0) { part.cls =3D float_class_inf; } else { @@ -413,7 +416,15 @@ static FloatParts round_canonical(FloatParts p, float_= status *s, } frac >>=3D frac_shift; =20 - if (unlikely(exp >=3D exp_max)) { + if (parm->arm_althp) { + /* ARM Alt HP eschews Inf and NaN for a wider exponent. */ + if (unlikely(exp > exp_max)) { + /* Overflow. Return the maximum normal. */ + flags =3D float_flag_invalid; + exp =3D exp_max; + frac =3D -1; + } + } else if (unlikely(exp >=3D exp_max)) { flags |=3D float_flag_overflow | float_flag_inexact; if (overflow_norm) { exp =3D exp_max - 1; @@ -464,12 +475,14 @@ static FloatParts round_canonical(FloatParts p, float= _status *s, =20 case float_class_inf: do_inf: + assert(!parm->arm_althp); exp =3D exp_max; frac =3D 0; break; =20 case float_class_qnan: case float_class_snan: + assert(!parm->arm_althp); exp =3D exp_max; frac >>=3D parm->frac_shift; break; --=20 2.17.0 From nobody Wed Oct 29 23:02:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526337041284211.0520797491099; Mon, 14 May 2018 15:30:41 -0700 (PDT) Received: from localhost ([::1]:49986 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILzJ-0006N8-97 for importer@patchew.org; Mon, 14 May 2018 18:30:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52541) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILi1-00084h-OS for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fILhy-0007vg-PO for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:45 -0400 Received: from mail-pf0-x22c.google.com ([2607:f8b0:400e:c00::22c]:36752) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fILhy-0007u6-EB for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:42 -0400 Received: by mail-pf0-x22c.google.com with SMTP id w129-v6so6668454pfd.3 for ; Mon, 14 May 2018 15:12:42 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id y2-v6sm14512457pgp.92.2018.05.14.15.12.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 May 2018 15:12:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YVASLLmdeyYkv95jR1njHejb/dXrJzhKOk8H1pN32jc=; b=aIGJPLMpcFcgMDdkUonOWayAkoFGILlxFerx8y5OJ4/Ug3hKa2okknvZacc3jGZ3wi jZn+rzn+sgiU/4taTTtzadG3JGpIwpac83sKbtcFc3iNrmnRAanpRgeDpfFbRO/S2CDZ YZ9qcC1mVggiaBIrxIf68OKnY3Z+SUiVnQtfc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YVASLLmdeyYkv95jR1njHejb/dXrJzhKOk8H1pN32jc=; b=D0T0B54NbkwVrqw+H5DstcQXGRQlAn9+hLKIuExtU5sv35ModEl7w8+yagB/AkyrXM Aszmh8GBRcIHQ26xGB1idgL2CNwoB7h3xjz4UfWVm7697CyBf9mOizbnZ+UHu1/s7H/y qemEDlNq+8noUieEb0eKvVeq5osS1LWQPBfbTjcLpdKNlwDkTb+05O4FKjwdKCc9YZ/O NRT0JorvugzrBdlpZv2Rp1WWYEuBUHuIZWUv4HTrD1+t8/ULHSq6dUlbAQTcF5TwcMcj HYXho4MDmPyV2picFN40h1tfpSkwXgdYgVNDvWmY7NzTuLqy0h+ioKCNf+8/Gk6B42gg CHIg== X-Gm-Message-State: ALKqPwfGa6bwVOaW/HNZeVhO6u58ARBbOUzjNfeTnSJrHBUBzdWRmhnl yguXuovjNmQ92GEQhKLSdb6zb/fyPRA= X-Google-Smtp-Source: AB8JxZpHbVyhHPjXsC2BvfsElHJexDdzL9vYUmKsXYVKcTYtzT/EIFmHyKGNmwQescbKGOZKwj9NxA== X-Received: by 2002:a65:4a48:: with SMTP id a8-v6mr9491529pgu.395.1526335960798; Mon, 14 May 2018 15:12:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 May 2018 15:12:05 -0700 Message-Id: <20180514221219.7091-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180514221219.7091-1-richard.henderson@linaro.org> References: <20180514221219.7091-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22c Subject: [Qemu-devel] [PATCH v5 14/28] fpu/softfloat: re-factor float to float conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Alex Benn=C3=A9e This allows us to delete a lot of additional boilerplate code which is no longer needed. Signed-off-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Tested-by: Alex Benn=C3=A9e --- v2 - pass FloatFmt to float_to_float instead of sizes - split AHP handling to another patch - use rth's suggested re-packing (+ setting .exp) v3 - also rm extractFloat16Sign v4 - update for canonical nan handling v5 - merge arm alt fp16 support into this patch --- fpu/softfloat-specialize.h | 40 --- include/fpu/softfloat.h | 8 +- fpu/softfloat.c | 488 +++++++++---------------------------- 3 files changed, 122 insertions(+), 414 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 571d1df378..995a0132c6 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -377,46 +377,6 @@ float16 float16_maybe_silence_nan(float16 a, float_sta= tus *status) return a; } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the half-precision floating-point NaN -| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid -| exception is raised. -*-------------------------------------------------------------------------= ---*/ - -static commonNaNT float16ToCommonNaN(float16 a, float_status *status) -{ - commonNaNT z; - - if (float16_is_signaling_nan(a, status)) { - float_raise(float_flag_invalid, status); - } - z.sign =3D float16_val(a) >> 15; - z.low =3D 0; - z.high =3D ((uint64_t) float16_val(a)) << 54; - return z; -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the canonical NaN `a' to the half- -| precision floating-point format. -*-------------------------------------------------------------------------= ---*/ - -static float16 commonNaNToFloat16(commonNaNT a, float_status *status) -{ - uint16_t mantissa =3D a.high >> 54; - - if (status->default_nan_mode) { - return float16_default_nan(status); - } - - if (mantissa) { - return make_float16(((((uint16_t) a.sign) << 15) - | (0x1F << 10) | mantissa)); - } else { - return float16_default_nan(status); - } -} - /*------------------------------------------------------------------------= ---- | Returns 1 if the single-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 43962dc3f5..a6860e858d 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -211,10 +211,10 @@ float128 uint64_to_float128(uint64_t, float_status *s= tatus); /*------------------------------------------------------------------------= ---- | Software half-precision conversion routines. *-------------------------------------------------------------------------= ---*/ -float16 float32_to_float16(float32, flag, float_status *status); -float32 float16_to_float32(float16, flag, float_status *status); -float16 float64_to_float16(float64 a, flag ieee, float_status *status); -float64 float16_to_float64(float16 a, flag ieee, float_status *status); +float16 float32_to_float16(float32, bool ieee, float_status *status); +float32 float16_to_float32(float16, bool ieee, float_status *status); +float16 float64_to_float16(float64 a, bool ieee, float_status *status); +float64 float16_to_float64(float16 a, bool ieee, float_status *status); int16_t float16_to_int16(float16, float_status *status); uint16_t float16_to_uint16(float16 a, float_status *status); int16_t float16_to_int16_round_to_zero(float16, float_status *status); diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 55d0d01ec3..e9e421728b 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -113,15 +113,6 @@ static inline int extractFloat16Exp(float16 a) return (float16_val(a) >> 10) & 0x1f; } =20 -/*------------------------------------------------------------------------= ---- -| Returns the sign bit of the single-precision floating-point value `a'. -*-------------------------------------------------------------------------= ---*/ - -static inline flag extractFloat16Sign(float16 a) -{ - return float16_val(a)>>15; -} - /*------------------------------------------------------------------------= ---- | Returns the fraction bits of the single-precision floating-point value `= a'. *-------------------------------------------------------------------------= ---*/ @@ -254,6 +245,11 @@ static const FloatFmt float16_params =3D { FLOAT_PARAMS(5, 10) }; =20 +static const FloatFmt float16_params_ahp =3D { + FLOAT_PARAMS(5, 10), + .arm_althp =3D true +}; + static const FloatFmt float32_params =3D { FLOAT_PARAMS(8, 23) }; @@ -497,14 +493,27 @@ static FloatParts round_canonical(FloatParts p, float= _status *s, return p; } =20 +/* Explicit FloatFmt version */ +static FloatParts float16a_unpack_canonical(float16 f, float_status *s, + const FloatFmt *params) +{ + return canonicalize(float16_unpack_raw(f), params, s); +} + static FloatParts float16_unpack_canonical(float16 f, float_status *s) { - return canonicalize(float16_unpack_raw(f), &float16_params, s); + return float16a_unpack_canonical(f, s, &float16_params); +} + +static float16 float16a_round_pack_canonical(FloatParts p, float_status *s, + const FloatFmt *params) +{ + return float16_pack_raw(round_canonical(p, s, params)); } =20 static float16 float16_round_pack_canonical(FloatParts p, float_status *s) { - return float16_pack_raw(round_canonical(p, s, &float16_params)); + return float16a_round_pack_canonical(p, s, &float16_params); } =20 static FloatParts float32_unpack_canonical(float32 f, float_status *s) @@ -1181,6 +1190,104 @@ float64 float64_div(float64 a, float64 b, float_sta= tus *status) return float64_round_pack_canonical(pr, status); } =20 +/* + * Float to Float conversions + * + * Returns the result of converting one float format to another. The + * conversion is performed according to the IEC/IEEE Standard for + * Binary Floating-Point Arithmetic. + * + * The float_to_float helper only needs to take care of raising + * invalid exceptions and handling the conversion on NaNs. + */ + +static FloatParts float_to_float(FloatParts a, const FloatFmt *dstf, + float_status *s) +{ + if (dstf->arm_althp) { + switch (a.cls) { + case float_class_qnan: + case float_class_snan: + /* There is no NaN in the destination format. Raise Invalid + * and return a zero with the sign of the input NaN. + */ + s->float_exception_flags |=3D float_flag_invalid; + a.cls =3D float_class_zero; + a.frac =3D 0; + a.exp =3D 0; + break; + + case float_class_inf: + /* There is no Inf in the destination format. Raise Invalid + * and return the maximum normal with the correct sign. + */ + s->float_exception_flags |=3D float_flag_invalid; + a.cls =3D float_class_normal; + a.exp =3D dstf->exp_max; + a.frac =3D ((1ull << dstf->frac_size) - 1) << dstf->frac_shift; + break; + + default: + break; + } + } else if (is_nan(a.cls)) { + if (is_snan(a.cls)) { + s->float_exception_flags |=3D float_flag_invalid; + a =3D parts_silence_nan(a, s); + } + if (s->default_nan_mode) { + return parts_default_nan(s); + } + } + return a; +} + +float32 float16_to_float32(float16 a, bool ieee, float_status *s) +{ + const FloatFmt *fmt16 =3D ieee ? &float16_params : &float16_params_ahp; + FloatParts p =3D float16a_unpack_canonical(a, s, fmt16); + FloatParts pr =3D float_to_float(p, &float32_params, s); + return float32_round_pack_canonical(pr, s); +} + +float64 float16_to_float64(float16 a, bool ieee, float_status *s) +{ + const FloatFmt *fmt16 =3D ieee ? &float16_params : &float16_params_ahp; + FloatParts p =3D float16a_unpack_canonical(a, s, fmt16); + FloatParts pr =3D float_to_float(p, &float64_params, s); + return float64_round_pack_canonical(pr, s); +} + +float16 float32_to_float16(float32 a, bool ieee, float_status *s) +{ + const FloatFmt *fmt16 =3D ieee ? &float16_params : &float16_params_ahp; + FloatParts p =3D float32_unpack_canonical(a, s); + FloatParts pr =3D float_to_float(p, fmt16, s); + return float16a_round_pack_canonical(pr, s, fmt16); +} + +float64 float32_to_float64(float32 a, float_status *s) +{ + FloatParts p =3D float32_unpack_canonical(a, s); + FloatParts pr =3D float_to_float(p, &float64_params, s); + return float64_round_pack_canonical(pr, s); +} + +float16 float64_to_float16(float64 a, bool ieee, float_status *s) +{ + const FloatFmt *fmt16 =3D ieee ? &float16_params : &float16_params_ahp; + FloatParts p =3D float64_unpack_canonical(a, s); + FloatParts pr =3D float_to_float(p, fmt16, s); + return float16a_round_pack_canonical(pr, s, fmt16); +} + +float32 float64_to_float32(float64 a, float_status *s) +{ + FloatParts p =3D float64_unpack_canonical(a, s); + FloatParts pr =3D float_to_float(p, &float32_params, s); + return float32_round_pack_canonical(pr, s); +} + /* * Rounds the floating-point value `a' to an integer, and returns the * result as a floating-point value. The operation is performed @@ -3124,41 +3231,6 @@ float128 uint64_to_float128(uint64_t a, float_status= *status) return normalizeRoundAndPackFloat128(0, 0x406E, 0, a, status); } =20 - - - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the single-precision floating-point val= ue -| `a' to the double-precision floating-point format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float64 float32_to_float64(float32 a, float_status *status) -{ - flag aSign; - int aExp; - uint32_t aSig; - a =3D float32_squash_input_denormal(a, status); - - aSig =3D extractFloat32Frac( a ); - aExp =3D extractFloat32Exp( a ); - aSign =3D extractFloat32Sign( a ); - if ( aExp =3D=3D 0xFF ) { - if (aSig) { - return commonNaNToFloat64(float32ToCommonNaN(a, status), statu= s); - } - return packFloat64( aSign, 0x7FF, 0 ); - } - if ( aExp =3D=3D 0 ) { - if ( aSig =3D=3D 0 ) return packFloat64( aSign, 0, 0 ); - normalizeFloat32Subnormal( aSig, &aExp, &aSig ); - --aExp; - } - return packFloat64( aSign, aExp + 0x380, ( (uint64_t) aSig )<<29 ); - -} - /*------------------------------------------------------------------------= ---- | Returns the result of converting the single-precision floating-point val= ue | `a' to the extended double-precision floating-point format. The convers= ion @@ -3677,173 +3749,6 @@ int float32_unordered_quiet(float32 a, float32 b, f= loat_status *status) return 0; } =20 - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the double-precision floating-point val= ue -| `a' to the single-precision floating-point format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float32 float64_to_float32(float64 a, float_status *status) -{ - flag aSign; - int aExp; - uint64_t aSig; - uint32_t zSig; - a =3D float64_squash_input_denormal(a, status); - - aSig =3D extractFloat64Frac( a ); - aExp =3D extractFloat64Exp( a ); - aSign =3D extractFloat64Sign( a ); - if ( aExp =3D=3D 0x7FF ) { - if (aSig) { - return commonNaNToFloat32(float64ToCommonNaN(a, status), statu= s); - } - return packFloat32( aSign, 0xFF, 0 ); - } - shift64RightJamming( aSig, 22, &aSig ); - zSig =3D aSig; - if ( aExp || zSig ) { - zSig |=3D 0x40000000; - aExp -=3D 0x381; - } - return roundAndPackFloat32(aSign, aExp, zSig, status); - -} - - -/*------------------------------------------------------------------------= ---- -| Packs the sign `zSign', exponent `zExp', and significand `zSig' into a -| half-precision floating-point value, returning the result. After being -| shifted into the proper positions, the three fields are simply added -| together to form the result. This means that any integer portion of `zS= ig' -| will be added into the exponent. Since a properly normalized significand -| will have an integer portion equal to 1, the `zExp' input should be 1 le= ss -| than the desired result exponent whenever `zSig' is a complete, normaliz= ed -| significand. -*-------------------------------------------------------------------------= ---*/ -static float16 packFloat16(flag zSign, int zExp, uint16_t zSig) -{ - return make_float16( - (((uint32_t)zSign) << 15) + (((uint32_t)zExp) << 10) + zSig); -} - -/*------------------------------------------------------------------------= ---- -| Takes an abstract floating-point value having sign `zSign', exponent `zE= xp', -| and significand `zSig', and returns the proper half-precision floating- -| point value corresponding to the abstract input. Ordinarily, the abstra= ct -| value is simply rounded and packed into the half-precision format, with -| the inexact exception raised if the abstract input cannot be represented -| exactly. However, if the abstract value is too large, the overflow and -| inexact exceptions are raised and an infinity or maximal finite value is -| returned. If the abstract value is too small, the input value is rounde= d to -| a subnormal number, and the underflow and inexact exceptions are raised = if -| the abstract input cannot be represented exactly as a subnormal half- -| precision floating-point number. -| The `ieee' flag indicates whether to use IEEE standard half precision, or -| ARM-style "alternative representation", which omits the NaN and Inf -| encodings in order to raise the maximum representable exponent by one. -| The input significand `zSig' has its binary point between bits 22 -| and 23, which is 13 bits to the left of the usual location. This shifted -| significand must be normalized or smaller. If `zSig' is not normalized, -| `zExp' must be 0; in that case, the result returned is a subnormal numbe= r, -| and it must not require rounding. In the usual case that `zSig' is -| normalized, `zExp' must be 1 less than the ``true'' floating-point expon= ent. -| Note the slightly odd position of the binary point in zSig compared with= the -| other roundAndPackFloat functions. This should probably be fixed if we -| need to implement more float16 routines than just conversion. -| The handling of underflow and overflow follows the IEC/IEEE Standard for -| Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -static float16 roundAndPackFloat16(flag zSign, int zExp, - uint32_t zSig, flag ieee, - float_status *status) -{ - int maxexp =3D ieee ? 29 : 30; - uint32_t mask; - uint32_t increment; - bool rounding_bumps_exp; - bool is_tiny =3D false; - - /* Calculate the mask of bits of the mantissa which are not - * representable in half-precision and will be lost. - */ - if (zExp < 1) { - /* Will be denormal in halfprec */ - mask =3D 0x00ffffff; - if (zExp >=3D -11) { - mask >>=3D 11 + zExp; - } - } else { - /* Normal number in halfprec */ - mask =3D 0x00001fff; - } - - switch (status->float_rounding_mode) { - case float_round_nearest_even: - increment =3D (mask + 1) >> 1; - if ((zSig & mask) =3D=3D increment) { - increment =3D zSig & (increment << 1); - } - break; - case float_round_ties_away: - increment =3D (mask + 1) >> 1; - break; - case float_round_up: - increment =3D zSign ? 0 : mask; - break; - case float_round_down: - increment =3D zSign ? mask : 0; - break; - default: /* round_to_zero */ - increment =3D 0; - break; - } - - rounding_bumps_exp =3D (zSig + increment >=3D 0x01000000); - - if (zExp > maxexp || (zExp =3D=3D maxexp && rounding_bumps_exp)) { - if (ieee) { - float_raise(float_flag_overflow | float_flag_inexact, status); - return packFloat16(zSign, 0x1f, 0); - } else { - float_raise(float_flag_invalid, status); - return packFloat16(zSign, 0x1f, 0x3ff); - } - } - - if (zExp < 0) { - /* Note that flush-to-zero does not affect half-precision results = */ - is_tiny =3D - (status->float_detect_tininess =3D=3D float_tininess_before_ro= unding) - || (zExp < -1) - || (!rounding_bumps_exp); - } - if (zSig & mask) { - float_raise(float_flag_inexact, status); - if (is_tiny) { - float_raise(float_flag_underflow, status); - } - } - - zSig +=3D increment; - if (rounding_bumps_exp) { - zSig >>=3D 1; - zExp++; - } - - if (zExp < -10) { - return packFloat16(zSign, 0, 0); - } - if (zExp < 0) { - zSig >>=3D -zExp; - zExp =3D 0; - } - return packFloat16(zSign, zExp, zSig >> 13); -} - /*------------------------------------------------------------------------= ---- | If `a' is denormal and we are in flush-to-zero mode then set the | input-denormal exception and return zero. Otherwise just return the valu= e. @@ -3859,163 +3764,6 @@ float16 float16_squash_input_denormal(float16 a, fl= oat_status *status) return a; } =20 -static void normalizeFloat16Subnormal(uint32_t aSig, int *zExpPtr, - uint32_t *zSigPtr) -{ - int8_t shiftCount =3D countLeadingZeros32(aSig) - 21; - *zSigPtr =3D aSig << shiftCount; - *zExpPtr =3D 1 - shiftCount; -} - -/* Half precision floats come in two formats: standard IEEE and "ARM" form= at. - The latter gains extra exponent range by omitting the NaN/Inf encodings= . */ - -float32 float16_to_float32(float16 a, flag ieee, float_status *status) -{ - flag aSign; - int aExp; - uint32_t aSig; - - aSign =3D extractFloat16Sign(a); - aExp =3D extractFloat16Exp(a); - aSig =3D extractFloat16Frac(a); - - if (aExp =3D=3D 0x1f && ieee) { - if (aSig) { - return commonNaNToFloat32(float16ToCommonNaN(a, status), statu= s); - } - return packFloat32(aSign, 0xff, 0); - } - if (aExp =3D=3D 0) { - if (aSig =3D=3D 0) { - return packFloat32(aSign, 0, 0); - } - - normalizeFloat16Subnormal(aSig, &aExp, &aSig); - aExp--; - } - return packFloat32( aSign, aExp + 0x70, aSig << 13); -} - -float16 float32_to_float16(float32 a, flag ieee, float_status *status) -{ - flag aSign; - int aExp; - uint32_t aSig; - - a =3D float32_squash_input_denormal(a, status); - - aSig =3D extractFloat32Frac( a ); - aExp =3D extractFloat32Exp( a ); - aSign =3D extractFloat32Sign( a ); - if ( aExp =3D=3D 0xFF ) { - if (aSig) { - /* Input is a NaN */ - if (!ieee) { - float_raise(float_flag_invalid, status); - return packFloat16(aSign, 0, 0); - } - return commonNaNToFloat16( - float32ToCommonNaN(a, status), status); - } - /* Infinity */ - if (!ieee) { - float_raise(float_flag_invalid, status); - return packFloat16(aSign, 0x1f, 0x3ff); - } - return packFloat16(aSign, 0x1f, 0); - } - if (aExp =3D=3D 0 && aSig =3D=3D 0) { - return packFloat16(aSign, 0, 0); - } - /* Decimal point between bits 22 and 23. Note that we add the 1 bit - * even if the input is denormal; however this is harmless because - * the largest possible single-precision denormal is still smaller - * than the smallest representable half-precision denormal, and so we - * will end up ignoring aSig and returning via the "always return zero" - * codepath. - */ - aSig |=3D 0x00800000; - aExp -=3D 0x71; - - return roundAndPackFloat16(aSign, aExp, aSig, ieee, status); -} - -float64 float16_to_float64(float16 a, flag ieee, float_status *status) -{ - flag aSign; - int aExp; - uint32_t aSig; - - aSign =3D extractFloat16Sign(a); - aExp =3D extractFloat16Exp(a); - aSig =3D extractFloat16Frac(a); - - if (aExp =3D=3D 0x1f && ieee) { - if (aSig) { - return commonNaNToFloat64( - float16ToCommonNaN(a, status), status); - } - return packFloat64(aSign, 0x7ff, 0); - } - if (aExp =3D=3D 0) { - if (aSig =3D=3D 0) { - return packFloat64(aSign, 0, 0); - } - - normalizeFloat16Subnormal(aSig, &aExp, &aSig); - aExp--; - } - return packFloat64(aSign, aExp + 0x3f0, ((uint64_t)aSig) << 42); -} - -float16 float64_to_float16(float64 a, flag ieee, float_status *status) -{ - flag aSign; - int aExp; - uint64_t aSig; - uint32_t zSig; - - a =3D float64_squash_input_denormal(a, status); - - aSig =3D extractFloat64Frac(a); - aExp =3D extractFloat64Exp(a); - aSign =3D extractFloat64Sign(a); - if (aExp =3D=3D 0x7FF) { - if (aSig) { - /* Input is a NaN */ - if (!ieee) { - float_raise(float_flag_invalid, status); - return packFloat16(aSign, 0, 0); - } - return commonNaNToFloat16( - float64ToCommonNaN(a, status), status); - } - /* Infinity */ - if (!ieee) { - float_raise(float_flag_invalid, status); - return packFloat16(aSign, 0x1f, 0x3ff); - } - return packFloat16(aSign, 0x1f, 0); - } - shift64RightJamming(aSig, 29, &aSig); - zSig =3D aSig; - if (aExp =3D=3D 0 && zSig =3D=3D 0) { - return packFloat16(aSign, 0, 0); - } - /* Decimal point between bits 22 and 23. Note that we add the 1 bit - * even if the input is denormal; however this is harmless because - * the largest possible single-precision denormal is still smaller - * than the smallest representable half-precision denormal, and so we - * will end up ignoring aSig and returning via the "always return zero" - * codepath. - */ - zSig |=3D 0x00800000; - aExp -=3D 0x3F1; - - return roundAndPackFloat16(aSign, aExp, zSig, ieee, status); -} - /*------------------------------------------------------------------------= ---- | Returns the result of converting the double-precision floating-point val= ue | `a' to the extended double-precision floating-point format. The convers= ion --=20 2.17.0 From nobody Wed Oct 29 23:02:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526336853767868.3551863241587; Mon, 14 May 2018 15:27:33 -0700 (PDT) Received: from localhost ([::1]:49964 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILwK-0003hP-Vq for importer@patchew.org; Mon, 14 May 2018 18:27:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52537) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILi1-00084Q-Gz for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fILhz-0007xk-M8 for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:45 -0400 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:47014) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fILhz-0007wJ-G6 for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:43 -0400 Received: by mail-pg0-x241.google.com with SMTP id z4-v6so6056119pgu.13 for ; Mon, 14 May 2018 15:12:43 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id y2-v6sm14512457pgp.92.2018.05.14.15.12.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 May 2018 15:12:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1Mx8i479tPm4Ez9yZyrtzG8zM3rDgGJOLuQ8CZwezuY=; b=iOhj4Jn/bKMaUxN7uUFY0a9XgqdblkmATGsNwXqgoUYqhFj0ZEvOjPEtK1rwWMa1NC r4rbag3m7rOPQXIPxAVRv6ommiSeLh9fs6jHHkjXESSO7rQkpOjXNS6OGFv+cD6zNyp8 OXQufz3HxMS7VypsNWCQEtpZ2c3f9TLWa1f8I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1Mx8i479tPm4Ez9yZyrtzG8zM3rDgGJOLuQ8CZwezuY=; b=Fk2039ehp6Xy6lkigFNLUnjYOH/zK0b9XLPvcrV1WEF8fzCI4ynR9CUk5DCsGuPBjN p5HLUpksxwbgiIRqZiR1CekfOJ+v5Cdiq+uBT+AgqOcG4IJnzWEH5gzxS9l8Jp52aqoM bDtuiDGyJhI5G3A12Ylue/nfXbTmTq/Fl911Mg3+vQ08O6uR6fDl267uv2zlCDhpiY9F 9cDsNh3UkCjGtiwCu2vb+Pyv+jK56sVkqRsA6No/uDavXM0quVyv9n3KcTNfaxQMoK+T X4RETCblfNpgTFjxAoKhJyXCOlyBSOxTnI0k+6wbIYIB6p7M73vffWGx4WKyDF9gt+0U y8og== X-Gm-Message-State: ALKqPwfVSKz0qvMA8InufhUT0u7PC490OQhFDdAYtYw4/JAqI/2TcN11 c23oBjnpoIsKWHgnSLOuI9wSlCAGuAU= X-Google-Smtp-Source: AB8JxZpZfg0E0EC/jIHSRbRQddsV3g1/JbX6mQzf7jVa+w7S8frE8L7/hK7nDEN7PYRqybYx3vTqtA== X-Received: by 2002:a63:b406:: with SMTP id s6-v6mr10076044pgf.334.1526335962306; Mon, 14 May 2018 15:12:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 May 2018 15:12:06 -0700 Message-Id: <20180514221219.7091-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180514221219.7091-1-richard.henderson@linaro.org> References: <20180514221219.7091-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v5 15/28] target/hppa: Remove floatX_maybe_silence_nan from conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is now handled properly by the generic softfloat code. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Tested-by: Alex Benn=C3=A9e --- target/hppa/op_helper.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index a3af62daf7..912e8d5be4 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -341,7 +341,6 @@ float64 HELPER(fdiv_d)(CPUHPPAState *env, float64 a, fl= oat64 b) float64 HELPER(fcnv_s_d)(CPUHPPAState *env, float32 arg) { float64 ret =3D float32_to_float64(arg, &env->fp_status); - ret =3D float64_maybe_silence_nan(ret, &env->fp_status); update_fr0_op(env, GETPC()); return ret; } @@ -349,7 +348,6 @@ float64 HELPER(fcnv_s_d)(CPUHPPAState *env, float32 arg) float32 HELPER(fcnv_d_s)(CPUHPPAState *env, float64 arg) { float32 ret =3D float64_to_float32(arg, &env->fp_status); - ret =3D float32_maybe_silence_nan(ret, &env->fp_status); update_fr0_op(env, GETPC()); return ret; } --=20 2.17.0 From nobody Wed Oct 29 23:02:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526336864730567.6236916504665; Mon, 14 May 2018 15:27:44 -0700 (PDT) Received: from localhost ([::1]:49965 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILwV-0003tY-SL for importer@patchew.org; Mon, 14 May 2018 18:27:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52539) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILi1-00084f-NW for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fILi0-00080V-QH for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:45 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:34389) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fILi0-0007z8-L3 for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:44 -0400 Received: by mail-pg0-x244.google.com with SMTP id k2-v6so484935pgc.1 for ; Mon, 14 May 2018 15:12:44 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id y2-v6sm14512457pgp.92.2018.05.14.15.12.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 May 2018 15:12:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ec+SMNRzcNPO1wdC4VjFMBQqFtdgGcnELN/AuHLHLvE=; b=f0batlrH7F8ypHM2bjxZVAr3xMv29jFDATnedebG6Uhv1mIswvaIVZTfcLhwToS09r vPJdGVa+ztOkv4ipGFhndwUxLwiwI8A72GNgnDNnbIdva9zbILfPsQgjIIYcQ2SSxRn+ BapcLOYc8a8FHnj0ZmhGRjhkQbZfl23TpGwnE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ec+SMNRzcNPO1wdC4VjFMBQqFtdgGcnELN/AuHLHLvE=; b=EFSygQGdHdrnnKDox9twqPuuGz3fkDMfMGZfFQOkfm1iWMtlEDLroe+irGJA8EgRJu PjeqnYg0AKMLDP+/hbPG0mBrhxu+OFdfXRxF6zcxh8huzTIaLDAhuE5H8vntWratCZnB 5sXAtbA2oVQmf/+AUNINExDR0nK89PgEF4oIYkfXgoxWU1Sz6mVGmPzmYcuaZtNbetuQ Zzx1rANextzpoGjX7axSgtr/tANVvjPIFtklgJ6WkuDc4V09B8TAqcsskKKpSzGcUWPO GjQpPvIjkqdgZdCGXwoajsPNqRDMyRqRxlF0cG7/LQMpnslSGBH0Il8Fm39cLBEHySVv PrSQ== X-Gm-Message-State: ALKqPwe8icuZ8J2WJJZeAvGedauStzTzscx4LQan3YNtSGMA/NY5N3qC gvQmA7FswUPLcEY5sB8xQ7b3XWk+ku0= X-Google-Smtp-Source: AB8JxZpKTxDWEq+2XEL9KY1DHw9OxwDTBEfNb5yatWtEM1baGhw4absjZUTBBZ0wdJxxw0idxoJIFw== X-Received: by 2002:a65:61c8:: with SMTP id j8-v6mr9804784pgv.370.1526335963510; Mon, 14 May 2018 15:12:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 May 2018 15:12:07 -0700 Message-Id: <20180514221219.7091-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180514221219.7091-1-richard.henderson@linaro.org> References: <20180514221219.7091-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v5 16/28] target/m68k: Use floatX_silence_nan when we have already checked for SNaN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/m68k/softfloat.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/m68k/softfloat.c b/target/m68k/softfloat.c index e41b07d042..6ec227e20f 100644 --- a/target/m68k/softfloat.c +++ b/target/m68k/softfloat.c @@ -31,13 +31,14 @@ static floatx80 propagateFloatx80NaNOneArg(floatx80 a, = float_status *status) { if (floatx80_is_signaling_nan(a, status)) { float_raise(float_flag_invalid, status); + a =3D floatx80_silence_nan(a, status); } =20 if (status->default_nan_mode) { return floatx80_default_nan(status); } =20 - return floatx80_maybe_silence_nan(a, status); + return a; } =20 /*------------------------------------------------------------------------= ---- --=20 2.17.0 From nobody Wed Oct 29 23:02:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526336827606282.4144618657806; Mon, 14 May 2018 15:27:07 -0700 (PDT) Received: from localhost ([::1]:49963 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILvu-0003MD-MR for importer@patchew.org; Mon, 14 May 2018 18:27:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52561) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILi3-00086n-Qk for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fILi2-00084G-Io for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:47 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:46272) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fILi2-00082b-DF for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:46 -0400 Received: by mail-pf0-x244.google.com with SMTP id p12-v6so6656624pff.13 for ; Mon, 14 May 2018 15:12:46 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id y2-v6sm14512457pgp.92.2018.05.14.15.12.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 May 2018 15:12:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YG4WDuvg/nU14CtfIK1nI16sf1EHjyzdnNJh8QSrA1M=; b=PVWlf9na+m230jhnYcQw+laf+8jfu7s3eAYWA+ASbwYchpY6hJhYe7V3vjZAlPNy8d rmFp2RMcRCKpW3TMahvSK4/3x6J1MaN+TUuls6lzXZzXUeMMyUGq4JPV+47z5wH4eGOo IUN+fxRv+IESeGxI02yD8dA9yRFaBGT1C9fX8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YG4WDuvg/nU14CtfIK1nI16sf1EHjyzdnNJh8QSrA1M=; b=kUxY/rgNNS+KaujcTzMQvhkMmrn0XSnbLn3CxbqSPmgZsIzqqxibh1pJjdiPrDQ/we L7hf1ugVEelCQFSXuhHlcAc0Xkd+fwOD4uuXDp7JY6TI67V99voPuvz3nh5IjCqwoXye JKJFL8hWxEI5Zyubl+8lgWBUIxBabnHzWR2Nlh6zKcxdT8xoInIditcUj8Z+AY0GLsbb h4x5073AUucoxsS3ErvqK1ckmHgvYbo7QPPuCsTqWUATEnkYqDNqJPFXZTOm3lRwuiTE VZHFDEpNMhB8moBIZw/NZPKWwFervgI/jC9wMjoqGi4sq9XIQDptEBIpHxtpt+7bI5Qy LqIw== X-Gm-Message-State: ALKqPwfEYaO+Khy3+2pEgb0TpGXsmEH35+mA+2g/yfF86xQL30ve0fdj 5B0qYaywHL6yyJ9+7DnBj8FS7UmezCo= X-Google-Smtp-Source: AB8JxZrZgBMAg+x3/KrsGbs67oxOFECS3BeY0rwwR0Hwc//5ynMj1DMmSeMzu2Xc7Jpfx1AExAPCvA== X-Received: by 2002:a63:887:: with SMTP id 129-v6mr9671439pgi.17.1526335965161; Mon, 14 May 2018 15:12:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 May 2018 15:12:08 -0700 Message-Id: <20180514221219.7091-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180514221219.7091-1-richard.henderson@linaro.org> References: <20180514221219.7091-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v5 17/28] target/mips: Remove floatX_maybe_silence_nan from conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Yongbok Kim , alex.bennee@linaro.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is now handled properly by the generic softfloat code. Cc: Aurelien Jarno Cc: Yongbok Kim Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/mips/msa_helper.c | 4 ---- target/mips/op_helper.c | 2 -- 2 files changed, 6 deletions(-) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 8fb7a369ca..c74e3cdc65 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -1615,7 +1615,6 @@ static inline float16 float16_from_float32(int32_t a,= flag ieee, float16 f_val; =20 f_val =3D float32_to_float16((float32)a, ieee, status); - f_val =3D float16_maybe_silence_nan(f_val, status); =20 return a < 0 ? (f_val | (1 << 15)) : f_val; } @@ -1625,7 +1624,6 @@ static inline float32 float32_from_float64(int64_t a,= float_status *status) float32 f_val; =20 f_val =3D float64_to_float32((float64)a, status); - f_val =3D float32_maybe_silence_nan(f_val, status); =20 return a < 0 ? (f_val | (1 << 31)) : f_val; } @@ -1636,7 +1634,6 @@ static inline float32 float32_from_float16(int16_t a,= flag ieee, float32 f_val; =20 f_val =3D float16_to_float32((float16)a, ieee, status); - f_val =3D float32_maybe_silence_nan(f_val, status); =20 return a < 0 ? (f_val | (1 << 31)) : f_val; } @@ -1646,7 +1643,6 @@ static inline float64 float64_from_float32(int32_t a,= float_status *status) float64 f_val; =20 f_val =3D float32_to_float64((float64)a, status); - f_val =3D float64_maybe_silence_nan(f_val, status); =20 return a < 0 ? (f_val | (1ULL << 63)) : f_val; } diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 798cdad030..9025f42366 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -2700,7 +2700,6 @@ uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint3= 2_t fst0) uint64_t fdt2; =20 fdt2 =3D float32_to_float64(fst0, &env->active_fpu.fp_status); - fdt2 =3D float64_maybe_silence_nan(fdt2, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); return fdt2; } @@ -2790,7 +2789,6 @@ uint32_t helper_float_cvts_d(CPUMIPSState *env, uint6= 4_t fdt0) uint32_t fst2; =20 fst2 =3D float64_to_float32(fdt0, &env->active_fpu.fp_status); - fst2 =3D float32_maybe_silence_nan(fst2, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); return fst2; } --=20 2.17.0 From nobody Wed Oct 29 23:02:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526336647862212.53645911173192; Mon, 14 May 2018 15:24:07 -0700 (PDT) Received: from localhost ([::1]:49942 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILsr-0000UC-N2 for importer@patchew.org; Mon, 14 May 2018 18:23:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52576) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILi5-00088c-BR for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fILi4-00087W-3c for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:49 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:45659) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fILi3-000861-TF for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:48 -0400 Received: by mail-pf0-x244.google.com with SMTP id c10-v6so6658570pfi.12 for ; Mon, 14 May 2018 15:12:47 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id y2-v6sm14512457pgp.92.2018.05.14.15.12.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 May 2018 15:12:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lFbjHgIjVdntVwEG8TX8Zn/QYQH/a160DBSlPiGyBN4=; b=O7YckEzOS93CP+o7AXg6CyjlcHA9jJ2BSUh3uz5RjL5LZxTWHhekG5PF0Zmupi4yHg yHH9oa0dHDuPew4iUP+MWbvu3QWFva1OBjHGFnB4Hlkv1CwNH6bdmsuelJbY4ShiFvDd L9GrWtcPRr86OWHEVLVsV5dfiwmPe1BoZuB0Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lFbjHgIjVdntVwEG8TX8Zn/QYQH/a160DBSlPiGyBN4=; b=CwMOji/qc1zx8TyZvjzSqv52Oy+KxT84XqtB9RCCraF3vLFBN8Y1n1UcZK7ZDDhaJE WenTSjMMetmoVldGyf/oFuJgNekzRyVdkgHSY64Tbsc97EouDdC8TXKOQ5jjgGp86Bjg T2KC+by1WsEyUcGQli4u1CwDUnsVbbt9CYcqP2J2RvJJPSw9zxVUgFasI/u2xqXJAz2P KNd9cKQvNviEdp87v8EKy48KeIWe3XG4Jh/S6Nlq1XEJRiriWRVWevh7mO2PCWx+/Zu5 zEsb6XG0oh1edEU2w8a0exBIZI/yJnJIXKPmQ1RU8EBZaDliTMBuvsK1mzYGX+ki5dde zPAg== X-Gm-Message-State: ALKqPwf61TS+kFZEJgOz2ZWMoDzYJ1WMUyJa/ZGW7h5sQHX6v5RsorDy amZCj4ZTP/ohaCy/7LnQbUyHAgkomvY= X-Google-Smtp-Source: AB8JxZoXaFnkDGlh7SrwxFOe1FFBMSp7mBn4m/zFf8T3Sz8bS68lhbY51K/qjkIL2chMxjrkGVsQag== X-Received: by 2002:a65:5008:: with SMTP id f8-v6mr6019205pgo.349.1526335966786; Mon, 14 May 2018 15:12:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 May 2018 15:12:09 -0700 Message-Id: <20180514221219.7091-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180514221219.7091-1-richard.henderson@linaro.org> References: <20180514221219.7091-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v5 18/28] target/riscv: Remove floatX_maybe_silence_nan from conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Palmer Dabbelt , alex.bennee@linaro.org, Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is now handled properly by the generic softfloat code. Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Reviewed-by: Michael Clark Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/riscv/fpu_helper.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index abbadead5c..fdb87d8d82 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -279,14 +279,12 @@ uint64_t helper_fmax_d(CPURISCVState *env, uint64_t f= rs1, uint64_t frs2) =20 uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1) { - rs1 =3D float64_to_float32(rs1, &env->fp_status); - return float32_maybe_silence_nan(rs1, &env->fp_status); + return float64_to_float32(rs1, &env->fp_status); } =20 uint64_t helper_fcvt_d_s(CPURISCVState *env, uint64_t rs1) { - rs1 =3D float32_to_float64(rs1, &env->fp_status); - return float64_maybe_silence_nan(rs1, &env->fp_status); + return float32_to_float64(rs1, &env->fp_status); } =20 uint64_t helper_fsqrt_d(CPURISCVState *env, uint64_t frs1) --=20 2.17.0 From nobody Wed Oct 29 23:02:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526337021013683.925439838857; Mon, 14 May 2018 15:30:21 -0700 (PDT) Received: from localhost ([::1]:49985 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILz1-0006B2-0y for importer@patchew.org; Mon, 14 May 2018 18:30:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52589) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILi6-00089p-FE for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fILi5-0008A0-Cs for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:50 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:36605) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fILi5-00088s-6W for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:49 -0400 Received: by mail-pg0-x244.google.com with SMTP id z70-v6so6065153pgz.3 for ; Mon, 14 May 2018 15:12:49 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id y2-v6sm14512457pgp.92.2018.05.14.15.12.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 May 2018 15:12:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=N/MQDXmC5P0rKEPWLGL6olcs6gD/4PAiety6G0UTpec=; b=EwcG9ejWdyJWfKlpQmklMu8vZBOnL9752ihIsFo6JYbSm5oRChU6KIJeoQc//rlrtn dX8Ucb+Ccalu0SeF9af1Be3+fXBYGWkr4M1C0aT1qurXkGbVSJpDrsKIbA0DRs4557gV ZVQCfEJWYJGumhyzpjYcEBPOfjmskekaimsEM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=N/MQDXmC5P0rKEPWLGL6olcs6gD/4PAiety6G0UTpec=; b=fQrtA+3vBxGKEjeYwRR3kZflLVZyd4QC55LtkQRzRB3ByMCsQygnPD/gPNdYMw7NeY q/vtlTwxZY67lgI1py/mSrhMsgXCeRp4Y8sP6IykgejmOyYOMQ7rzE2P6mRyzZBT2lKP s95hBVZWQh/bqR5EDZwwcF3NXYCW+DHC4qYUHWJO57UF0/jgK+bYFVgcYvD6fz3p9OVd 1wumyT/n70eJ0Tl6Elz+07d0HoAFGKACX5Nt6Tri1BhxlwW4lx7tPYSndeNf0mRUrNOA fbDWbGhNnfSdurfNuTESn+5PgyGmaLxK5Q/4XO0gx2DBEtnu03s/w05LemXI+swtxpuv aISw== X-Gm-Message-State: ALKqPwf5VlcXu14fi7iEj63vFPHLMhGXCib2I5JEgt8dW82vdqiVvVYW F0n5v8a/AeR8xRNoieFZ1ZLSvLeqCSU= X-Google-Smtp-Source: AB8JxZqUT3rWqsbFGfH5YUpOp3EyXMdTX8sZLk971Zf/6KLYg4KhP4SqbwRTAbJMiC18fp/QY5TNTg== X-Received: by 2002:a63:6d42:: with SMTP id i63-v6mr9934803pgc.161.1526335967979; Mon, 14 May 2018 15:12:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 May 2018 15:12:10 -0700 Message-Id: <20180514221219.7091-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180514221219.7091-1-richard.henderson@linaro.org> References: <20180514221219.7091-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v5 19/28] target/s390x: Remove floatX_maybe_silence_nan from conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, Alexander Graf Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is now handled properly by the generic softfloat code. Cc: Alexander Graf Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/s390x/fpu_helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/s390x/fpu_helper.c b/target/s390x/fpu_helper.c index 43f8bf1c94..5c5b451b3b 100644 --- a/target/s390x/fpu_helper.c +++ b/target/s390x/fpu_helper.c @@ -269,7 +269,7 @@ uint64_t HELPER(ldeb)(CPUS390XState *env, uint64_t f2) { float64 ret =3D float32_to_float64(f2, &env->fpu_status); handle_exceptions(env, GETPC()); - return float64_maybe_silence_nan(ret, &env->fpu_status); + return ret; } =20 /* convert 128-bit float to 64-bit float */ @@ -277,7 +277,7 @@ uint64_t HELPER(ldxb)(CPUS390XState *env, uint64_t ah, = uint64_t al) { float64 ret =3D float128_to_float64(make_float128(ah, al), &env->fpu_s= tatus); handle_exceptions(env, GETPC()); - return float64_maybe_silence_nan(ret, &env->fpu_status); + return ret; } =20 /* convert 64-bit float to 128-bit float */ @@ -285,7 +285,7 @@ uint64_t HELPER(lxdb)(CPUS390XState *env, uint64_t f2) { float128 ret =3D float64_to_float128(f2, &env->fpu_status); handle_exceptions(env, GETPC()); - return RET128(float128_maybe_silence_nan(ret, &env->fpu_status)); + return RET128(ret); } =20 /* convert 32-bit float to 128-bit float */ @@ -293,7 +293,7 @@ uint64_t HELPER(lxeb)(CPUS390XState *env, uint64_t f2) { float128 ret =3D float32_to_float128(f2, &env->fpu_status); handle_exceptions(env, GETPC()); - return RET128(float128_maybe_silence_nan(ret, &env->fpu_status)); + return RET128(ret); } =20 /* convert 64-bit float to 32-bit float */ @@ -301,7 +301,7 @@ uint64_t HELPER(ledb)(CPUS390XState *env, uint64_t f2) { float32 ret =3D float64_to_float32(f2, &env->fpu_status); handle_exceptions(env, GETPC()); - return float32_maybe_silence_nan(ret, &env->fpu_status); + return ret; } =20 /* convert 128-bit float to 32-bit float */ @@ -309,7 +309,7 @@ uint64_t HELPER(lexb)(CPUS390XState *env, uint64_t ah, = uint64_t al) { float32 ret =3D float128_to_float32(make_float128(ah, al), &env->fpu_s= tatus); handle_exceptions(env, GETPC()); - return float32_maybe_silence_nan(ret, &env->fpu_status); + return ret; } =20 /* 32-bit FP compare */ --=20 2.17.0 From nobody Wed Oct 29 23:02:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526337255048157.05344983030955; Mon, 14 May 2018 15:34:15 -0700 (PDT) Received: from localhost ([::1]:50369 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIM2o-0001Cq-6P for importer@patchew.org; Mon, 14 May 2018 18:34:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52604) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILi7-0008BF-Qe for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fILi6-0008D8-KQ for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:51 -0400 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:43161) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fILi6-0008BM-Eh for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:50 -0400 Received: by mail-pg0-x241.google.com with SMTP id p8-v6so2538834pgq.10 for ; Mon, 14 May 2018 15:12:50 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id y2-v6sm14512457pgp.92.2018.05.14.15.12.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 May 2018 15:12:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9z4EoWnekLIhRQCMjbOL53uOBSiOY08v6fsPvwdooRE=; b=fzmOaYfYonw1peGW5pSYesgsFxtBsoZdXwSn822MpCE/0s8zd/8iCa6VTrLver0M1a z0WceH7ScOg+XeBRe3mgUhYi3oE8r4ElsK+Vz7wozfB9ZHCxMmCgmt8uxP0trUL7UZ80 tATrtFY3tNohwp+N4wHkkY/Xaimw8jEr/YUnI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9z4EoWnekLIhRQCMjbOL53uOBSiOY08v6fsPvwdooRE=; b=rfnqBZXNdghenVWslyRO6dL1BDsUE7XYk2NijG3JtFQTMNdca4tman3zNq39e8mIr5 KMzTyLIX12w9yHy2P8y/ItlVvBJeOeUXEyrI4s+6C1Aup+w13t78Scmsl8d5QlD76Mav vp4DN9DJ6Tm97M5tvLs7DLcR7b//mvdP1SypTVztB/XVYAkPCGxkncx7Ieo7yiXu4gSi R0KHnU6038KPC4Cih8X0py4cl4p82VWkzRDlUhllciuQ7L1B5KlkZM6KfQbk3fmMy6HT 1gFFKslaxS28b4/CJ+zF6maJWVlFlZ4H7IDl8rdpMFhl3UfAMHTSYRSiFT/+kIrxTSvY 9ucA== X-Gm-Message-State: ALKqPweTM+WRRZO9vPvxjFUP9MACY0xH6xvXBCVKGLZLPhbkGL7eHXT+ kuNl5RCJpb6i+gNYbEsr/kAACm/flJk= X-Google-Smtp-Source: AB8JxZq/q6nzwNgKPwiE3ABZctIYSPBMJJhYvjPbk+Yd8QKG0WLBOKX2B2exwlVg5Teg2qamvszhEA== X-Received: by 2002:a63:a312:: with SMTP id s18-v6mr9680477pge.187.1526335969247; Mon, 14 May 2018 15:12:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 May 2018 15:12:11 -0700 Message-Id: <20180514221219.7091-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180514221219.7091-1-richard.henderson@linaro.org> References: <20180514221219.7091-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v5 20/28] fpu/softfloat: Use float*_silence_nan in propagateFloat*NaN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We have already checked the arguments for SNaN; we don't need to do it again. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Tested-by: Alex Benn=C3=A9e --- fpu/softfloat-specialize.h | 44 +++++++++++++++++++++++++++++--------- 1 file changed, 34 insertions(+), 10 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 995a0132c6..4fa068a5dc 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -498,7 +498,7 @@ static float32 commonNaNToFloat32(commonNaNT a, float_s= tatus *status) | The routine is passed various bits of information about the | two NaNs and should return 0 to select NaN a and 1 for NaN b. | Note that signalling NaNs are always squashed to quiet NaNs -| by the caller, by calling floatXX_maybe_silence_nan() before +| by the caller, by calling floatXX_silence_nan() before | returning them. | | aIsLargerSignificand is only valid if both a and b are NaNs @@ -536,7 +536,7 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIs= QNaN, flag bIsSNaN, { /* According to MIPS specifications, if one of the two operands is * a sNaN, a new qNaN has to be generated. This is done in - * floatXX_maybe_silence_nan(). For qNaN inputs the specifications + * floatXX_silence_nan(). For qNaN inputs the specifications * says: "When possible, this QNaN result is one of the operand QNaN * values." In practice it seems that most implementations choose * the first operand if both operands are qNaN. In short this gives @@ -788,9 +788,15 @@ static float32 propagateFloat32NaN(float32 a, float32 = b, float_status *status) =20 if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, aIsLargerSignificand)) { - return float32_maybe_silence_nan(b, status); + if (bIsSignalingNaN) { + return float32_silence_nan(b, status); + } + return b; } else { - return float32_maybe_silence_nan(a, status); + if (aIsSignalingNaN) { + return float32_silence_nan(a, status); + } + return a; } } =20 @@ -950,9 +956,15 @@ static float64 propagateFloat64NaN(float64 a, float64 = b, float_status *status) =20 if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, aIsLargerSignificand)) { - return float64_maybe_silence_nan(b, status); + if (bIsSignalingNaN) { + return float64_silence_nan(b, status); + } + return b; } else { - return float64_maybe_silence_nan(a, status); + if (aIsSignalingNaN) { + return float64_silence_nan(a, status); + } + return a; } } =20 @@ -1121,9 +1133,15 @@ floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b= , float_status *status) =20 if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, aIsLargerSignificand)) { - return floatx80_maybe_silence_nan(b, status); + if (bIsSignalingNaN) { + return floatx80_silence_nan(b, status); + } + return b; } else { - return floatx80_maybe_silence_nan(a, status); + if (aIsSignalingNaN) { + return floatx80_silence_nan(a, status); + } + return a; } } =20 @@ -1270,8 +1288,14 @@ static float128 propagateFloat128NaN(float128 a, flo= at128 b, =20 if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, aIsLargerSignificand)) { - return float128_maybe_silence_nan(b, status); + if (bIsSignalingNaN) { + return float128_silence_nan(b, status); + } + return b; } else { - return float128_maybe_silence_nan(a, status); + if (aIsSignalingNaN) { + return float128_silence_nan(a, status); + } + return a; } } --=20 2.17.0 From nobody Wed Oct 29 23:02:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526336823205941.7621600184655; Mon, 14 May 2018 15:27:03 -0700 (PDT) Received: from localhost ([::1]:49962 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILvq-0003Iq-BQ for importer@patchew.org; Mon, 14 May 2018 18:27:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52627) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILiB-0008EQ-92 for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fILi8-0008I9-A2 for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:55 -0400 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:36603) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fILi8-0008Fm-1U for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:52 -0400 Received: by mail-pg0-x241.google.com with SMTP id z70-v6so6065203pgz.3 for ; Mon, 14 May 2018 15:12:52 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id y2-v6sm14512457pgp.92.2018.05.14.15.12.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 May 2018 15:12:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=B0Uh1jzxOOh72JWGxxTuSXYGeNK1unJxmboGYXUn8YQ=; b=kwLuUYqelCeApgC2/82EFw58JgRfdbcIjaK/LV/qGFf+PZ2hrnrnS4UCPKPUePqt4J vaIZAs3R6Sx4Pwv06v5+pR8VZ/DGhpQWpF003+CKO5TQhQ2YqoIWW+or1tZXerfA81Nn 4vBlR1cx8F8yzZs58sf8WDhMzmLzUUGRV4zGc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=B0Uh1jzxOOh72JWGxxTuSXYGeNK1unJxmboGYXUn8YQ=; b=TLjrZlyjb1f0D7AUWfj6pLgibLbIoV3eOK47vpT6kApRxURxLmTvj5v9qzjwHxd5mm nXZLLQmXno8MxAT7zWEkZYht7Resc889T3gglR10fsZKZZPfln1aVOJFu8xYFtherkU3 q4b0c80lgwCDhk7z8RGmZUjUBm/MtA7t8POaKgbjFOtOPI8MOG7/K+FYNsh2JE5u/lJM 7wSM+bLNtTGd0+SDGybIW9rkS6EQZuE8TbgjkfVWYpYvl2pb7+K/GeZO6hYuYo1W2xZS XSNYdi5EfYOLE0O/e3Z28bqcIjtbt1PwM0LYup96n+IjeMuaNlN6vvhIh/2f7x+Xrwf/ HxYA== X-Gm-Message-State: ALKqPwcfIRFt98ymgN2VV7V6MELuUdL86H0SWLA3xCldFDdTfy1F5Vtj lSY+1m/2YTZIbAq4bk+CEbmKe3EuVxk= X-Google-Smtp-Source: AB8JxZpmYqDabqfvhmeLF68htb2yVcWX/VJeXj6fKdbEH2Fo91bsioHyn+jY/z+pzMU32AVoS0baIQ== X-Received: by 2002:a65:414c:: with SMTP id x12-v6mr9951469pgp.70.1526335970843; Mon, 14 May 2018 15:12:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 May 2018 15:12:12 -0700 Message-Id: <20180514221219.7091-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180514221219.7091-1-richard.henderson@linaro.org> References: <20180514221219.7091-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v5 21/28] fpu/softfloat: Remove floatX_maybe_silence_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These functions are now unused. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Tested-by: Alex Benn=C3=A9e --- fpu/softfloat-specialize.h | 63 -------------------------------------- include/fpu/softfloat.h | 5 --- 2 files changed, 68 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 4fa068a5dc..d7033b7757 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -364,19 +364,6 @@ float16 float16_silence_nan(float16 a, float_status *s= tatus) #endif } =20 -/*------------------------------------------------------------------------= ---- -| Returns a quiet NaN if the half-precision floating point value `a' is a -| signaling NaN; otherwise returns `a'. -*-------------------------------------------------------------------------= ---*/ - -float16 float16_maybe_silence_nan(float16 a, float_status *status) -{ - if (float16_is_signaling_nan(a, status)) { - return float16_silence_nan(a, status); - } - return a; -} - /*------------------------------------------------------------------------= ---- | Returns 1 if the single-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -438,18 +425,6 @@ float32 float32_silence_nan(float32 a, float_status *s= tatus) } #endif } -/*------------------------------------------------------------------------= ---- -| Returns a quiet NaN if the single-precision floating point value `a' is a -| signaling NaN; otherwise returns `a'. -*-------------------------------------------------------------------------= ---*/ - -float32 float32_maybe_silence_nan(float32 a, float_status *status) -{ - if (float32_is_signaling_nan(a, status)) { - return float32_silence_nan(a, status); - } - return a; -} =20 /*------------------------------------------------------------------------= ---- | Returns the result of converting the single-precision floating-point NaN @@ -864,18 +839,6 @@ float64 float64_silence_nan(float64 a, float_status *s= tatus) #endif } =20 -/*------------------------------------------------------------------------= ---- -| Returns a quiet NaN if the double-precision floating point value `a' is a -| signaling NaN; otherwise returns `a'. -*-------------------------------------------------------------------------= ---*/ - -float64 float64_maybe_silence_nan(float64 a, float_status *status) -{ - if (float64_is_signaling_nan(a, status)) { - return float64_silence_nan(a, status); - } - return a; -} =20 /*------------------------------------------------------------------------= ---- | Returns the result of converting the double-precision floating-point NaN @@ -1037,19 +1000,6 @@ floatx80 floatx80_silence_nan(floatx80 a, float_stat= us *status) #endif } =20 -/*------------------------------------------------------------------------= ---- -| Returns a quiet NaN if the extended double-precision floating point value -| `a' is a signaling NaN; otherwise returns `a'. -*-------------------------------------------------------------------------= ---*/ - -floatx80 floatx80_maybe_silence_nan(floatx80 a, float_status *status) -{ - if (floatx80_is_signaling_nan(a, status)) { - return floatx80_silence_nan(a, status); - } - return a; -} - /*------------------------------------------------------------------------= ---- | Returns the result of converting the extended double-precision floating- | point NaN `a' to the canonical NaN format. If `a' is a signaling NaN, t= he @@ -1204,19 +1154,6 @@ float128 float128_silence_nan(float128 a, float_stat= us *status) #endif } =20 -/*------------------------------------------------------------------------= ---- -| Returns a quiet NaN if the quadruple-precision floating point value `a' = is -| a signaling NaN; otherwise returns `a'. -*-------------------------------------------------------------------------= ---*/ - -float128 float128_maybe_silence_nan(float128 a, float_status *status) -{ - if (float128_is_signaling_nan(a, status)) { - return float128_silence_nan(a, status); - } - return a; -} - /*------------------------------------------------------------------------= ---- | Returns the result of converting the quadruple-precision floating-point = NaN | `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index a6860e858d..69f4dbc4db 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -258,7 +258,6 @@ int float16_compare_quiet(float16, float16, float_statu= s *status); int float16_is_quiet_nan(float16, float_status *status); int float16_is_signaling_nan(float16, float_status *status); float16 float16_silence_nan(float16, float_status *status); -float16 float16_maybe_silence_nan(float16, float_status *status); =20 static inline int float16_is_any_nan(float16 a) { @@ -370,7 +369,6 @@ float32 float32_maxnummag(float32, float32, float_statu= s *status); int float32_is_quiet_nan(float32, float_status *status); int float32_is_signaling_nan(float32, float_status *status); float32 float32_silence_nan(float32, float_status *status); -float32 float32_maybe_silence_nan(float32, float_status *status); float32 float32_scalbn(float32, int, float_status *status); =20 static inline float32 float32_abs(float32 a) @@ -500,7 +498,6 @@ float64 float64_maxnummag(float64, float64, float_statu= s *status); int float64_is_quiet_nan(float64 a, float_status *status); int float64_is_signaling_nan(float64, float_status *status); float64 float64_silence_nan(float64, float_status *status); -float64 float64_maybe_silence_nan(float64, float_status *status); float64 float64_scalbn(float64, int, float_status *status); =20 static inline float64 float64_abs(float64 a) @@ -604,7 +601,6 @@ int floatx80_compare_quiet(floatx80, floatx80, float_st= atus *status); int floatx80_is_quiet_nan(floatx80, float_status *status); int floatx80_is_signaling_nan(floatx80, float_status *status); floatx80 floatx80_silence_nan(floatx80, float_status *status); -floatx80 floatx80_maybe_silence_nan(floatx80, float_status *status); floatx80 floatx80_scalbn(floatx80, int, float_status *status); =20 static inline floatx80 floatx80_abs(floatx80 a) @@ -816,7 +812,6 @@ int float128_compare_quiet(float128, float128, float_st= atus *status); int float128_is_quiet_nan(float128, float_status *status); int float128_is_signaling_nan(float128, float_status *status); float128 float128_silence_nan(float128, float_status *status); -float128 float128_maybe_silence_nan(float128, float_status *status); float128 float128_scalbn(float128, int, float_status *status); =20 static inline float128 float128_abs(float128 a) --=20 2.17.0 From nobody Wed Oct 29 23:02:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526337455855672.5419714731594; Mon, 14 May 2018 15:37:35 -0700 (PDT) Received: from localhost ([::1]:50615 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIM5r-0004AQ-Ap for importer@patchew.org; Mon, 14 May 2018 18:37:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52633) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILiB-0008Ev-OK for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fILi9-0008LB-L2 for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:55 -0400 Received: from mail-pl0-x243.google.com ([2607:f8b0:400e:c01::243]:45884) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fILi9-0008JX-BT for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:53 -0400 Received: by mail-pl0-x243.google.com with SMTP id bi12-v6so8144440plb.12 for ; Mon, 14 May 2018 15:12:53 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id y2-v6sm14512457pgp.92.2018.05.14.15.12.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 May 2018 15:12:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=t7/aog2Cky4Dgm8gVOdXWM/mBfrK88ILxMNiYMKbySQ=; b=YvcqHjI/SBE4oANPVDbI9Vb2vhSD/WKIbA6ZPSHOzq8QuFgkmjEW1QHeSpewb5/pIs wAwhF625nX2vSd+mAtPFR4XC7R5y0wrkrAeyf14NepTL4GxagnJpoH/WjaBcJbhVfjEX Vh07VuXtL9fuKplsN97rB+CUJQ4eS9pKpv56s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=t7/aog2Cky4Dgm8gVOdXWM/mBfrK88ILxMNiYMKbySQ=; b=I/JIej8UEo6F9IfugsF/qHWsEVLjG/QCG+mib3cZiqBwHGwxgF0kwOhiPxb+Uo5R1U bZITKSBH9B6dCFsNRHfpHFnS1rRfB5p0fIggOSewg0YA9IRLy7CjowkFtfEZXUnU9Uvv ZVJGUApOdaqnjatLO+VcIRQonuBwjwS8CUwsri+gC3PSUo9IWm5AP/a5S4Yd7qoU0SZA Jj/4QzYK4Fq9eLWNQE7yAZvWyyJlJ5BWDvac9uhLaWdNhj2QGSXyPsQIA79iMHvgH11o jU4WghPgxlcBJKzxHSnalcMexJ1oxyKzI9mcdTQP+B+TuJJE3t9fzPqqtyYYsupgVnCJ QSoA== X-Gm-Message-State: ALKqPwdTg38vomD/rPZrinDetzpCxDAz+6HZXvB5FWfeW5dbv3ZZCTuC NXwEW61KtKCQCP9vy7XWTZppb9m2duY= X-Google-Smtp-Source: AB8JxZqBRHRrYiVV6wvEIRAcNlLFOlm8T4zIDPeF4EYrjOea/kLDcnccH09uBw/JRrASTSdPXcthOA== X-Received: by 2002:a17:902:8a95:: with SMTP id p21-v6mr11737484plo.325.1526335972146; Mon, 14 May 2018 15:12:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 May 2018 15:12:13 -0700 Message-Id: <20180514221219.7091-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180514221219.7091-1-richard.henderson@linaro.org> References: <20180514221219.7091-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v5 22/28] fpu/softfloat: Specialize on snan_bit_is_one X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, Alexander Graf , Guan Xuetao , Yongbok Kim , Aurelien Jarno , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Only MIPS requires snan_bit_is_one to be variable. While we are specializing softfloat behaviour, allow other targets to eliminate this runtime check. Cc: Aurelien Jarno Cc: Yongbok Kim Cc: David Gibson Cc: Alexander Graf Cc: Guan Xuetao Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Tested-by: Alex Benn=C3=A9e --- v5 - do not remove the set_snan_bit_is_one function - tidy the language in the snan_bit_is_one block comment --- fpu/softfloat-specialize.h | 68 ++++++++++++++++++++++------------- include/fpu/softfloat-types.h | 1 + target/hppa/cpu.c | 1 - target/ppc/fpu_helper.c | 1 - target/sh4/cpu.c | 1 - target/unicore32/cpu.c | 2 -- 6 files changed, 44 insertions(+), 30 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index d7033b7757..d1e06da75b 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -79,13 +79,31 @@ this code that are retained. * version 2 or later. See the COPYING file in the top-level directory. */ =20 -#if defined(TARGET_XTENSA) /* Define for architectures which deviate from IEEE in not supporting * signaling NaNs (so all NaNs are treated as quiet). */ +#if defined(TARGET_XTENSA) #define NO_SIGNALING_NANS 1 #endif =20 +/* Define how the architecture discriminates signaling NaNs. + * This done with the most significant bit of the fraction. + * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008 + * the msb must be zero. MIPS is (so far) unique in supporting both the + * 2008 revision and backward compatibility with their original choice. + * Thus for MIPS we must make the choice at runtime. + */ +static inline flag snan_bit_is_one(float_status *status) +{ +#if defined(TARGET_MIPS) + return status->snan_bit_is_one; +#elif defined(TARGET_HPPA) || defined(TARGET_UNICORE32) || defined(TARGET_= SH4) + return 1; +#else + return 0; +#endif +} + /*------------------------------------------------------------------------= ---- | For the deconstructed floating-point with fraction FRAC, return true | if the fraction represents a signalling NaN; otherwise false. @@ -97,7 +115,7 @@ static bool parts_is_snan_frac(uint64_t frac, float_stat= us *status) return false; #else flag msb =3D extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1); - return msb =3D=3D status->snan_bit_is_one; + return msb =3D=3D snan_bit_is_one(status); #endif } =20 @@ -118,7 +136,7 @@ static FloatParts parts_default_nan(float_status *statu= s) #elif defined(TARGET_HPPA) frac =3D 1ULL << (DECOMPOSED_BINARY_POINT - 2); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { frac =3D (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; } else { #if defined(TARGET_MIPS) @@ -151,7 +169,7 @@ static FloatParts parts_silence_nan(FloatParts a, float= _status *status) a.frac &=3D ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); a.frac |=3D 1ULL << (DECOMPOSED_BINARY_POINT - 2); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return parts_default_nan(status); } else { a.frac |=3D 1ULL << (DECOMPOSED_BINARY_POINT - 1); @@ -169,7 +187,7 @@ float16 float16_default_nan(float_status *status) #if defined(TARGET_ARM) return const_float16(0x7E00); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return const_float16(0x7DFF); } else { #if defined(TARGET_MIPS) @@ -195,7 +213,7 @@ float32 float32_default_nan(float_status *status) #elif defined(TARGET_HPPA) return const_float32(0x7FA00000); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return const_float32(0x7FBFFFFF); } else { #if defined(TARGET_MIPS) @@ -220,7 +238,7 @@ float64 float64_default_nan(float_status *status) #elif defined(TARGET_HPPA) return const_float64(LIT64(0x7FF4000000000000)); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return const_float64(LIT64(0x7FF7FFFFFFFFFFFF)); } else { #if defined(TARGET_MIPS) @@ -242,7 +260,7 @@ floatx80 floatx80_default_nan(float_status *status) r.low =3D LIT64(0xFFFFFFFFFFFFFFFF); r.high =3D 0x7FFF; #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { r.low =3D LIT64(0xBFFFFFFFFFFFFFFF); r.high =3D 0x7FFF; } else { @@ -274,7 +292,7 @@ float128 float128_default_nan(float_status *status) { float128 r; =20 - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { r.low =3D LIT64(0xFFFFFFFFFFFFFFFF); r.high =3D LIT64(0x7FFF7FFFFFFFFFFF); } else { @@ -319,7 +337,7 @@ int float16_is_quiet_nan(float16 a_, float_status *stat= us) return float16_is_any_nan(a_); #else uint16_t a =3D float16_val(a_); - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return (((a >> 9) & 0x3F) =3D=3D 0x3E) && (a & 0x1FF); } else { return ((a & ~0x8000) >=3D 0x7C80); @@ -338,7 +356,7 @@ int float16_is_signaling_nan(float16 a_, float_status *= status) return 0; #else uint16_t a =3D float16_val(a_); - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return ((a & ~0x8000) >=3D 0x7C80); } else { return (((a >> 9) & 0x3F) =3D=3D 0x3E) && (a & 0x1FF); @@ -356,7 +374,7 @@ float16 float16_silence_nan(float16 a, float_status *st= atus) #ifdef NO_SIGNALING_NANS g_assert_not_reached(); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return float16_default_nan(status); } else { return a | (1 << 9); @@ -375,7 +393,7 @@ int float32_is_quiet_nan(float32 a_, float_status *stat= us) return float32_is_any_nan(a_); #else uint32_t a =3D float32_val(a_); - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return (((a >> 22) & 0x1FF) =3D=3D 0x1FE) && (a & 0x003FFFFF); } else { return ((uint32_t)(a << 1) >=3D 0xFF800000); @@ -394,7 +412,7 @@ int float32_is_signaling_nan(float32 a_, float_status *= status) return 0; #else uint32_t a =3D float32_val(a_); - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return ((uint32_t)(a << 1) >=3D 0xFF800000); } else { return (((a >> 22) & 0x1FF) =3D=3D 0x1FE) && (a & 0x003FFFFF); @@ -412,7 +430,7 @@ float32 float32_silence_nan(float32 a, float_status *st= atus) #ifdef NO_SIGNALING_NANS g_assert_not_reached(); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { # ifdef TARGET_HPPA a &=3D ~0x00400000; a |=3D 0x00200000; @@ -651,7 +669,7 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, fl= ag bIsQNaN, flag bIsSNaN, return 3; } =20 - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { /* Prefer sNaN over qNaN, in the a, b, c order. */ if (aIsSNaN) { return 0; @@ -786,7 +804,7 @@ int float64_is_quiet_nan(float64 a_, float_status *stat= us) return float64_is_any_nan(a_); #else uint64_t a =3D float64_val(a_); - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return (((a >> 51) & 0xFFF) =3D=3D 0xFFE) && (a & 0x0007FFFFFFFFFFFFULL); } else { @@ -806,7 +824,7 @@ int float64_is_signaling_nan(float64 a_, float_status *= status) return 0; #else uint64_t a =3D float64_val(a_); - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return ((a << 1) >=3D 0xFFF0000000000000ULL); } else { return (((a >> 51) & 0xFFF) =3D=3D 0xFFE) @@ -825,7 +843,7 @@ float64 float64_silence_nan(float64 a, float_status *st= atus) #ifdef NO_SIGNALING_NANS g_assert_not_reached(); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { # ifdef TARGET_HPPA a &=3D ~0x0008000000000000ULL; a |=3D 0x0004000000000000ULL; @@ -942,7 +960,7 @@ int floatx80_is_quiet_nan(floatx80 a, float_status *sta= tus) #ifdef NO_SIGNALING_NANS return floatx80_is_any_nan(a); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { uint64_t aLow; =20 aLow =3D a.low & ~0x4000000000000000ULL; @@ -967,7 +985,7 @@ int floatx80_is_signaling_nan(floatx80 a, float_status = *status) #ifdef NO_SIGNALING_NANS return 0; #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return ((a.high & 0x7FFF) =3D=3D 0x7FFF) && ((a.low << 1) >=3D 0x8000000000000000ULL); } else { @@ -991,7 +1009,7 @@ floatx80 floatx80_silence_nan(floatx80 a, float_status= *status) #ifdef NO_SIGNALING_NANS g_assert_not_reached(); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return floatx80_default_nan(status); } else { a.low |=3D LIT64(0xC000000000000000); @@ -1105,7 +1123,7 @@ int float128_is_quiet_nan(float128 a, float_status *s= tatus) #ifdef NO_SIGNALING_NANS return float128_is_any_nan(a); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return (((a.high >> 47) & 0xFFFF) =3D=3D 0xFFFE) && (a.low || (a.high & 0x00007FFFFFFFFFFFULL)); } else { @@ -1125,7 +1143,7 @@ int float128_is_signaling_nan(float128 a, float_statu= s *status) #ifdef NO_SIGNALING_NANS return 0; #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return ((a.high << 1) >=3D 0xFFFF000000000000ULL) && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); } else { @@ -1145,7 +1163,7 @@ float128 float128_silence_nan(float128 a, float_statu= s *status) #ifdef NO_SIGNALING_NANS g_assert_not_reached(); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return float128_default_nan(status); } else { a.high |=3D LIT64(0x0000800000000000); diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 4e378cb612..2aae6a89b1 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -173,6 +173,7 @@ typedef struct float_status { /* should denormalised inputs go to zero and set the input_denormal fl= ag? */ flag flush_inputs_to_zero; flag default_nan_mode; + /* not always used -- see snan_bit_is_one() in softfloat-specialize.h = */ flag snan_bit_is_one; } float_status; =20 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index c261b6b090..00bf444620 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -141,7 +141,6 @@ static void hppa_cpu_initfn(Object *obj) cs->env_ptr =3D env; cs->exception_index =3D -1; cpu_hppa_loaded_fr0(env); - set_snan_bit_is_one(true, &env->fp_status); cpu_hppa_put_psw(env, PSW_W); } =20 diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 9ae418a577..d31a933cbb 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -3382,7 +3382,6 @@ void helper_xssqrtqp(CPUPPCState *env, uint32_t opcod= e) xt.f128 =3D xb.f128; } else if (float128_is_neg(xb.f128) && !float128_is_zero(xb.f128))= { float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1); - set_snan_bit_is_one(0, &env->fp_status); xt.f128 =3D float128_default_nan(&env->fp_status); } } diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 541ffc2d97..b9f393b7c7 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -71,7 +71,6 @@ static void superh_cpu_reset(CPUState *s) set_flush_to_zero(1, &env->fp_status); #endif set_default_nan_mode(1, &env->fp_status); - set_snan_bit_is_one(1, &env->fp_status); } =20 static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *inf= o) diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 29d160a88d..68f978d80b 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -70,7 +70,6 @@ static void unicore_ii_cpu_initfn(Object *obj) =20 set_feature(env, UC32_HWCAP_CMOV); set_feature(env, UC32_HWCAP_UCF64); - set_snan_bit_is_one(1, &env->ucf64.fp_status); } =20 static void uc32_any_cpu_initfn(Object *obj) @@ -83,7 +82,6 @@ static void uc32_any_cpu_initfn(Object *obj) =20 set_feature(env, UC32_HWCAP_CMOV); set_feature(env, UC32_HWCAP_UCF64); - set_snan_bit_is_one(1, &env->ucf64.fp_status); } =20 static void uc32_cpu_realizefn(DeviceState *dev, Error **errp) --=20 2.17.0 From nobody Wed Oct 29 23:02:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526337617447486.1247318612694; Mon, 14 May 2018 15:40:17 -0700 (PDT) Received: from localhost ([::1]:50807 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIM8e-0006ng-IV for importer@patchew.org; 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X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH v5 23/28] fpu/softfloat: Make is_nan et al available to softfloat-specialize.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We will need these helpers within softfloat-specialize.h, so move the definitions above the include. After specialization, they will not always be used so mark them to avoid the Werror. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Tested-by: Alex Benn=C3=A9e --- fpu/softfloat.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index e9e421728b..9934adbae5 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -181,6 +181,22 @@ typedef enum __attribute__ ((__packed__)) { float_class_snan, } FloatClass; =20 +/* Simple helpers for checking if, or what kind of, NaN we have */ +static inline __attribute__((unused)) bool is_nan(FloatClass c) +{ + return unlikely(c >=3D float_class_qnan); +} + +static inline __attribute__((unused)) bool is_snan(FloatClass c) +{ + return c =3D=3D float_class_snan; +} + +static inline __attribute__((unused)) bool is_qnan(FloatClass c) +{ + return c =3D=3D float_class_qnan; +} + /* * Structure holding all of the decomposed parts of a float. The * exponent is unbiased and the fraction is normalized. All @@ -536,20 +552,6 @@ static float64 float64_round_pack_canonical(FloatParts= p, float_status *s) return float64_pack_raw(round_canonical(p, s, &float64_params)); } =20 -/* Simple helpers for checking if what NaN we have */ -static bool is_nan(FloatClass c) -{ - return unlikely(c >=3D float_class_qnan); -} -static bool is_snan(FloatClass c) -{ - return c =3D=3D float_class_snan; -} -static bool is_qnan(FloatClass c) -{ - return c =3D=3D float_class_qnan; -} - static FloatParts return_nan(FloatParts a, float_status *s) { switch (a.cls) { --=20 2.17.0 From nobody Wed Oct 29 23:02:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526337754553202.08402303276887; Mon, 14 May 2018 15:42:34 -0700 (PDT) Received: from localhost ([::1]:50929 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIMAk-0000J6-O4 for importer@patchew.org; Mon, 14 May 2018 18:42:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52666) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILiE-0008GD-Di for qemu-devel@nongnu.org; Mon, 14 May 2018 18:13:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fILiC-0008SK-CB for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:58 -0400 Received: from mail-pl0-x241.google.com ([2607:f8b0:400e:c01::241]:33642) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fILiC-0008QU-3h for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:56 -0400 Received: by mail-pl0-x241.google.com with SMTP id n10-v6so8155722plp.0 for ; Mon, 14 May 2018 15:12:56 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id y2-v6sm14512457pgp.92.2018.05.14.15.12.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 May 2018 15:12:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AEMxNIHQs7jJxtdv+SUmM5dUZKPGuUubR9YypD1/cP8=; b=Zrp17ppCTT8eOqgRsutWvp67wAT/x6j3BTswt2EbR6QuxPl3ZU01wdeN8OG7u+UVGy AueKvGi2ptXcKAS6ENkFtBht3GaW9gz192gKI6D4q2BJMc406DFNDyyvY5ZjY88IkOnA CKe+hcAMknStb31tY51XRp60MdroUVQBiTh/Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AEMxNIHQs7jJxtdv+SUmM5dUZKPGuUubR9YypD1/cP8=; b=Ntz9vBoiKV4Ju2Br73bh/+uJyFC6TaNRDxofqX5imhe6RGSnFoxit2nus3k9N/GlpH 7HPtxFzG6WlB+fbZTnyHV1a+ko1SDlwJosw/WRMBt+kh4DPpl71ERTxjB50nNdF1BkgE LG/OstD4l4ajoXt+hfmfJaypYXY4n9yN1YD1XxOK5wFaR29OGEShCw0rd17cm983COk6 h5MBOVdjNveuj3n5iNXJbF8qC1jgbNYUH+txRIz7o72Kbxf2kTpzosWDPgpKT3KJFteh OJSe28EuA2yHvm1X699/piK33wz+uCa60kWuRGpSex94ioBEGiGD8DS22O7piCEsHOo5 +T8Q== X-Gm-Message-State: ALKqPwdypgWMC6tF/AQhhZ7yQ3hJeqp1oGPY5/EMuUCjnnxZvIg7OUdN hierB6QYcIHsSB9xyJtVF/EAnc55A5k= X-Google-Smtp-Source: AB8JxZoG5/W9KpNwo8UZy2cmhHXhwc3znYCDy6cD7TQMXmFlXg3M1JcSX6Gs1ou67xDstnz5t5Nl0A== X-Received: by 2002:a17:902:4303:: with SMTP id i3-v6mr11889953pld.394.1526335974681; Mon, 14 May 2018 15:12:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 May 2018 15:12:15 -0700 Message-Id: <20180514221219.7091-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180514221219.7091-1-richard.henderson@linaro.org> References: <20180514221219.7091-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH v5 24/28] fpu/softfloat: Pass FloatClass to pickNaN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For each operand, pass a single enumeration instead of a pair of booleans. The commit also merges multiple different ifdef-selected implementations of pickNaN into a single function whose body is ifdef-selected. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- fpu/softfloat-specialize.h | 168 ++++++++++++++++++------------------- fpu/softfloat.c | 3 +- 2 files changed, 82 insertions(+), 89 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index d1e06da75b..2695183188 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -501,10 +501,10 @@ static float32 commonNaNToFloat32(commonNaNT a, float= _status *status) | tie-break rule. *-------------------------------------------------------------------------= ---*/ =20 -#if defined(TARGET_ARM) -static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, +static int pickNaN(FloatClass a_cls, FloatClass b_cls, flag aIsLargerSignificand) { +#if defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA) /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take * the first of: * 1. A if it is signaling @@ -513,20 +513,6 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bI= sQNaN, flag bIsSNaN, * 4. B (quiet) * A signaling NaN is always quietened before returning it. */ - if (aIsSNaN) { - return 0; - } else if (bIsSNaN) { - return 1; - } else if (aIsQNaN) { - return 0; - } else { - return 1; - } -} -#elif defined(TARGET_MIPS) || defined(TARGET_HPPA) -static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag aIsLargerSignificand) -{ /* According to MIPS specifications, if one of the two operands is * a sNaN, a new qNaN has to be generated. This is done in * floatXX_silence_nan(). For qNaN inputs the specifications @@ -540,35 +526,21 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag b= IsQNaN, flag bIsSNaN, * 4. B (quiet) * A signaling NaN is always silenced before returning it. */ - if (aIsSNaN) { + if (is_snan(a_cls)) { return 0; - } else if (bIsSNaN) { + } else if (is_snan(b_cls)) { return 1; - } else if (aIsQNaN) { + } else if (is_qnan(a_cls)) { return 0; } else { return 1; } -} -#elif defined(TARGET_PPC) || defined(TARGET_XTENSA) -static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag aIsLargerSignificand) -{ +#elif defined(TARGET_PPC) || defined(TARGET_XTENSA) || defined(TARGET_M68K) /* PowerPC propagation rules: * 1. A if it sNaN or qNaN * 2. B if it sNaN or qNaN * A signaling NaN is always silenced before returning it. */ - if (aIsSNaN || aIsQNaN) { - return 0; - } else { - return 1; - } -} -#elif defined(TARGET_M68K) -static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag aIsLargerSignificand) -{ /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL * 3.4 FLOATING-POINT INSTRUCTION DETAILS * If either operand, but not both operands, of an operation is a @@ -583,16 +555,12 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag b= IsQNaN, flag bIsSNaN, * a nonsignaling NaN. The operation then continues as described in the * preceding paragraph for nonsignaling NaNs. */ - if (aIsQNaN || aIsSNaN) { /* a is the destination operand */ - return 0; /* return the destination operand */ + if (is_nan(a_cls)) { + return 0; } else { - return 1; /* return b */ + return 1; } -} #else -static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag aIsLargerSignificand) -{ /* This implements x87 NaN propagation rules: * SNaN + QNaN =3D> return the QNaN * two SNaNs =3D> return the one with the larger significand, silenced @@ -603,13 +571,13 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag b= IsQNaN, flag bIsSNaN, * If we get down to comparing significands and they are the same, * return the NaN with the positive sign bit (if any). */ - if (aIsSNaN) { - if (bIsSNaN) { + if (is_snan(a_cls)) { + if (is_snan(b_cls)) { return aIsLargerSignificand ? 0 : 1; } - return bIsQNaN ? 1 : 0; - } else if (aIsQNaN) { - if (bIsSNaN || !bIsQNaN) { + return is_qnan(b_cls) ? 1 : 0; + } else if (is_qnan(a_cls)) { + if (is_snan(b_cls) || !is_qnan(b_cls)) { return 0; } else { return aIsLargerSignificand ? 0 : 1; @@ -617,8 +585,8 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIs= QNaN, flag bIsSNaN, } else { return 1; } -} #endif +} =20 /*------------------------------------------------------------------------= ---- | Select which NaN to propagate for a three-input operation. @@ -752,18 +720,26 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, = flag bIsQNaN, flag bIsSNaN, =20 static float32 propagateFloat32NaN(float32 a, float32 b, float_status *sta= tus) { - flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN; flag aIsLargerSignificand; uint32_t av, bv; + FloatClass a_cls, b_cls; + + /* This is not complete, but is good enough for pickNaN. */ + a_cls =3D (!float32_is_any_nan(a) + ? float_class_normal + : float32_is_signaling_nan(a, status) + ? float_class_snan + : float_class_qnan); + b_cls =3D (!float32_is_any_nan(b) + ? float_class_normal + : float32_is_signaling_nan(b, status) + ? float_class_snan + : float_class_qnan); =20 - aIsQuietNaN =3D float32_is_quiet_nan(a, status); - aIsSignalingNaN =3D float32_is_signaling_nan(a, status); - bIsQuietNaN =3D float32_is_quiet_nan(b, status); - bIsSignalingNaN =3D float32_is_signaling_nan(b, status); av =3D float32_val(a); bv =3D float32_val(b); =20 - if (aIsSignalingNaN | bIsSignalingNaN) { + if (is_snan(a_cls) || is_snan(b_cls)) { float_raise(float_flag_invalid, status); } =20 @@ -779,14 +755,13 @@ static float32 propagateFloat32NaN(float32 a, float32= b, float_status *status) aIsLargerSignificand =3D (av < bv) ? 1 : 0; } =20 - if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, - aIsLargerSignificand)) { - if (bIsSignalingNaN) { + if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { + if (is_snan(b_cls)) { return float32_silence_nan(b, status); } return b; } else { - if (aIsSignalingNaN) { + if (is_snan(a_cls)) { return float32_silence_nan(a, status); } return a; @@ -908,18 +883,26 @@ static float64 commonNaNToFloat64(commonNaNT a, float= _status *status) =20 static float64 propagateFloat64NaN(float64 a, float64 b, float_status *sta= tus) { - flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN; flag aIsLargerSignificand; uint64_t av, bv; + FloatClass a_cls, b_cls; + + /* This is not complete, but is good enough for pickNaN. */ + a_cls =3D (!float64_is_any_nan(a) + ? float_class_normal + : float64_is_signaling_nan(a, status) + ? float_class_snan + : float_class_qnan); + b_cls =3D (!float64_is_any_nan(b) + ? float_class_normal + : float64_is_signaling_nan(b, status) + ? float_class_snan + : float_class_qnan); =20 - aIsQuietNaN =3D float64_is_quiet_nan(a, status); - aIsSignalingNaN =3D float64_is_signaling_nan(a, status); - bIsQuietNaN =3D float64_is_quiet_nan(b, status); - bIsSignalingNaN =3D float64_is_signaling_nan(b, status); av =3D float64_val(a); bv =3D float64_val(b); =20 - if (aIsSignalingNaN | bIsSignalingNaN) { + if (is_snan(a_cls) || is_snan(b_cls)) { float_raise(float_flag_invalid, status); } =20 @@ -935,14 +918,13 @@ static float64 propagateFloat64NaN(float64 a, float64= b, float_status *status) aIsLargerSignificand =3D (av < bv) ? 1 : 0; } =20 - if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, - aIsLargerSignificand)) { - if (bIsSignalingNaN) { + if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { + if (is_snan(b_cls)) { return float64_silence_nan(b, status); } return b; } else { - if (aIsSignalingNaN) { + if (is_snan(a_cls)) { return float64_silence_nan(a, status); } return a; @@ -1075,15 +1057,22 @@ static floatx80 commonNaNToFloatx80(commonNaNT a, f= loat_status *status) =20 floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) { - flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN; flag aIsLargerSignificand; + FloatClass a_cls, b_cls; =20 - aIsQuietNaN =3D floatx80_is_quiet_nan(a, status); - aIsSignalingNaN =3D floatx80_is_signaling_nan(a, status); - bIsQuietNaN =3D floatx80_is_quiet_nan(b, status); - bIsSignalingNaN =3D floatx80_is_signaling_nan(b, status); + /* This is not complete, but is good enough for pickNaN. */ + a_cls =3D (!floatx80_is_any_nan(a) + ? float_class_normal + : floatx80_is_signaling_nan(a, status) + ? float_class_snan + : float_class_qnan); + b_cls =3D (!floatx80_is_any_nan(b) + ? float_class_normal + : floatx80_is_signaling_nan(b, status) + ? float_class_snan + : float_class_qnan); =20 - if (aIsSignalingNaN | bIsSignalingNaN) { + if (is_snan(a_cls) || is_snan(b_cls)) { float_raise(float_flag_invalid, status); } =20 @@ -1099,14 +1088,13 @@ floatx80 propagateFloatx80NaN(floatx80 a, floatx80 = b, float_status *status) aIsLargerSignificand =3D (a.high < b.high) ? 1 : 0; } =20 - if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, - aIsLargerSignificand)) { - if (bIsSignalingNaN) { + if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { + if (is_snan(b_cls)) { return floatx80_silence_nan(b, status); } return b; } else { - if (aIsSignalingNaN) { + if (is_snan(a_cls)) { return floatx80_silence_nan(a, status); } return a; @@ -1217,15 +1205,22 @@ static float128 commonNaNToFloat128(commonNaNT a, f= loat_status *status) static float128 propagateFloat128NaN(float128 a, float128 b, float_status *status) { - flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN; flag aIsLargerSignificand; + FloatClass a_cls, b_cls; =20 - aIsQuietNaN =3D float128_is_quiet_nan(a, status); - aIsSignalingNaN =3D float128_is_signaling_nan(a, status); - bIsQuietNaN =3D float128_is_quiet_nan(b, status); - bIsSignalingNaN =3D float128_is_signaling_nan(b, status); + /* This is not complete, but is good enough for pickNaN. */ + a_cls =3D (!float128_is_any_nan(a) + ? float_class_normal + : float128_is_signaling_nan(a, status) + ? float_class_snan + : float_class_qnan); + b_cls =3D (!float128_is_any_nan(b) + ? float_class_normal + : float128_is_signaling_nan(b, status) + ? float_class_snan + : float_class_qnan); =20 - if (aIsSignalingNaN | bIsSignalingNaN) { + if (is_snan(a_cls) || is_snan(b_cls)) { float_raise(float_flag_invalid, status); } =20 @@ -1241,14 +1236,13 @@ static float128 propagateFloat128NaN(float128 a, fl= oat128 b, aIsLargerSignificand =3D (a.high < b.high) ? 1 : 0; } =20 - if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, - aIsLargerSignificand)) { - if (bIsSignalingNaN) { + if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { + if (is_snan(b_cls)) { return float128_silence_nan(b, status); } return b; } else { - if (aIsSignalingNaN) { + if (is_snan(a_cls)) { return float128_silence_nan(a, status); } return a; diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 9934adbae5..43264fa1f6 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -580,8 +580,7 @@ static FloatParts pick_nan(FloatParts a, FloatParts b, = float_status *s) if (s->default_nan_mode) { return parts_default_nan(s); } else { - if (pickNaN(is_qnan(a.cls), is_snan(a.cls), - is_qnan(b.cls), is_snan(b.cls), + if (pickNaN(a.cls, b.cls, a.frac > b.frac || (a.frac =3D=3D b.frac && a.sign < b.sign))) { a =3D b; --=20 2.17.0 From nobody Wed Oct 29 23:02:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526337005511899.7702994853792; Mon, 14 May 2018 15:30:05 -0700 (PDT) Received: from localhost ([::1]:49983 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILyd-0005on-3e for importer@patchew.org; Mon, 14 May 2018 18:29:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52678) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILiF-0008GF-5f for qemu-devel@nongnu.org; Mon, 14 May 2018 18:13:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fILiD-0008Vn-M1 for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:59 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:40810) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fILiD-0008Tl-Dy for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:57 -0400 Received: by mail-pf0-x242.google.com with SMTP id f189-v6so6668320pfa.7 for ; Mon, 14 May 2018 15:12:57 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id y2-v6sm14512457pgp.92.2018.05.14.15.12.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 May 2018 15:12:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6WuZ9p/7jNL+hLMOjd4yPOus0eQnm6/8jO4I9mebAGw=; b=YWW+5kIxaZXUUKq4PgJcLnv9QX1aexikvnpfJyULyC/kLpA0MvcYNlcpbG3wTYRR8l S7+YtUumN3VLQ0LYzRFME3js9X34rXlwO9SMwoWe1YRBu9RDHNxFQk1ILiwpxj89bf8h L692iDCQrhDQWNwCtdogUUA2kwW0C5oSlDr/0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6WuZ9p/7jNL+hLMOjd4yPOus0eQnm6/8jO4I9mebAGw=; b=mVh0/I9j8E0sAj3sOuNfw83lFZR+AI65YjaFlx3hxWVHF2XTc5jUWFvx/kWf6Cq6s3 y7wMYNpyUY9Ml0xr4BFqqzvd57w47fY1XskxYv2AeO9toq2LTN8lERBbLB3UESSltu3F 3mEAsMoLoc83DxiCztmwa3W2+wb6TpFAlzzf8Iey1womZ4zlLq6fNxz5FBovP+U4AR1m u9jbHtAx9bJxZy4SmH8B/+gNS4a7OtbrKhT+ndEOCAuPg8df+HIHTkaUuVH4aUBFnRpM DFP/qU6A6/XZZzxf7MzEm5vofsg6V5cTJZCxrLBZDG5SeBbSqzZOLWMIMfBdJ743Rc+k LOYg== X-Gm-Message-State: ALKqPwf1rLXWA+Wfl2+OB6FrUYoMipIFDOdSBWXr58MB4EiTpZ0/Xa6r /2xoYpiLy/7Mcvuv8VmhYrcZwfmezC8= X-Google-Smtp-Source: AB8JxZo9UrNaNACP07n83mxHrrPjjfFDVWtMbW5iMffkxtQ3z1mZuEO8vyQIeAWxiEQmLkMl0hNUEQ== X-Received: by 2002:a63:8849:: with SMTP id l70-v6mr10027306pgd.49.1526335976103; Mon, 14 May 2018 15:12:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 May 2018 15:12:16 -0700 Message-Id: <20180514221219.7091-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180514221219.7091-1-richard.henderson@linaro.org> References: <20180514221219.7091-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v5 25/28] fpu/softfloat: Pass FloatClass to pickNaNMulAdd X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For each operand, pass a single enumeration instead of a pair of booleans. The commit also merges multiple different ifdef-selected implementations of pickNaNMulAdd into a single function whose body is ifdef-selected. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- fpu/softfloat-specialize.h | 70 +++++++++++++++----------------------- fpu/softfloat.c | 5 +-- 2 files changed, 28 insertions(+), 47 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 2695183188..0399dfe011 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -594,15 +594,14 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | information. | Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN *-------------------------------------------------------------------------= ---*/ -#if defined(TARGET_ARM) -static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bI= sSNaN, - flag cIsQNaN, flag cIsSNaN, flag infzero, - float_status *status) +static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_= cls, + bool infzero, float_status *status) { +#if defined(TARGET_ARM) /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns * the default NaN */ - if (infzero && cIsQNaN) { + if (infzero && is_qnan(c_cls)) { float_raise(float_flag_invalid, status); return 3; } @@ -610,25 +609,20 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, = flag bIsQNaN, flag bIsSNaN, /* This looks different from the ARM ARM pseudocode, because the ARM A= RM * puts the operands to a fused mac operation (a*b)+c in the order c,a= ,b. */ - if (cIsSNaN) { + if (is_snan(c_cls)) { return 2; - } else if (aIsSNaN) { + } else if (is_snan(a_cls)) { return 0; - } else if (bIsSNaN) { + } else if (is_snan(b_cls)) { return 1; - } else if (cIsQNaN) { + } else if (is_qnan(c_cls)) { return 2; - } else if (aIsQNaN) { + } else if (is_qnan(a_cls)) { return 0; } else { return 1; } -} #elif defined(TARGET_MIPS) -static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bI= sSNaN, - flag cIsQNaN, flag cIsSNaN, flag infzero, - float_status *status) -{ /* For MIPS, the (inf,zero,qnan) case sets InvalidOp and returns * the default NaN */ @@ -639,41 +633,36 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, = flag bIsQNaN, flag bIsSNaN, =20 if (snan_bit_is_one(status)) { /* Prefer sNaN over qNaN, in the a, b, c order. */ - if (aIsSNaN) { + if (is_snan(a_cls)) { return 0; - } else if (bIsSNaN) { + } else if (is_snan(b_cls)) { return 1; - } else if (cIsSNaN) { + } else if (is_snan(c_cls)) { return 2; - } else if (aIsQNaN) { + } else if (is_qnan(a_cls)) { return 0; - } else if (bIsQNaN) { + } else if (is_qnan(b_cls)) { return 1; } else { return 2; } } else { /* Prefer sNaN over qNaN, in the c, a, b order. */ - if (cIsSNaN) { + if (is_snan(c_cls)) { return 2; - } else if (aIsSNaN) { + } else if (is_snan(a_cls)) { return 0; - } else if (bIsSNaN) { + } else if (is_snan(b_cls)) { return 1; - } else if (cIsQNaN) { + } else if (is_qnan(c_cls)) { return 2; - } else if (aIsQNaN) { + } else if (is_qnan(a_cls)) { return 0; } else { return 1; } } -} #elif defined(TARGET_PPC) -static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bI= sSNaN, - flag cIsQNaN, flag cIsSNaN, flag infzero, - float_status *status) -{ /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer * to return an input NaN if we have one (ie c) rather than generating * a default NaN @@ -686,31 +675,26 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, = flag bIsQNaN, flag bIsSNaN, /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB */ - if (aIsSNaN || aIsQNaN) { + if (is_nan(a_cls)) { return 0; - } else if (cIsSNaN || cIsQNaN) { + } else if (is_nan(c_cls)) { return 2; } else { return 1; } -} #else -/* A default implementation: prefer a to b to c. - * This is unlikely to actually match any real implementation. - */ -static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bI= sSNaN, - flag cIsQNaN, flag cIsSNaN, flag infzero, - float_status *status) -{ - if (aIsSNaN || aIsQNaN) { + /* A default implementation: prefer a to b to c. + * This is unlikely to actually match any real implementation. + */ + if (is_nan(a_cls)) { return 0; - } else if (bIsSNaN || bIsQNaN) { + } else if (is_nan(b_cls)) { return 1; } else { return 2; } -} #endif +} =20 /*------------------------------------------------------------------------= ---- | Takes two single-precision floating-point values `a' and `b', one of whi= ch diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 43264fa1f6..65e970eeb2 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -601,10 +601,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatP= arts b, FloatParts c, s->float_exception_flags |=3D float_flag_invalid; } =20 - which =3D pickNaNMulAdd(is_qnan(a.cls), is_snan(a.cls), - is_qnan(b.cls), is_snan(b.cls), - is_qnan(c.cls), is_snan(c.cls), - inf_zero, s); + which =3D pickNaNMulAdd(a.cls, b.cls, c.cls, inf_zero, s); =20 if (s->default_nan_mode) { /* Note that this check is after pickNaNMulAdd so that function --=20 2.17.0 From nobody Wed Oct 29 23:02:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526337005776716.2657133343345; Mon, 14 May 2018 15:30:05 -0700 (PDT) Received: from localhost ([::1]:49984 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILyi-0005ux-Jw for importer@patchew.org; Mon, 14 May 2018 18:30:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52699) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILiG-0008HZ-Iz for qemu-devel@nongnu.org; Mon, 14 May 2018 18:13:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fILiF-00008a-3Z for qemu-devel@nongnu.org; Mon, 14 May 2018 18:13:00 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:37438) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fILiE-00006M-Rg for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:59 -0400 Received: by mail-pf0-x244.google.com with SMTP id e9-v6so6669644pfi.4 for ; Mon, 14 May 2018 15:12:58 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id y2-v6sm14512457pgp.92.2018.05.14.15.12.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 May 2018 15:12:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tSLVnkHv3Kd/+xdpFOzuYurgmMTBI9n4hg87yMUQ/60=; b=GDXRGPmQLnEoaRDsgrwT1pFP1KnURwDgwOy8M9nxL8KaUDY5a1y4Qz+O5nPaLk5moP 7ES3LNnYBZNmICYrbWuAZDwiSXqG/WztKL0Z4pVaAxRdANRcQCJn3hueFEVdxLjc3eoB daq8v08o2GqG2GEJDhTPrQPNXkb0IoWi0M73A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tSLVnkHv3Kd/+xdpFOzuYurgmMTBI9n4hg87yMUQ/60=; b=QzEsWzmzMGOB6RJRNx586lNyg1Z7DaJk/6PmquCoL6xNY+rHHQIb6J9IL1ratoE7kP YbV1nw4cBZNWmCZhPCG/XgpQrNhi31FaBctcsX2nPwVMqFJkwhldSTgTprblmRBxOm5F bdYw0+W0j9JqkBJA+RGiREaJlHNoFIUvnWmWTf8ehk4X21Lbx3RAOA7VF+TM71ZXCBQL VR27ydSdkcL4H8A78qtaZWSO37c7WnoRnjT+G5LXM5j+U//+zRb8XTmLCUagU4UPOdA5 46/OnjZA8erzITggVIP/wHmXBdIKqWVqC8WBVfSN9fjmZsIruyl/g9AtldEMk8mWLOuB OcjA== X-Gm-Message-State: ALKqPwcs+KW+O2h16QWPRrpz0IlIFvICy72f4in21wFcAfOwMCPItqrR WLqbK+0/jjz7yjwU7iaSDZ2CY5C4bFM= X-Google-Smtp-Source: AB8JxZqe3vmxNzhGmoAhsEwILdXri1gH8VVCgm9Jdhh/FnhR4wBYHpg7QtCZL2hfgEpUzyPkcZ/0Aw== X-Received: by 2002:a63:5f11:: with SMTP id t17-v6mr8332307pgb.94.1526335977527; Mon, 14 May 2018 15:12:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 May 2018 15:12:17 -0700 Message-Id: <20180514221219.7091-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180514221219.7091-1-richard.henderson@linaro.org> References: <20180514221219.7091-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v5 26/28] fpu/softfloat: Define floatN_default_nan in terms of parts_default_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Isolate the target-specific choice to 2 functions instead of 6. The code in float16_default_nan was only correct for ARM, MIPS, and X86. Though float16 support is rare among our targets. The code in float128_default_nan was arguably wrong for Sparc. While QEMU supports the Sparc 128-bit insns, no real cpu enables it. The code in floatx80_default_nan tried to be over-general. There are only two targets that support this format: x86 and m68k. Thus there is no point in inventing a value for snan_bit_is_one. Move routines that no longer have ifdefs out of softfloat-specialize.h. Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- fpu/softfloat-specialize.h | 105 +++---------------------------------- fpu/softfloat.c | 35 +++++++++++++ 2 files changed, 41 insertions(+), 99 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 0399dfe011..9d562ed504 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -179,94 +179,22 @@ static FloatParts parts_silence_nan(FloatParts a, flo= at_status *status) return a; } =20 -/*------------------------------------------------------------------------= ---- -| The pattern for a default generated half-precision NaN. -*-------------------------------------------------------------------------= ---*/ -float16 float16_default_nan(float_status *status) -{ -#if defined(TARGET_ARM) - return const_float16(0x7E00); -#else - if (snan_bit_is_one(status)) { - return const_float16(0x7DFF); - } else { -#if defined(TARGET_MIPS) - return const_float16(0x7E00); -#else - return const_float16(0xFE00); -#endif - } -#endif -} - -/*------------------------------------------------------------------------= ---- -| The pattern for a default generated single-precision NaN. -*-------------------------------------------------------------------------= ---*/ -float32 float32_default_nan(float_status *status) -{ -#if defined(TARGET_SPARC) || defined(TARGET_M68K) - return const_float32(0x7FFFFFFF); -#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) = || \ - defined(TARGET_XTENSA) || defined(TARGET_S390X) || \ - defined(TARGET_TRICORE) || defined(TARGET_RISCV) - return const_float32(0x7FC00000); -#elif defined(TARGET_HPPA) - return const_float32(0x7FA00000); -#else - if (snan_bit_is_one(status)) { - return const_float32(0x7FBFFFFF); - } else { -#if defined(TARGET_MIPS) - return const_float32(0x7FC00000); -#else - return const_float32(0xFFC00000); -#endif - } -#endif -} - -/*------------------------------------------------------------------------= ---- -| The pattern for a default generated double-precision NaN. -*-------------------------------------------------------------------------= ---*/ -float64 float64_default_nan(float_status *status) -{ -#if defined(TARGET_SPARC) || defined(TARGET_M68K) - return const_float64(LIT64(0x7FFFFFFFFFFFFFFF)); -#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) = || \ - defined(TARGET_S390X) || defined(TARGET_RISCV) - return const_float64(LIT64(0x7FF8000000000000)); -#elif defined(TARGET_HPPA) - return const_float64(LIT64(0x7FF4000000000000)); -#else - if (snan_bit_is_one(status)) { - return const_float64(LIT64(0x7FF7FFFFFFFFFFFF)); - } else { -#if defined(TARGET_MIPS) - return const_float64(LIT64(0x7FF8000000000000)); -#else - return const_float64(LIT64(0xFFF8000000000000)); -#endif - } -#endif -} - /*------------------------------------------------------------------------= ---- | The pattern for a default generated extended double-precision NaN. *-------------------------------------------------------------------------= ---*/ floatx80 floatx80_default_nan(float_status *status) { floatx80 r; + + /* None of the targets that have snan_bit_is_one use floatx80. */ + assert(!snan_bit_is_one(status)); #if defined(TARGET_M68K) r.low =3D LIT64(0xFFFFFFFFFFFFFFFF); r.high =3D 0x7FFF; #else - if (snan_bit_is_one(status)) { - r.low =3D LIT64(0xBFFFFFFFFFFFFFFF); - r.high =3D 0x7FFF; - } else { - r.low =3D LIT64(0xC000000000000000); - r.high =3D 0xFFFF; - } + /* X86 */ + r.low =3D LIT64(0xC000000000000000); + r.high =3D 0xFFFF; #endif return r; } @@ -285,27 +213,6 @@ floatx80 floatx80_default_nan(float_status *status) const floatx80 floatx80_infinity =3D make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low); =20 -/*------------------------------------------------------------------------= ---- -| The pattern for a default generated quadruple-precision NaN. -*-------------------------------------------------------------------------= ---*/ -float128 float128_default_nan(float_status *status) -{ - float128 r; - - if (snan_bit_is_one(status)) { - r.low =3D LIT64(0xFFFFFFFFFFFFFFFF); - r.high =3D LIT64(0x7FFF7FFFFFFFFFFF); - } else { - r.low =3D LIT64(0x0000000000000000); -#if defined(TARGET_S390X) || defined(TARGET_PPC) || defined(TARGET_RISCV) - r.high =3D LIT64(0x7FFF800000000000); -#else - r.high =3D LIT64(0xFFFF800000000000); -#endif - } - return r; -} - /*------------------------------------------------------------------------= ---- | Raises the exceptions specified by `flags'. Floating-point traps can be | defined here if desired. It is currently not possible for such a trap diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 65e970eeb2..b5842f7b1c 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -2092,6 +2092,41 @@ float64 __attribute__((flatten)) float64_sqrt(float6= 4 a, float_status *status) return float64_round_pack_canonical(pr, status); } =20 +/*------------------------------------------------------------------------= ---- +| The pattern for a default generated NaN. +*-------------------------------------------------------------------------= ---*/ + +float16 float16_default_nan(float_status *status) +{ + return float16_pack_raw(parts_default_nan(status)); +} + +float32 float32_default_nan(float_status *status) +{ + return float32_pack_raw(parts_default_nan(status)); +} + +float64 float64_default_nan(float_status *status) +{ + return float64_pack_raw(parts_default_nan(status)); +} + +float128 float128_default_nan(float_status *status) +{ + FloatParts p =3D parts_default_nan(status); + float128 r; + + /* Extrapolate from the choices made by parts_default_nan to fill + * in the quad-floating format. If the low bit is set, assume we + * want to set all non-snan bits. + */ + r.low =3D -(p.frac & 1); + r.high =3D p.frac >> (DECOMPOSED_BINARY_POINT - 48); + r.high |=3D LIT64(0x7FFF000000000000); + r.high |=3D (uint64_t)p.sign << 63; + + return r; +} =20 /*------------------------------------------------------------------------= ---- | Takes a 64-bit fixed-point value `absZ' with binary point between bits 6 --=20 2.17.0 From nobody Wed Oct 29 23:02:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526337858862290.91718950350105; Mon, 14 May 2018 15:44:18 -0700 (PDT) Received: from localhost ([::1]:51044 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIMCY-0001ln-5V for importer@patchew.org; Mon, 14 May 2018 18:44:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52707) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILiH-0008JU-G2 for qemu-devel@nongnu.org; Mon, 14 May 2018 18:13:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fILiG-0000C8-8D for qemu-devel@nongnu.org; Mon, 14 May 2018 18:13:01 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:37436) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fILiG-0000AG-1r for qemu-devel@nongnu.org; Mon, 14 May 2018 18:13:00 -0400 Received: by mail-pf0-x241.google.com with SMTP id e9-v6so6669675pfi.4 for ; Mon, 14 May 2018 15:13:00 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id y2-v6sm14512457pgp.92.2018.05.14.15.12.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 May 2018 15:12:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MmSgSLwT1JZjRsPCpF/ZgIgh9cLg8HFIxpF7qjon1YU=; b=QoxeagOy7NvXSOcgbeZjM6UqSXCzSETKqOrfTtlfIXXjDnXaGMgxX7Fmf7/prulULO ZSnMHHW1ij9QUNUkZioPDX0OcqJOFeZ7sfb/3HFY04PFKSWXMGi2VC5YVB5PT3Vu8ccC FTZ62O4uZpUJ8Mhx8q0ZnKVs9Dmp8Q72iFCag= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MmSgSLwT1JZjRsPCpF/ZgIgh9cLg8HFIxpF7qjon1YU=; b=e6L0jlWWKaD++stN9wSJIgCmNzwWLQEwcO1JXxfvlXuuCmAkO4CZnqlpxKxvvwvAwh 8Tq3KibdSqZ4i6cSmmeXwINHpUFSC0MNgSaq04wXZ28CqFLhvezlpUISa7fZQBH5JYQI +sIsqk/MgO0MDjKrBhkCBgv7kKImNytPlLWgIu2JKKqRqsxqN8aKZSa/uiTLIK3fqNWV LoOXS9s463t+b3cSMpov+QEn9h5Q0w6YLiXsSE8bu+b1ZnH1KmZVEcT6LbwUY13F6hWP fHZEdDPB7+ctH5KzYs9Wchh8FwkFQfmGDNzNI3xf6Wtz0AgJLU/zIp0FQHtYoGDV/Vp5 RrIw== X-Gm-Message-State: ALKqPwfGg4iSx8ZJjvu5AEgIemCUnDQMHLU16e35wVeY9AfT5L/dGOv+ ydyQ8DjbSBjicnJlVIK3Hk0SKgiJWTI= X-Google-Smtp-Source: AB8JxZrw6ghBtNYvhWRKwiVzbTfJBMsJsO6qqDd7Y8j1Tq3fwMba8iWVWanh3nExzsEjb5s5ijIZfA== X-Received: by 2002:a65:508d:: with SMTP id r13-v6mr10018768pgp.134.1526335978831; Mon, 14 May 2018 15:12:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 May 2018 15:12:18 -0700 Message-Id: <20180514221219.7091-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180514221219.7091-1-richard.henderson@linaro.org> References: <20180514221219.7091-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v5 27/28] fpu/softfloat: Clean up parts_default_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reduce the number of ifdefs. Correct the result for OpenRISC and TriCore (although TriCore fixed in target-specific code). Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Tested-by: Alex Benn=C3=A9e --- fpu/softfloat-specialize.h | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 9d562ed504..ec4fb6ba8b 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -129,22 +129,29 @@ static FloatParts parts_default_nan(float_status *sta= tus) uint64_t frac; =20 #if defined(TARGET_SPARC) || defined(TARGET_M68K) + /* !snan_bit_is_one, set all bits */ frac =3D (1ULL << DECOMPOSED_BINARY_POINT) - 1; -#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) = || \ - defined(TARGET_S390X) || defined(TARGET_RISCV) +#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ + || defined(TARGET_MICROBLAZE) + /* !snan_bit_is_one, set sign and msb */ frac =3D 1ULL << (DECOMPOSED_BINARY_POINT - 1); + sign =3D 1; #elif defined(TARGET_HPPA) + /* snan_bit_is_one, set msb-1. */ frac =3D 1ULL << (DECOMPOSED_BINARY_POINT - 2); #else + /* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, + * S390, SH4, TriCore, and Xtensa. I cannot find documentation + * for Unicore32; the choice from the original commit is unchanged. + * Our other supported targets, CRIS, LM32, Moxie, Nios2, and Tile, + * do not have floating-point. + */ if (snan_bit_is_one(status)) { + /* set all bits other than msb */ frac =3D (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; } else { -#if defined(TARGET_MIPS) + /* set msb */ frac =3D 1ULL << (DECOMPOSED_BINARY_POINT - 1); -#else - frac =3D 1ULL << (DECOMPOSED_BINARY_POINT - 1); - sign =3D 1; -#endif } #endif =20 --=20 2.17.0 From nobody Wed Oct 29 23:02:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526337213665742.1190594655588; Mon, 14 May 2018 15:33:33 -0700 (PDT) Received: from localhost ([::1]:50367 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIM28-0000hS-Qm for importer@patchew.org; Mon, 14 May 2018 18:33:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52731) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILiK-0008OZ-U5 for qemu-devel@nongnu.org; Mon, 14 May 2018 18:13:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fILiH-0000GH-LU for qemu-devel@nongnu.org; Mon, 14 May 2018 18:13:04 -0400 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:42034) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fILiH-0000EG-Cy for qemu-devel@nongnu.org; Mon, 14 May 2018 18:13:01 -0400 Received: by mail-pg0-x243.google.com with SMTP id p9-v6so6060659pgc.9 for ; Mon, 14 May 2018 15:13:01 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id y2-v6sm14512457pgp.92.2018.05.14.15.12.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 May 2018 15:12:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1q8CvQLaVO8CGA7b0QttcxlJQ18Lc1p3qQpT+0UVsAo=; b=PLhE6j6RHwTeLpMhHWmfh/+n0R9IrFT1wBxKJYKvhijYAISElXJ4pj0U5jYKmBOlF4 th6lpZn7BEAt9slRPPNhxdmHmx/OgKxd99q4od6A/MwO+SLunpPdCDPDrso2GeLajAFd OENbHXvPQURChSLhb9Ax7Ym0zgMl8+w/Xi5lg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1q8CvQLaVO8CGA7b0QttcxlJQ18Lc1p3qQpT+0UVsAo=; b=IjSmxX1W2Ug+Qi2hBP4xnX+qJi3iquzPPyFjiZYc7R2NrjO3ZEITB2+oUp2TOZQHM0 BKWFvNuKjCqykyJu3oCvuZoxIo5Z8QfXzHNWT0fXVnPpluNN9enyyF4Ru1Zf8DOKoAEC ITThGx+TRrRMT627VWm/YHZXe89X93ZgUgsmLNQeV2SuZTHsVC7Gi7tmUv7eg8bJsBu/ qqME3EaCXM9iWISHAf/irr0ACG2wEFIgVmqbUikUKEdI0vroWSAcOtU1A7HQLxRT2NM4 Vt8+Nf4iCTocp+hrYYYqXmG5uNrNVazMaoaAhthDweb6oCbCPRagba7KLplIpbZbTPuh L3dQ== X-Gm-Message-State: ALKqPwc1PKmJlo+t2wmwqWzSb6oOnNqkBr8zP2DTV7kktnvSbiaE5ypG SpxxLUqBQh7AA9Yn266Mbnwlf03Qejw= X-Google-Smtp-Source: AB8JxZqb5qbenM106VXawGyY3YLsYu3+c+NCGDC6ShO+FYI4aHaHsUDoQo4i77Jnk7e6xO00ODrEjA== X-Received: by 2002:a65:53ca:: with SMTP id z10-v6mr7727398pgr.413.1526335980058; Mon, 14 May 2018 15:13:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 May 2018 15:12:19 -0700 Message-Id: <20180514221219.7091-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180514221219.7091-1-richard.henderson@linaro.org> References: <20180514221219.7091-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v5 28/28] fpu/softfloat: Define floatN_silence_nan in terms of parts_silence_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Isolate the target-specific choice to 3 functions instead of 6. The code in floatx80_default_nan tried to be over-general. There are only two targets that support this format: x86 and m68k. Thus there is no point in inventing a mechanism for snan_bit_is_one. Move routines that no longer have ifdefs out of softfloat-specialize.h. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Tested-by: Alex Benn=C3=A9e --- fpu/softfloat-specialize.h | 81 ++------------------------------------ fpu/softfloat.c | 19 +++++++++ 2 files changed, 23 insertions(+), 77 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index ec4fb6ba8b..16c0bcb6fa 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -278,24 +278,6 @@ int float16_is_signaling_nan(float16 a_, float_status = *status) #endif } =20 -/*------------------------------------------------------------------------= ---- -| Returns a quiet NaN from a signalling NaN for the half-precision -| floating point value `a'. -*-------------------------------------------------------------------------= ---*/ - -float16 float16_silence_nan(float16 a, float_status *status) -{ -#ifdef NO_SIGNALING_NANS - g_assert_not_reached(); -#else - if (snan_bit_is_one(status)) { - return float16_default_nan(status); - } else { - return a | (1 << 9); - } -#endif -} - /*------------------------------------------------------------------------= ---- | Returns 1 if the single-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -334,30 +316,6 @@ int float32_is_signaling_nan(float32 a_, float_status = *status) #endif } =20 -/*------------------------------------------------------------------------= ---- -| Returns a quiet NaN from a signalling NaN for the single-precision -| floating point value `a'. -*-------------------------------------------------------------------------= ---*/ - -float32 float32_silence_nan(float32 a, float_status *status) -{ -#ifdef NO_SIGNALING_NANS - g_assert_not_reached(); -#else - if (snan_bit_is_one(status)) { -# ifdef TARGET_HPPA - a &=3D ~0x00400000; - a |=3D 0x00200000; - return a; -# else - return float32_default_nan(status); -# endif - } else { - return a | (1 << 22); - } -#endif -} - /*------------------------------------------------------------------------= ---- | Returns the result of converting the single-precision floating-point NaN | `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid @@ -706,31 +664,6 @@ int float64_is_signaling_nan(float64 a_, float_status = *status) #endif } =20 -/*------------------------------------------------------------------------= ---- -| Returns a quiet NaN from a signalling NaN for the double-precision -| floating point value `a'. -*-------------------------------------------------------------------------= ---*/ - -float64 float64_silence_nan(float64 a, float_status *status) -{ -#ifdef NO_SIGNALING_NANS - g_assert_not_reached(); -#else - if (snan_bit_is_one(status)) { -# ifdef TARGET_HPPA - a &=3D ~0x0008000000000000ULL; - a |=3D 0x0004000000000000ULL; - return a; -# else - return float64_default_nan(status); -# endif - } else { - return a | LIT64(0x0008000000000000); - } -#endif -} - - /*------------------------------------------------------------------------= ---- | Returns the result of converting the double-precision floating-point NaN | `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid @@ -886,16 +819,10 @@ int floatx80_is_signaling_nan(floatx80 a, float_statu= s *status) =20 floatx80 floatx80_silence_nan(floatx80 a, float_status *status) { -#ifdef NO_SIGNALING_NANS - g_assert_not_reached(); -#else - if (snan_bit_is_one(status)) { - return floatx80_default_nan(status); - } else { - a.low |=3D LIT64(0xC000000000000000); - return a; - } -#endif + /* None of the targets that have snan_bit_is_one use floatx80. */ + assert(!snan_bit_is_one(status)); + a.low |=3D LIT64(0xC000000000000000); + return a; } =20 /*------------------------------------------------------------------------= ---- diff --git a/fpu/softfloat.c b/fpu/softfloat.c index b5842f7b1c..40b039ee5b 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -2128,6 +2128,25 @@ float128 float128_default_nan(float_status *status) return r; } =20 +/*------------------------------------------------------------------------= ---- +| Returns a quiet NaN from a signalling NaN for the floating point value `= a'. +*-------------------------------------------------------------------------= ---*/ + +float16 float16_silence_nan(float16 a, float_status *status) +{ + return float16_pack_raw(parts_silence_nan(float16_unpack_raw(a), statu= s)); +} + +float32 float32_silence_nan(float32 a, float_status *status) +{ + return float32_pack_raw(parts_silence_nan(float32_unpack_raw(a), statu= s)); +} + +float64 float64_silence_nan(float64 a, float_status *status) +{ + return float64_pack_raw(parts_silence_nan(float64_unpack_raw(a), statu= s)); +} + /*------------------------------------------------------------------------= ---- | Takes a 64-bit fixed-point value `absZ' with binary point between bits 6 | and 7, and returns the properly rounded 32-bit integer corresponding to = the --=20 2.17.0