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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id t1-v6sm8695688pgu.41.2018.05.12.10.57.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 12 May 2018 10:57:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7ixsQOLtzk0PcoLDeNcIl7jZJN/K1rFl+xHItUE4g2g=; b=iftOlNSFFNJsQBIJR9lxH8CbyTYSzqz5KS3pJOAIU4r1a7jgwAGGYyTgUC661dilx2 7wJx3eWqmUuAskUPc40+iT7EYc2FmmZje3Hb02ERv9Q+M2+klIi9GQDlpugjxJOKTWLk dbSZBmsbaSY3WINaaH+TgnEGEsyXSaLJlnuKs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7ixsQOLtzk0PcoLDeNcIl7jZJN/K1rFl+xHItUE4g2g=; b=q+xQU/ixlKr3zKEn/5s+YMVmJBoOL4+F1UCbv6UvstNE73qT8IQWiogZq3QHvY5Kuz Wcnk+ZuTtpyg0YboNgTRL1vsGhqJsqhpM8JOVWK9yVmpcJqoVA1iAtp9pwodgKro9ud1 y1dmS0z1sTLWTPAP1Bb2t1JVNy80/Vo5AO1M75zWPYNTGO97OySEH03mecFXHUPyvnns q86W5GFGtvqT2s/jebqIw6mZpYEHVI8Akbiay8P826lwAX3qz2UZUQTcJcA66jt5H5Qt M97MhaKMFXBpmRATc60GISXdP21hXtlOJmF2qHGuVkthIaaxo944wBDFRIljj3gy1du1 r8sw== X-Gm-Message-State: ALKqPweZBjsqZdp8X6c+Y6WYtOzgz40QEFJuIXWJwaQBdb4r4fFokJmM QH7doHFgwnExw1VR/XJghr/DtEkEX04= X-Google-Smtp-Source: AB8JxZo/OKXB3324O/rhoRPUzFyTDt7GtNlorJCePjA5ix26gnVGXJOZ8Y7W8nrAq/xPViqz1C1JBg== X-Received: by 2002:a63:7e18:: with SMTP id z24-v6mr3261504pgc.276.1526147852605; Sat, 12 May 2018 10:57:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 12 May 2018 10:57:24 -0700 Message-Id: <20180512175724.5923-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512175724.5923-1-richard.henderson@linaro.org> References: <20180512175724.5923-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH 4/4] target/xtensa: Convert to TranslatorOps X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jcmvbkbc@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/xtensa/translate.c | 229 ++++++++++++++++++++------------------ 1 file changed, 122 insertions(+), 107 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 45f32dc71f..9de45e4be4 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1048,148 +1048,163 @@ static void gen_ibreak_check(CPUXtensaState *env,= DisasContext *dc) } } =20 -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +static void xtensa_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cpu) { - CPUXtensaState *env =3D cs->env_ptr; - DisasContext dc1, *dc =3D &dc1; - int insn_count =3D 0; - int max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; - uint32_t pc_start =3D tb->pc; - uint32_t page_start =3D pc_start & TARGET_PAGE_MASK; - - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + CPUXtensaState *env =3D cpu->env_ptr; + uint32_t tb_flags =3D dc->base.tb->flags; =20 dc->config =3D env->config; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; - dc->base.tb =3D tb; - dc->pc =3D pc_start; - dc->ring =3D tb->flags & XTENSA_TBFLAG_RING_MASK; - dc->cring =3D (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc->ring; + dc->pc =3D dc->base.pc_first; + dc->ring =3D tb_flags & XTENSA_TBFLAG_RING_MASK; + dc->cring =3D (tb_flags & XTENSA_TBFLAG_EXCM) ? 0 : dc->ring; dc->lbeg =3D env->sregs[LBEG]; dc->lend =3D env->sregs[LEND]; - dc->base.is_jmp =3D DISAS_NEXT; - dc->debug =3D tb->flags & XTENSA_TBFLAG_DEBUG; - dc->icount =3D tb->flags & XTENSA_TBFLAG_ICOUNT; - dc->cpenable =3D (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >> + dc->debug =3D tb_flags & XTENSA_TBFLAG_DEBUG; + dc->icount =3D tb_flags & XTENSA_TBFLAG_ICOUNT; + dc->cpenable =3D (tb_flags & XTENSA_TBFLAG_CPENABLE_MASK) >> XTENSA_TBFLAG_CPENABLE_SHIFT; - dc->window =3D ((tb->flags & XTENSA_TBFLAG_WINDOW_MASK) >> + dc->window =3D ((tb_flags & XTENSA_TBFLAG_WINDOW_MASK) >> XTENSA_TBFLAG_WINDOW_SHIFT); =20 if (dc->config->isa) { dc->insnbuf =3D xtensa_insnbuf_alloc(dc->config->isa); dc->slotbuf =3D xtensa_insnbuf_alloc(dc->config->isa); } - init_sar_tracker(dc); +} + +static void xtensa_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + if (dc->icount) { dc->next_icount =3D tcg_temp_local_new_i32(); } +} =20 - gen_tb_start(tb); +static void xtensa_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + tcg_gen_insn_start(dcbase->pc_next); +} =20 - if ((tb_cflags(tb) & CF_USE_ICOUNT) && - (tb->flags & XTENSA_TBFLAG_YIELD)) { - tcg_gen_insn_start(dc->pc); - ++insn_count; +static bool xtensa_tr_breakpoint_check(DisasContextBase *dcbase, CPUState = *cpu, + const CPUBreakpoint *bp) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); + gen_exception(dc, EXCP_DEBUG); + dc->base.is_jmp =3D DISAS_NORETURN; + /* The address covered by the breakpoint must be included in + [tb->pc, tb->pc + tb->size) in order to for it to be + properly cleared -- thus we increment the PC here so that + the logic setting tb->size below does the right thing. */ + dc->base.pc_next +=3D 2; + return true; +} + +static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *c= pu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + CPUXtensaState *env =3D cpu->env_ptr; + target_ulong page_start; + + /* These two conditions only apply to the first insn in the TB, + but this is the first TranslateOps hook that allows exiting. */ + if ((tb_cflags(dc->base.tb) & CF_USE_ICOUNT) + && (dc->base.tb->flags & XTENSA_TBFLAG_YIELD)) { gen_exception(dc, EXCP_YIELD); dc->base.is_jmp =3D DISAS_NORETURN; - goto done; + return; } - if (tb->flags & XTENSA_TBFLAG_EXCEPTION) { - tcg_gen_insn_start(dc->pc); - ++insn_count; + if (dc->base.tb->flags & XTENSA_TBFLAG_EXCEPTION) { gen_exception(dc, EXCP_DEBUG); dc->base.is_jmp =3D DISAS_NORETURN; - goto done; + return; } =20 - do { - tcg_gen_insn_start(dc->pc); - ++insn_count; - - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { - tcg_gen_movi_i32(cpu_pc, dc->pc); - gen_exception(dc, EXCP_DEBUG); - dc->base.is_jmp =3D DISAS_NORETURN; - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - dc->pc +=3D 2; - break; - } - - if (insn_count =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { - gen_io_start(); - } - - if (dc->icount) { - TCGLabel *label =3D gen_new_label(); - - tcg_gen_addi_i32(dc->next_icount, cpu_SR[ICOUNT], 1); - tcg_gen_brcondi_i32(TCG_COND_NE, dc->next_icount, 0, label); - tcg_gen_mov_i32(dc->next_icount, cpu_SR[ICOUNT]); - if (dc->debug) { - gen_debug_exception(dc, DEBUGCAUSE_IC); - } - gen_set_label(label); - } - - if (dc->debug) { - gen_ibreak_check(env, dc); - } - - disas_xtensa_insn(env, dc); - if (dc->icount) { - tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount); - } - if (dc->base.singlestep_enabled) { - tcg_gen_movi_i32(cpu_pc, dc->pc); - gen_exception(dc, EXCP_DEBUG); - break; - } - } while (dc->base.is_jmp =3D=3D DISAS_NEXT && - insn_count < max_insns && - dc->pc - page_start < TARGET_PAGE_SIZE && - dc->pc - page_start + xtensa_insn_len(env, dc) <=3D TARGET_PA= GE_SIZE - && !tcg_op_buf_full()); -done: - reset_sar_tracker(dc); if (dc->icount) { - tcg_temp_free(dc->next_icount); + TCGLabel *label =3D gen_new_label(); + + tcg_gen_addi_i32(dc->next_icount, cpu_SR[ICOUNT], 1); + tcg_gen_brcondi_i32(TCG_COND_NE, dc->next_icount, 0, label); + tcg_gen_mov_i32(dc->next_icount, cpu_SR[ICOUNT]); + if (dc->debug) { + gen_debug_exception(dc, DEBUGCAUSE_IC); + } + gen_set_label(label); } + + if (dc->debug) { + gen_ibreak_check(env, dc); + } + + disas_xtensa_insn(env, dc); + + if (dc->icount) { + tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount); + } + + /* End the TB if the next insn will cross into the next page. */ + page_start =3D dc->base.pc_first & TARGET_PAGE_MASK; + if (dc->base.is_jmp =3D=3D DISAS_NEXT && + dc->pc - page_start < TARGET_PAGE_SIZE && + dc->pc - page_start + xtensa_insn_len(env, dc) <=3D TARGET_PAGE_SI= ZE) { + dc->base.is_jmp =3D DISAS_TOO_MANY; + } +} + +static void xtensa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + reset_sar_tracker(dc); if (dc->config->isa) { xtensa_insnbuf_free(dc->config->isa, dc->insnbuf); xtensa_insnbuf_free(dc->config->isa, dc->slotbuf); } - - if (tb_cflags(tb) & CF_LAST_IO) { - gen_io_end(); + if (dc->icount) { + tcg_temp_free(dc->next_icount); } =20 - if (dc->base.is_jmp =3D=3D DISAS_NEXT) { - gen_jumpi(dc, dc->pc, 0); + switch (dc->base.is_jmp) { + case DISAS_NORETURN: + break; + case DISAS_TOO_MANY: + if (dc->base.singlestep_enabled) { + tcg_gen_movi_i32(cpu_pc, dc->pc); + gen_exception(dc, EXCP_DEBUG); + } else { + gen_jumpi(dc, dc->pc, 0); + } + break; + default: + g_assert_not_reached(); } - gen_tb_end(tb, insn_count); +} =20 -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(pc_start)) { - qemu_log_lock(); - qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc->pc - pc_start); - qemu_log("\n"); - qemu_log_unlock(); - } -#endif - tb->size =3D dc->pc - pc_start; - tb->icount =3D insn_count; +static void xtensa_tr_disas_log(const DisasContextBase *dcbase, CPUState *= cpu) +{ + qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); + log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); +} + +static const TranslatorOps xtensa_translator_ops =3D { + .init_disas_context =3D xtensa_tr_init_disas_context, + .tb_start =3D xtensa_tr_tb_start, + .insn_start =3D xtensa_tr_insn_start, + .breakpoint_check =3D xtensa_tr_breakpoint_check, + .translate_insn =3D xtensa_tr_translate_insn, + .tb_stop =3D xtensa_tr_tb_stop, + .disas_log =3D xtensa_tr_disas_log, +}; + +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +{ + DisasContext dc =3D {}; + translator_loop(&xtensa_translator_ops, &dc.base, cpu, tb); } =20 void xtensa_cpu_dump_state(CPUState *cs, FILE *f, --=20 2.17.0