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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id t1-v6sm8695688pgu.41.2018.05.12.10.57.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 12 May 2018 10:57:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=I4s4Ah+oHP2r3HCOp2TF3LOOeerbkqaM7TeDar5sIoE=; b=VX4jB4CFOdDeycRom+WnLCGfBi5cfez3bMbd34l1MGScPONmhk4/IKMd4H9zHNg055 pTYP6Y3FDWOfV+kOidpI/kSYR5PNIraUqKI4cuofn2T5BOgk2kxILDBZFpD2kI3Rr4ZC xufJtCnHWaCj7Xet6B/6dUKpAsvQNTlpdl2VY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=I4s4Ah+oHP2r3HCOp2TF3LOOeerbkqaM7TeDar5sIoE=; b=lZZs8goqWUiQb4t71RwcUmDAOxeF1TeJAuKjyt4OHpILdkWzKmXrinba2sKkUHuIgh GYPi9tIPJz/64yChQc+/e7d/HuEMn/Z75AFBA1LUOO2CZuoJhXlTVVyeVOh5oaC4vu0c wYikWxHbj26R2FMnNdmxqU1muGmfgLCw+OngJsJZGFD8unx4Ed/O+ydpCbhcG+D8ZZiv HKvAxSgT8Cd0i9bYsALzFMr0tQhrBa+mAMeMOsnjUDmpVWcZA+TLXty03XhLxlTBmEcx 1hjsyISS0pDYEZTCzW8gbypYfSkrXxpE2rtafRxRLZxDy6tt1/BuW3kD+XDKwnJIB2x2 wzgw== X-Gm-Message-State: ALKqPweS0vdOxql28ngHTFf9oqPnIpjR+9NIfo++PDrycRcf+IJn/9zn J9+k4WHD2NYk2LhY8EmkgCG2rbD01ug= X-Google-Smtp-Source: AB8JxZrLHqJ/ZjibmmwNYXfN5p8DqdZciJ2QxI+wv6m7yB66FU3debxZflhe/eih/qZX9wWYlVXJ2g== X-Received: by 2002:a17:902:14d:: with SMTP id 71-v6mr3268023plb.275.1526147851368; Sat, 12 May 2018 10:57:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 12 May 2018 10:57:23 -0700 Message-Id: <20180512175724.5923-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512175724.5923-1-richard.henderson@linaro.org> References: <20180512175724.5923-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH 3/4] target/xtensa: Change gen_intermediate_code dc to pointer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jcmvbkbc@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This will reduce the size of the patch in the next patch, where the context will have to be a pointer. Signed-off-by: Richard Henderson --- target/xtensa/translate.c | 122 +++++++++++++++++++------------------- 1 file changed, 61 insertions(+), 61 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index cc48d105e9..45f32dc71f 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1051,7 +1051,7 @@ static void gen_ibreak_check(CPUXtensaState *env, Dis= asContext *dc) void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { CPUXtensaState *env =3D cs->env_ptr; - DisasContext dc; + DisasContext dc1, *dc =3D &dc1; int insn_count =3D 0; int max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; uint32_t pc_start =3D tb->pc; @@ -1064,63 +1064,63 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) max_insns =3D TCG_MAX_INSNS; } =20 - dc.config =3D env->config; - dc.base.singlestep_enabled =3D cs->singlestep_enabled; - dc.base.tb =3D tb; - dc.pc =3D pc_start; - dc.ring =3D tb->flags & XTENSA_TBFLAG_RING_MASK; - dc.cring =3D (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring; - dc.lbeg =3D env->sregs[LBEG]; - dc.lend =3D env->sregs[LEND]; - dc.base.is_jmp =3D DISAS_NEXT; - dc.debug =3D tb->flags & XTENSA_TBFLAG_DEBUG; - dc.icount =3D tb->flags & XTENSA_TBFLAG_ICOUNT; - dc.cpenable =3D (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >> + dc->config =3D env->config; + dc->base.singlestep_enabled =3D cs->singlestep_enabled; + dc->base.tb =3D tb; + dc->pc =3D pc_start; + dc->ring =3D tb->flags & XTENSA_TBFLAG_RING_MASK; + dc->cring =3D (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc->ring; + dc->lbeg =3D env->sregs[LBEG]; + dc->lend =3D env->sregs[LEND]; + dc->base.is_jmp =3D DISAS_NEXT; + dc->debug =3D tb->flags & XTENSA_TBFLAG_DEBUG; + dc->icount =3D tb->flags & XTENSA_TBFLAG_ICOUNT; + dc->cpenable =3D (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >> XTENSA_TBFLAG_CPENABLE_SHIFT; - dc.window =3D ((tb->flags & XTENSA_TBFLAG_WINDOW_MASK) >> + dc->window =3D ((tb->flags & XTENSA_TBFLAG_WINDOW_MASK) >> XTENSA_TBFLAG_WINDOW_SHIFT); =20 - if (dc.config->isa) { - dc.insnbuf =3D xtensa_insnbuf_alloc(dc.config->isa); - dc.slotbuf =3D xtensa_insnbuf_alloc(dc.config->isa); + if (dc->config->isa) { + dc->insnbuf =3D xtensa_insnbuf_alloc(dc->config->isa); + dc->slotbuf =3D xtensa_insnbuf_alloc(dc->config->isa); } =20 - init_sar_tracker(&dc); - if (dc.icount) { - dc.next_icount =3D tcg_temp_local_new_i32(); + init_sar_tracker(dc); + if (dc->icount) { + dc->next_icount =3D tcg_temp_local_new_i32(); } =20 gen_tb_start(tb); =20 if ((tb_cflags(tb) & CF_USE_ICOUNT) && (tb->flags & XTENSA_TBFLAG_YIELD)) { - tcg_gen_insn_start(dc.pc); + tcg_gen_insn_start(dc->pc); ++insn_count; - gen_exception(&dc, EXCP_YIELD); - dc.base.is_jmp =3D DISAS_NORETURN; + gen_exception(dc, EXCP_YIELD); + dc->base.is_jmp =3D DISAS_NORETURN; goto done; } if (tb->flags & XTENSA_TBFLAG_EXCEPTION) { - tcg_gen_insn_start(dc.pc); + tcg_gen_insn_start(dc->pc); ++insn_count; - gen_exception(&dc, EXCP_DEBUG); - dc.base.is_jmp =3D DISAS_NORETURN; + gen_exception(dc, EXCP_DEBUG); + dc->base.is_jmp =3D DISAS_NORETURN; goto done; } =20 do { - tcg_gen_insn_start(dc.pc); + tcg_gen_insn_start(dc->pc); ++insn_count; =20 - if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) { - tcg_gen_movi_i32(cpu_pc, dc.pc); - gen_exception(&dc, EXCP_DEBUG); - dc.base.is_jmp =3D DISAS_NORETURN; + if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { + tcg_gen_movi_i32(cpu_pc, dc->pc); + gen_exception(dc, EXCP_DEBUG); + dc->base.is_jmp =3D DISAS_NORETURN; /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that the logic setting tb->size below does the right thing. */ - dc.pc +=3D 2; + dc->pc +=3D 2; break; } =20 @@ -1128,52 +1128,52 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) gen_io_start(); } =20 - if (dc.icount) { + if (dc->icount) { TCGLabel *label =3D gen_new_label(); =20 - tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1); - tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label); - tcg_gen_mov_i32(dc.next_icount, cpu_SR[ICOUNT]); - if (dc.debug) { - gen_debug_exception(&dc, DEBUGCAUSE_IC); + tcg_gen_addi_i32(dc->next_icount, cpu_SR[ICOUNT], 1); + tcg_gen_brcondi_i32(TCG_COND_NE, dc->next_icount, 0, label); + tcg_gen_mov_i32(dc->next_icount, cpu_SR[ICOUNT]); + if (dc->debug) { + gen_debug_exception(dc, DEBUGCAUSE_IC); } gen_set_label(label); } =20 - if (dc.debug) { - gen_ibreak_check(env, &dc); + if (dc->debug) { + gen_ibreak_check(env, dc); } =20 - disas_xtensa_insn(env, &dc); - if (dc.icount) { - tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount); + disas_xtensa_insn(env, dc); + if (dc->icount) { + tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount); } - if (cs->singlestep_enabled) { - tcg_gen_movi_i32(cpu_pc, dc.pc); - gen_exception(&dc, EXCP_DEBUG); + if (dc->base.singlestep_enabled) { + tcg_gen_movi_i32(cpu_pc, dc->pc); + gen_exception(dc, EXCP_DEBUG); break; } - } while (dc.base.is_jmp =3D=3D DISAS_NEXT && - insn_count < max_insns && - dc.pc - page_start < TARGET_PAGE_SIZE && - dc.pc - page_start + xtensa_insn_len(env, &dc) <=3D TARGET_PAG= E_SIZE - && !tcg_op_buf_full()); + } while (dc->base.is_jmp =3D=3D DISAS_NEXT && + insn_count < max_insns && + dc->pc - page_start < TARGET_PAGE_SIZE && + dc->pc - page_start + xtensa_insn_len(env, dc) <=3D TARGET_PA= GE_SIZE + && !tcg_op_buf_full()); done: - reset_sar_tracker(&dc); - if (dc.icount) { - tcg_temp_free(dc.next_icount); + reset_sar_tracker(dc); + if (dc->icount) { + tcg_temp_free(dc->next_icount); } - if (dc.config->isa) { - xtensa_insnbuf_free(dc.config->isa, dc.insnbuf); - xtensa_insnbuf_free(dc.config->isa, dc.slotbuf); + if (dc->config->isa) { + xtensa_insnbuf_free(dc->config->isa, dc->insnbuf); + xtensa_insnbuf_free(dc->config->isa, dc->slotbuf); } =20 if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } =20 - if (dc.base.is_jmp =3D=3D DISAS_NEXT) { - gen_jumpi(&dc, dc.pc, 0); + if (dc->base.is_jmp =3D=3D DISAS_NEXT) { + gen_jumpi(dc, dc->pc, 0); } gen_tb_end(tb, insn_count); =20 @@ -1183,12 +1183,12 @@ done: qemu_log_lock(); qemu_log("----------------\n"); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc.pc - pc_start); + log_target_disas(cs, pc_start, dc->pc - pc_start); qemu_log("\n"); qemu_log_unlock(); } #endif - tb->size =3D dc.pc - pc_start; + tb->size =3D dc->pc - pc_start; tb->icount =3D insn_count; } =20 --=20 2.17.0