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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id t1-v6sm8695688pgu.41.2018.05.12.10.57.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 12 May 2018 10:57:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uzTRu1cJli0cUNrCwQfSv1pusDe6ToUhXEDAbL1UNTY=; b=JRJKHF3sjjVxz04+kQvCMYmUkBLh8CNKBfI7/VR9ufbHDW3dFBUNjkc0qgWlFjgYag LPVI5csf7uM6N4hgAWsJnit4417O3SIBwDyhhaTpO5n9m4JNyL5fcm8BQIBudaGey+kr REZ6yiJvrEEPVxb3Dnbsih78vo7WJF2yWn+hc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uzTRu1cJli0cUNrCwQfSv1pusDe6ToUhXEDAbL1UNTY=; b=tuYDuBVgZGWbUkGb7WWudJBcS07ws2ZyaIkyFpA1KIHDuC7lIubGwCB+KW3k5yXPQ7 Rhwh8NLxCn5pfIZbFPh+bHR3nVnV5QmQ01nCZbREEHJjGy+CiEHV7AL4cguagvmvPkbC h4xxI+z0j+jFmObbkNfuE2cZcS+SlJ1cRY2uVktYhKuJLh8vjM2JCZTXjzla6hR3Er40 pKmguCBN4Ni4hrjwNfbVAPEc1NMbBVwYgZCVyDAOJ69bc7c2POm5iC2oEXbY0X/Hj9Ea pvWce8gDJVFjyJCOX8UKiR9qftl0jqFrnYurGUpIft/0sEQV25d7Q4AdUun/jCJFqqIV Tsxg== X-Gm-Message-State: ALKqPwdyyfYaQO6P1+VyiflFFR8EVpcZ9cLKRdYFaASTyhS83zUKxvRQ tT0UPlzikWCng9NwUrGQ+exzgxGNzss= X-Google-Smtp-Source: AB8JxZp2wtd7ltTE8lUBEvxzXc0kyYnG+Q06luXPwnQhjsRP8DOjJrtJ5EvymD5wRH4OIpjmQIyEBg== X-Received: by 2002:a17:902:8f97:: with SMTP id z23-v6mr3312217plo.329.1526147848545; Sat, 12 May 2018 10:57:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 12 May 2018 10:57:21 -0700 Message-Id: <20180512175724.5923-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512175724.5923-1-richard.henderson@linaro.org> References: <20180512175724.5923-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH 1/4] target/xtensa: Replace DISAS_UPDATE with DISAS_NORETURN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jcmvbkbc@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The usage of DISAS_UPDATE is after noreturn helpers. It is thus indistinguishable from DISAS_NORETURN. Signed-off-by: Richard Henderson Acked-by: Max Filippov Tested-by: Max Filippov --- target/xtensa/translate.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index aad496347d..a1e63f9661 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -47,9 +47,6 @@ #include "exec/log.h" =20 =20 -/* is_jmp field values */ -#define DISAS_UPDATE DISAS_TARGET_0 /* cpu state was modified dynamically= */ - struct DisasContext { const XtensaConfig *config; TranslationBlock *tb; @@ -317,7 +314,7 @@ static void gen_exception_cause(DisasContext *dc, uint3= 2_t cause) tcg_temp_free(tcause); if (cause =3D=3D ILLEGAL_INSTRUCTION_CAUSE || cause =3D=3D SYSCALL_CAUSE) { - dc->is_jmp =3D DISAS_UPDATE; + dc->is_jmp =3D DISAS_NORETURN; } } =20 @@ -339,7 +336,7 @@ static void gen_debug_exception(DisasContext *dc, uint3= 2_t cause) tcg_temp_free(tpc); tcg_temp_free(tcause); if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) { - dc->is_jmp =3D DISAS_UPDATE; + dc->is_jmp =3D DISAS_NORETURN; } } =20 @@ -351,7 +348,7 @@ static bool gen_check_privilege(DisasContext *dc) } #endif gen_exception_cause(dc, PRIVILEGED_CAUSE); - dc->is_jmp =3D DISAS_UPDATE; + dc->is_jmp =3D DISAS_NORETURN; return false; } =20 @@ -360,7 +357,7 @@ static bool gen_check_cpenable(DisasContext *dc, unsign= ed cp) if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) && !(dc->cpenable & (1 << cp))) { gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp); - dc->is_jmp =3D DISAS_UPDATE; + dc->is_jmp =3D DISAS_NORETURN; return false; } return true; @@ -382,7 +379,7 @@ static void gen_jump_slot(DisasContext *dc, TCGv dest, = int slot) tcg_gen_exit_tb(0); } } - dc->is_jmp =3D DISAS_UPDATE; + dc->is_jmp =3D DISAS_NORETURN; } =20 static void gen_jump(DisasContext *dc, TCGv dest) @@ -918,7 +915,7 @@ static bool gen_window_check1(DisasContext *dc, unsigne= d r1) TCGv_i32 w =3D tcg_const_i32(r1 / 4); =20 gen_helper_window_check(cpu_env, pc, w); - dc->is_jmp =3D DISAS_UPDATE; + dc->is_jmp =3D DISAS_NORETURN; return false; } return true; @@ -1103,14 +1100,14 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) tcg_gen_insn_start(dc.pc); ++insn_count; gen_exception(&dc, EXCP_YIELD); - dc.is_jmp =3D DISAS_UPDATE; + dc.is_jmp =3D DISAS_NORETURN; goto done; } if (tb->flags & XTENSA_TBFLAG_EXCEPTION) { tcg_gen_insn_start(dc.pc); ++insn_count; gen_exception(&dc, EXCP_DEBUG); - dc.is_jmp =3D DISAS_UPDATE; + dc.is_jmp =3D DISAS_NORETURN; goto done; } =20 @@ -1121,7 +1118,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) { tcg_gen_movi_i32(cpu_pc, dc.pc); gen_exception(&dc, EXCP_DEBUG); - dc.is_jmp =3D DISAS_UPDATE; + dc.is_jmp =3D DISAS_NORETURN; /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that --=20 2.17.0 From nobody Wed Oct 29 22:59:56 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526147997329703.4854647425701; Sat, 12 May 2018 10:59:57 -0700 (PDT) Received: from localhost ([::1]:60438 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fHYoC-0004Bg-Ki for importer@patchew.org; Sat, 12 May 2018 13:59:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46943) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fHYly-0005x6-41 for qemu-devel@nongnu.org; Sat, 12 May 2018 13:57:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fHYlv-0002tg-Pw for qemu-devel@nongnu.org; Sat, 12 May 2018 13:57:34 -0400 Received: from mail-pl0-x244.google.com ([2607:f8b0:400e:c01::244]:34106) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fHYlv-0002ta-Hm for qemu-devel@nongnu.org; Sat, 12 May 2018 13:57:31 -0400 Received: by mail-pl0-x244.google.com with SMTP id ay10-v6so5040128plb.1 for ; Sat, 12 May 2018 10:57:31 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id t1-v6sm8695688pgu.41.2018.05.12.10.57.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 12 May 2018 10:57:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2FxGm2PJnXeuNxcy5BLNHKtTBffRiMXv6b1ptlzADis=; b=U3qipdr3bP47YRDhv3bmq2W1yliIyMxNxRNZLaZL02HS5/c2d0bPOXsTxnXTRyvtBW 4Fh0m6DcStfWD4E/apSWz+UMVP9S7gWyhoKfFZMdI6aFEtFt5uI78Gp3XVvihf0gzeN1 Gc3EqyPLmOqdJqzm61jdCavicJnR4jvaw3mcA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2FxGm2PJnXeuNxcy5BLNHKtTBffRiMXv6b1ptlzADis=; b=ecTH+fN6NQ5NQ22ZsOQ3W30Wu2HqXJxzKohWA1ACQ/u197BoNrEWHc47ib5JtcqGg7 DB/3tbRmZpbKltK6k/RIQKyEQvmrVvJrjC/tGE7Jt0X1z2Q+c36rugO3zQEUYjAzWNJl u8ktD+xhECoMPpM3Fc6G3jXJv+dGbBpuMC1MpThnvObzjqU5My9eIugsz8H7H+0k3uYJ UNR/wn3dQnCzdWjoRTZTl5S0Vi+V+5m9AHnY2QPjEZQGwXvX7+cTMrVEwKja0DPzzJdO g3ArzhXqV1AGLxpHANCnrrTJPfQK73xz3bdTvdleVRjWCKfw8mHsHid7z299fIMH9To0 ipOQ== X-Gm-Message-State: ALKqPweXkpvcjLydHQyP1E8zZ8EnyupWuLKED4wL6XiBd/2B4k1mJhcz LMCpAXzo3K80o3NI/Ee2KxEjDxxgQiA= X-Google-Smtp-Source: AB8JxZq9gSWmE1ln2rH2TtclhM/BOjj7eGPdDSHhs7w5Bg3PSXx3+q4fv//kpa2JnxUTBTmMvE4JYQ== X-Received: by 2002:a17:902:2c83:: with SMTP id n3-v6mr3232953plb.211.1526147849984; Sat, 12 May 2018 10:57:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 12 May 2018 10:57:22 -0700 Message-Id: <20180512175724.5923-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512175724.5923-1-richard.henderson@linaro.org> References: <20180512175724.5923-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH 2/4] target/xtensa: Convert to DisasContextBase X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jcmvbkbc@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Acked-by: Max Filippov Tested-by: Max Filippov --- target/xtensa/translate.c | 89 +++++++++++++++++++-------------------- 1 file changed, 43 insertions(+), 46 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index a1e63f9661..cc48d105e9 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -48,16 +48,13 @@ =20 =20 struct DisasContext { + DisasContextBase base; const XtensaConfig *config; - TranslationBlock *tb; uint32_t pc; - uint32_t next_pc; int cring; int ring; uint32_t lbeg; uint32_t lend; - int is_jmp; - int singlestep_enabled; =20 bool sar_5bit; bool sar_m32_5bit; @@ -314,7 +311,7 @@ static void gen_exception_cause(DisasContext *dc, uint3= 2_t cause) tcg_temp_free(tcause); if (cause =3D=3D ILLEGAL_INSTRUCTION_CAUSE || cause =3D=3D SYSCALL_CAUSE) { - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; } } =20 @@ -336,7 +333,7 @@ static void gen_debug_exception(DisasContext *dc, uint3= 2_t cause) tcg_temp_free(tpc); tcg_temp_free(tcause); if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) { - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; } } =20 @@ -348,7 +345,7 @@ static bool gen_check_privilege(DisasContext *dc) } #endif gen_exception_cause(dc, PRIVILEGED_CAUSE); - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; return false; } =20 @@ -357,7 +354,7 @@ static bool gen_check_cpenable(DisasContext *dc, unsign= ed cp) if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) && !(dc->cpenable & (1 << cp))) { gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp); - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; return false; } return true; @@ -369,17 +366,17 @@ static void gen_jump_slot(DisasContext *dc, TCGv dest= , int slot) if (dc->icount) { tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount); } - if (dc->singlestep_enabled) { + if (dc->base.singlestep_enabled) { gen_exception(dc, EXCP_DEBUG); } else { if (slot >=3D 0) { tcg_gen_goto_tb(slot); - tcg_gen_exit_tb((uintptr_t)dc->tb + slot); + tcg_gen_exit_tb((uintptr_t)dc->base.tb + slot); } else { tcg_gen_exit_tb(0); } } - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_jump(DisasContext *dc, TCGv dest) @@ -391,7 +388,7 @@ static void gen_jumpi(DisasContext *dc, uint32_t dest, = int slot) { TCGv_i32 tmp =3D tcg_const_i32(dest); #ifndef CONFIG_USER_ONLY - if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) !=3D 0) { + if (((dc->base.pc_first ^ dest) & TARGET_PAGE_MASK) !=3D 0) { slot =3D -1; } #endif @@ -408,7 +405,7 @@ static void gen_callw_slot(DisasContext *dc, int callin= c, TCGv_i32 dest, tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN); tcg_temp_free(tcallinc); tcg_gen_movi_i32(cpu_R[callinc << 2], - (callinc << 30) | (dc->next_pc & 0x3fffffff)); + (callinc << 30) | (dc->base.pc_next & 0x3fffffff)); gen_jump_slot(dc, dest, slot); } =20 @@ -421,7 +418,7 @@ static void gen_callwi(DisasContext *dc, int callinc, u= int32_t dest, int slot) { TCGv_i32 tmp =3D tcg_const_i32(dest); #ifndef CONFIG_USER_ONLY - if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) !=3D 0) { + if (((dc->base.pc_first ^ dest) & TARGET_PAGE_MASK) !=3D 0) { slot =3D -1; } #endif @@ -432,15 +429,15 @@ static void gen_callwi(DisasContext *dc, int callinc,= uint32_t dest, int slot) static bool gen_check_loop_end(DisasContext *dc, int slot) { if (option_enabled(dc, XTENSA_OPTION_LOOP) && - !(dc->tb->flags & XTENSA_TBFLAG_EXCM) && - dc->next_pc =3D=3D dc->lend) { + !(dc->base.tb->flags & XTENSA_TBFLAG_EXCM) && + dc->base.pc_next =3D=3D dc->lend) { TCGLabel *label =3D gen_new_label(); =20 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label); tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1); gen_jumpi(dc, dc->lbeg, slot); gen_set_label(label); - gen_jumpi(dc, dc->next_pc, -1); + gen_jumpi(dc, dc->base.pc_next, -1); return true; } return false; @@ -449,7 +446,7 @@ static bool gen_check_loop_end(DisasContext *dc, int sl= ot) static void gen_jumpi_check_loop_end(DisasContext *dc, int slot) { if (!gen_check_loop_end(dc, slot)) { - gen_jumpi(dc, dc->next_pc, slot); + gen_jumpi(dc, dc->base.pc_next, slot); } } =20 @@ -500,12 +497,12 @@ static bool gen_check_sr(DisasContext *dc, uint32_t s= r, unsigned access) #ifndef CONFIG_USER_ONLY static bool gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr) { - if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_update_ccount(cpu_env); tcg_gen_mov_i32(d, cpu_SR[sr]); - if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { gen_io_end(); return true; } @@ -689,11 +686,11 @@ static bool gen_wsr_cpenable(DisasContext *dc, uint32= _t sr, TCGv_i32 v) =20 static void gen_check_interrupts(DisasContext *dc) { - if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_check_interrupts(cpu_env); - if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { gen_io_end(); } } @@ -747,11 +744,11 @@ static bool gen_wsr_ps(DisasContext *dc, uint32_t sr,= TCGv_i32 v) =20 static bool gen_wsr_ccount(DisasContext *dc, uint32_t sr, TCGv_i32 v) { - if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_wsr_ccount(cpu_env, v); - if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { gen_io_end(); gen_jumpi_check_loop_end(dc, 0); return true; @@ -788,11 +785,11 @@ static bool gen_wsr_ccompare(DisasContext *dc, uint32= _t sr, TCGv_i32 v) =20 tcg_gen_mov_i32(cpu_SR[sr], v); tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit); - if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_update_ccompare(cpu_env, tmp); - if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { gen_io_end(); gen_jumpi_check_loop_end(dc, 0); ret =3D true; @@ -892,14 +889,14 @@ static void gen_load_store_alignment(DisasContext *dc= , int shift, #ifndef CONFIG_USER_ONLY static void gen_waiti(DisasContext *dc, uint32_t imm4) { - TCGv_i32 pc =3D tcg_const_i32(dc->next_pc); + TCGv_i32 pc =3D tcg_const_i32(dc->base.pc_next); TCGv_i32 intlevel =3D tcg_const_i32(imm4); =20 - if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_waiti(cpu_env, pc, intlevel); - if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { gen_io_end(); } tcg_temp_free(pc); @@ -915,7 +912,7 @@ static bool gen_window_check1(DisasContext *dc, unsigne= d r1) TCGv_i32 w =3D tcg_const_i32(r1 / 4); =20 gen_helper_window_check(cpu_env, pc, w); - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; return false; } return true; @@ -966,7 +963,7 @@ static void disas_xtensa_insn(CPUXtensaState *env, Disa= sContext *dc) return; } =20 - dc->next_pc =3D dc->pc + len; + dc->base.pc_next =3D dc->pc + len; for (i =3D 1; i < len; ++i) { b[i] =3D cpu_ldub_code(env, dc->pc + i); } @@ -1026,10 +1023,10 @@ static void disas_xtensa_insn(CPUXtensaState *env, = DisasContext *dc) return; } } - if (dc->is_jmp =3D=3D DISAS_NEXT) { + if (dc->base.is_jmp =3D=3D DISAS_NEXT) { gen_check_loop_end(dc, 0); } - dc->pc =3D dc->next_pc; + dc->pc =3D dc->base.pc_next; } =20 static inline unsigned xtensa_insn_len(CPUXtensaState *env, DisasContext *= dc) @@ -1068,14 +1065,14 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) } =20 dc.config =3D env->config; - dc.singlestep_enabled =3D cs->singlestep_enabled; - dc.tb =3D tb; + dc.base.singlestep_enabled =3D cs->singlestep_enabled; + dc.base.tb =3D tb; dc.pc =3D pc_start; dc.ring =3D tb->flags & XTENSA_TBFLAG_RING_MASK; dc.cring =3D (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring; dc.lbeg =3D env->sregs[LBEG]; dc.lend =3D env->sregs[LEND]; - dc.is_jmp =3D DISAS_NEXT; + dc.base.is_jmp =3D DISAS_NEXT; dc.debug =3D tb->flags & XTENSA_TBFLAG_DEBUG; dc.icount =3D tb->flags & XTENSA_TBFLAG_ICOUNT; dc.cpenable =3D (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >> @@ -1100,14 +1097,14 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) tcg_gen_insn_start(dc.pc); ++insn_count; gen_exception(&dc, EXCP_YIELD); - dc.is_jmp =3D DISAS_NORETURN; + dc.base.is_jmp =3D DISAS_NORETURN; goto done; } if (tb->flags & XTENSA_TBFLAG_EXCEPTION) { tcg_gen_insn_start(dc.pc); ++insn_count; gen_exception(&dc, EXCP_DEBUG); - dc.is_jmp =3D DISAS_NORETURN; + dc.base.is_jmp =3D DISAS_NORETURN; goto done; } =20 @@ -1118,7 +1115,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) { tcg_gen_movi_i32(cpu_pc, dc.pc); gen_exception(&dc, EXCP_DEBUG); - dc.is_jmp =3D DISAS_NORETURN; + dc.base.is_jmp =3D DISAS_NORETURN; /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that @@ -1156,7 +1153,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) gen_exception(&dc, EXCP_DEBUG); break; } - } while (dc.is_jmp =3D=3D DISAS_NEXT && + } while (dc.base.is_jmp =3D=3D DISAS_NEXT && insn_count < max_insns && dc.pc - page_start < TARGET_PAGE_SIZE && dc.pc - page_start + xtensa_insn_len(env, &dc) <=3D TARGET_PAG= E_SIZE @@ -1175,7 +1172,7 @@ done: gen_io_end(); } =20 - if (dc.is_jmp =3D=3D DISAS_NEXT) { + if (dc.base.is_jmp =3D=3D DISAS_NEXT) { gen_jumpi(&dc, dc.pc, 0); } gen_tb_end(tb, insn_count); @@ -1480,7 +1477,7 @@ static void translate_break(DisasContext *dc, const u= int32_t arg[], static void translate_call0(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - tcg_gen_movi_i32(cpu_R[0], dc->next_pc); + tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next); gen_jumpi(dc, arg[0], 0); } =20 @@ -1498,7 +1495,7 @@ static void translate_callx0(DisasContext *dc, const = uint32_t arg[], if (gen_window_check1(dc, arg[0])) { TCGv_i32 tmp =3D tcg_temp_new_i32(); tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); - tcg_gen_movi_i32(cpu_R[0], dc->next_pc); + tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next); gen_jump(dc, tmp); tcg_temp_free(tmp); } @@ -1700,7 +1697,7 @@ static void translate_l32r(DisasContext *dc, const ui= nt32_t arg[], if (gen_window_check1(dc, arg[0])) { TCGv_i32 tmp; =20 - if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { + if (dc->base.tb->flags & XTENSA_TBFLAG_LITBASE) { tmp =3D tcg_const_i32(dc->raw_arg[1] - 1); tcg_gen_add_i32(tmp, cpu_SR[LITBASE], tmp); } else { @@ -1719,7 +1716,7 @@ static void translate_loop(DisasContext *dc, const ui= nt32_t arg[], TCGv_i32 tmp =3D tcg_const_i32(lend); =20 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[arg[0]], 1); - tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc); + tcg_gen_movi_i32(cpu_SR[LBEG], dc->base.pc_next); gen_helper_wsr_lend(cpu_env, tmp); tcg_temp_free(tmp); =20 @@ -1730,7 +1727,7 @@ static void translate_loop(DisasContext *dc, const ui= nt32_t arg[], gen_set_label(label); } =20 - gen_jumpi(dc, dc->next_pc, 0); + gen_jumpi(dc, dc->base.pc_next, 0); } } =20 --=20 2.17.0 From nobody Wed Oct 29 22:59:56 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH 3/4] target/xtensa: Change gen_intermediate_code dc to pointer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jcmvbkbc@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This will reduce the size of the patch in the next patch, where the context will have to be a pointer. Signed-off-by: Richard Henderson Acked-by: Max Filippov Tested-by: Max Filippov --- target/xtensa/translate.c | 122 +++++++++++++++++++------------------- 1 file changed, 61 insertions(+), 61 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index cc48d105e9..45f32dc71f 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1051,7 +1051,7 @@ static void gen_ibreak_check(CPUXtensaState *env, Dis= asContext *dc) void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { CPUXtensaState *env =3D cs->env_ptr; - DisasContext dc; + DisasContext dc1, *dc =3D &dc1; int insn_count =3D 0; int max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; uint32_t pc_start =3D tb->pc; @@ -1064,63 +1064,63 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) max_insns =3D TCG_MAX_INSNS; } =20 - dc.config =3D env->config; - dc.base.singlestep_enabled =3D cs->singlestep_enabled; - dc.base.tb =3D tb; - dc.pc =3D pc_start; - dc.ring =3D tb->flags & XTENSA_TBFLAG_RING_MASK; - dc.cring =3D (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring; - dc.lbeg =3D env->sregs[LBEG]; - dc.lend =3D env->sregs[LEND]; - dc.base.is_jmp =3D DISAS_NEXT; - dc.debug =3D tb->flags & XTENSA_TBFLAG_DEBUG; - dc.icount =3D tb->flags & XTENSA_TBFLAG_ICOUNT; - dc.cpenable =3D (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >> + dc->config =3D env->config; + dc->base.singlestep_enabled =3D cs->singlestep_enabled; + dc->base.tb =3D tb; + dc->pc =3D pc_start; + dc->ring =3D tb->flags & XTENSA_TBFLAG_RING_MASK; + dc->cring =3D (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc->ring; + dc->lbeg =3D env->sregs[LBEG]; + dc->lend =3D env->sregs[LEND]; + dc->base.is_jmp =3D DISAS_NEXT; + dc->debug =3D tb->flags & XTENSA_TBFLAG_DEBUG; + dc->icount =3D tb->flags & XTENSA_TBFLAG_ICOUNT; + dc->cpenable =3D (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >> XTENSA_TBFLAG_CPENABLE_SHIFT; - dc.window =3D ((tb->flags & XTENSA_TBFLAG_WINDOW_MASK) >> + dc->window =3D ((tb->flags & XTENSA_TBFLAG_WINDOW_MASK) >> XTENSA_TBFLAG_WINDOW_SHIFT); =20 - if (dc.config->isa) { - dc.insnbuf =3D xtensa_insnbuf_alloc(dc.config->isa); - dc.slotbuf =3D xtensa_insnbuf_alloc(dc.config->isa); + if (dc->config->isa) { + dc->insnbuf =3D xtensa_insnbuf_alloc(dc->config->isa); + dc->slotbuf =3D xtensa_insnbuf_alloc(dc->config->isa); } =20 - init_sar_tracker(&dc); - if (dc.icount) { - dc.next_icount =3D tcg_temp_local_new_i32(); + init_sar_tracker(dc); + if (dc->icount) { + dc->next_icount =3D tcg_temp_local_new_i32(); } =20 gen_tb_start(tb); =20 if ((tb_cflags(tb) & CF_USE_ICOUNT) && (tb->flags & XTENSA_TBFLAG_YIELD)) { - tcg_gen_insn_start(dc.pc); + tcg_gen_insn_start(dc->pc); ++insn_count; - gen_exception(&dc, EXCP_YIELD); - dc.base.is_jmp =3D DISAS_NORETURN; + gen_exception(dc, EXCP_YIELD); + dc->base.is_jmp =3D DISAS_NORETURN; goto done; } if (tb->flags & XTENSA_TBFLAG_EXCEPTION) { - tcg_gen_insn_start(dc.pc); + tcg_gen_insn_start(dc->pc); ++insn_count; - gen_exception(&dc, EXCP_DEBUG); - dc.base.is_jmp =3D DISAS_NORETURN; + gen_exception(dc, EXCP_DEBUG); + dc->base.is_jmp =3D DISAS_NORETURN; goto done; } =20 do { - tcg_gen_insn_start(dc.pc); + tcg_gen_insn_start(dc->pc); ++insn_count; =20 - if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) { - tcg_gen_movi_i32(cpu_pc, dc.pc); - gen_exception(&dc, EXCP_DEBUG); - dc.base.is_jmp =3D DISAS_NORETURN; + if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { + tcg_gen_movi_i32(cpu_pc, dc->pc); + gen_exception(dc, EXCP_DEBUG); + dc->base.is_jmp =3D DISAS_NORETURN; /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that the logic setting tb->size below does the right thing. */ - dc.pc +=3D 2; + dc->pc +=3D 2; break; } =20 @@ -1128,52 +1128,52 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) gen_io_start(); } =20 - if (dc.icount) { + if (dc->icount) { TCGLabel *label =3D gen_new_label(); =20 - tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1); - tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label); - tcg_gen_mov_i32(dc.next_icount, cpu_SR[ICOUNT]); - if (dc.debug) { - gen_debug_exception(&dc, DEBUGCAUSE_IC); + tcg_gen_addi_i32(dc->next_icount, cpu_SR[ICOUNT], 1); + tcg_gen_brcondi_i32(TCG_COND_NE, dc->next_icount, 0, label); + tcg_gen_mov_i32(dc->next_icount, cpu_SR[ICOUNT]); + if (dc->debug) { + gen_debug_exception(dc, DEBUGCAUSE_IC); } gen_set_label(label); } =20 - if (dc.debug) { - gen_ibreak_check(env, &dc); + if (dc->debug) { + gen_ibreak_check(env, dc); } =20 - disas_xtensa_insn(env, &dc); - if (dc.icount) { - tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount); + disas_xtensa_insn(env, dc); + if (dc->icount) { + tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount); } - if (cs->singlestep_enabled) { - tcg_gen_movi_i32(cpu_pc, dc.pc); - gen_exception(&dc, EXCP_DEBUG); + if (dc->base.singlestep_enabled) { + tcg_gen_movi_i32(cpu_pc, dc->pc); + gen_exception(dc, EXCP_DEBUG); break; } - } while (dc.base.is_jmp =3D=3D DISAS_NEXT && - insn_count < max_insns && - dc.pc - page_start < TARGET_PAGE_SIZE && - dc.pc - page_start + xtensa_insn_len(env, &dc) <=3D TARGET_PAG= E_SIZE - && !tcg_op_buf_full()); + } while (dc->base.is_jmp =3D=3D DISAS_NEXT && + insn_count < max_insns && + dc->pc - page_start < TARGET_PAGE_SIZE && + dc->pc - page_start + xtensa_insn_len(env, dc) <=3D TARGET_PA= GE_SIZE + && !tcg_op_buf_full()); done: - reset_sar_tracker(&dc); - if (dc.icount) { - tcg_temp_free(dc.next_icount); + reset_sar_tracker(dc); + if (dc->icount) { + tcg_temp_free(dc->next_icount); } - if (dc.config->isa) { - xtensa_insnbuf_free(dc.config->isa, dc.insnbuf); - xtensa_insnbuf_free(dc.config->isa, dc.slotbuf); + if (dc->config->isa) { + xtensa_insnbuf_free(dc->config->isa, dc->insnbuf); + xtensa_insnbuf_free(dc->config->isa, dc->slotbuf); } =20 if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } =20 - if (dc.base.is_jmp =3D=3D DISAS_NEXT) { - gen_jumpi(&dc, dc.pc, 0); + if (dc->base.is_jmp =3D=3D DISAS_NEXT) { + gen_jumpi(dc, dc->pc, 0); } gen_tb_end(tb, insn_count); =20 @@ -1183,12 +1183,12 @@ done: qemu_log_lock(); qemu_log("----------------\n"); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc.pc - pc_start); + log_target_disas(cs, pc_start, dc->pc - pc_start); qemu_log("\n"); qemu_log_unlock(); } #endif - tb->size =3D dc.pc - pc_start; + tb->size =3D dc->pc - pc_start; tb->icount =3D insn_count; } =20 --=20 2.17.0 From nobody Wed Oct 29 22:59:56 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152614813049647.529528083375226; Sat, 12 May 2018 11:02:10 -0700 (PDT) Received: from localhost ([::1]:60601 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fHYqP-0000Ir-Aw for importer@patchew.org; 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X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH 4/4] target/xtensa: Convert to TranslatorOps X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jcmvbkbc@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Acked-by: Max Filippov Tested-by: Max Filippov --- target/xtensa/translate.c | 229 ++++++++++++++++++++------------------ 1 file changed, 122 insertions(+), 107 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 45f32dc71f..9de45e4be4 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1048,148 +1048,163 @@ static void gen_ibreak_check(CPUXtensaState *env,= DisasContext *dc) } } =20 -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +static void xtensa_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cpu) { - CPUXtensaState *env =3D cs->env_ptr; - DisasContext dc1, *dc =3D &dc1; - int insn_count =3D 0; - int max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; - uint32_t pc_start =3D tb->pc; - uint32_t page_start =3D pc_start & TARGET_PAGE_MASK; - - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + CPUXtensaState *env =3D cpu->env_ptr; + uint32_t tb_flags =3D dc->base.tb->flags; =20 dc->config =3D env->config; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; - dc->base.tb =3D tb; - dc->pc =3D pc_start; - dc->ring =3D tb->flags & XTENSA_TBFLAG_RING_MASK; - dc->cring =3D (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc->ring; + dc->pc =3D dc->base.pc_first; + dc->ring =3D tb_flags & XTENSA_TBFLAG_RING_MASK; + dc->cring =3D (tb_flags & XTENSA_TBFLAG_EXCM) ? 0 : dc->ring; dc->lbeg =3D env->sregs[LBEG]; dc->lend =3D env->sregs[LEND]; - dc->base.is_jmp =3D DISAS_NEXT; - dc->debug =3D tb->flags & XTENSA_TBFLAG_DEBUG; - dc->icount =3D tb->flags & XTENSA_TBFLAG_ICOUNT; - dc->cpenable =3D (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >> + dc->debug =3D tb_flags & XTENSA_TBFLAG_DEBUG; + dc->icount =3D tb_flags & XTENSA_TBFLAG_ICOUNT; + dc->cpenable =3D (tb_flags & XTENSA_TBFLAG_CPENABLE_MASK) >> XTENSA_TBFLAG_CPENABLE_SHIFT; - dc->window =3D ((tb->flags & XTENSA_TBFLAG_WINDOW_MASK) >> + dc->window =3D ((tb_flags & XTENSA_TBFLAG_WINDOW_MASK) >> XTENSA_TBFLAG_WINDOW_SHIFT); =20 if (dc->config->isa) { dc->insnbuf =3D xtensa_insnbuf_alloc(dc->config->isa); dc->slotbuf =3D xtensa_insnbuf_alloc(dc->config->isa); } - init_sar_tracker(dc); +} + +static void xtensa_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + if (dc->icount) { dc->next_icount =3D tcg_temp_local_new_i32(); } +} =20 - gen_tb_start(tb); +static void xtensa_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + tcg_gen_insn_start(dcbase->pc_next); +} =20 - if ((tb_cflags(tb) & CF_USE_ICOUNT) && - (tb->flags & XTENSA_TBFLAG_YIELD)) { - tcg_gen_insn_start(dc->pc); - ++insn_count; +static bool xtensa_tr_breakpoint_check(DisasContextBase *dcbase, CPUState = *cpu, + const CPUBreakpoint *bp) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); + gen_exception(dc, EXCP_DEBUG); + dc->base.is_jmp =3D DISAS_NORETURN; + /* The address covered by the breakpoint must be included in + [tb->pc, tb->pc + tb->size) in order to for it to be + properly cleared -- thus we increment the PC here so that + the logic setting tb->size below does the right thing. */ + dc->base.pc_next +=3D 2; + return true; +} + +static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *c= pu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + CPUXtensaState *env =3D cpu->env_ptr; + target_ulong page_start; + + /* These two conditions only apply to the first insn in the TB, + but this is the first TranslateOps hook that allows exiting. */ + if ((tb_cflags(dc->base.tb) & CF_USE_ICOUNT) + && (dc->base.tb->flags & XTENSA_TBFLAG_YIELD)) { gen_exception(dc, EXCP_YIELD); dc->base.is_jmp =3D DISAS_NORETURN; - goto done; + return; } - if (tb->flags & XTENSA_TBFLAG_EXCEPTION) { - tcg_gen_insn_start(dc->pc); - ++insn_count; + if (dc->base.tb->flags & XTENSA_TBFLAG_EXCEPTION) { gen_exception(dc, EXCP_DEBUG); dc->base.is_jmp =3D DISAS_NORETURN; - goto done; + return; } =20 - do { - tcg_gen_insn_start(dc->pc); - ++insn_count; - - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { - tcg_gen_movi_i32(cpu_pc, dc->pc); - gen_exception(dc, EXCP_DEBUG); - dc->base.is_jmp =3D DISAS_NORETURN; - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - dc->pc +=3D 2; - break; - } - - if (insn_count =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { - gen_io_start(); - } - - if (dc->icount) { - TCGLabel *label =3D gen_new_label(); - - tcg_gen_addi_i32(dc->next_icount, cpu_SR[ICOUNT], 1); - tcg_gen_brcondi_i32(TCG_COND_NE, dc->next_icount, 0, label); - tcg_gen_mov_i32(dc->next_icount, cpu_SR[ICOUNT]); - if (dc->debug) { - gen_debug_exception(dc, DEBUGCAUSE_IC); - } - gen_set_label(label); - } - - if (dc->debug) { - gen_ibreak_check(env, dc); - } - - disas_xtensa_insn(env, dc); - if (dc->icount) { - tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount); - } - if (dc->base.singlestep_enabled) { - tcg_gen_movi_i32(cpu_pc, dc->pc); - gen_exception(dc, EXCP_DEBUG); - break; - } - } while (dc->base.is_jmp =3D=3D DISAS_NEXT && - insn_count < max_insns && - dc->pc - page_start < TARGET_PAGE_SIZE && - dc->pc - page_start + xtensa_insn_len(env, dc) <=3D TARGET_PA= GE_SIZE - && !tcg_op_buf_full()); -done: - reset_sar_tracker(dc); if (dc->icount) { - tcg_temp_free(dc->next_icount); + TCGLabel *label =3D gen_new_label(); + + tcg_gen_addi_i32(dc->next_icount, cpu_SR[ICOUNT], 1); + tcg_gen_brcondi_i32(TCG_COND_NE, dc->next_icount, 0, label); + tcg_gen_mov_i32(dc->next_icount, cpu_SR[ICOUNT]); + if (dc->debug) { + gen_debug_exception(dc, DEBUGCAUSE_IC); + } + gen_set_label(label); } + + if (dc->debug) { + gen_ibreak_check(env, dc); + } + + disas_xtensa_insn(env, dc); + + if (dc->icount) { + tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount); + } + + /* End the TB if the next insn will cross into the next page. */ + page_start =3D dc->base.pc_first & TARGET_PAGE_MASK; + if (dc->base.is_jmp =3D=3D DISAS_NEXT && + dc->pc - page_start < TARGET_PAGE_SIZE && + dc->pc - page_start + xtensa_insn_len(env, dc) <=3D TARGET_PAGE_SI= ZE) { + dc->base.is_jmp =3D DISAS_TOO_MANY; + } +} + +static void xtensa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + reset_sar_tracker(dc); if (dc->config->isa) { xtensa_insnbuf_free(dc->config->isa, dc->insnbuf); xtensa_insnbuf_free(dc->config->isa, dc->slotbuf); } - - if (tb_cflags(tb) & CF_LAST_IO) { - gen_io_end(); + if (dc->icount) { + tcg_temp_free(dc->next_icount); } =20 - if (dc->base.is_jmp =3D=3D DISAS_NEXT) { - gen_jumpi(dc, dc->pc, 0); + switch (dc->base.is_jmp) { + case DISAS_NORETURN: + break; + case DISAS_TOO_MANY: + if (dc->base.singlestep_enabled) { + tcg_gen_movi_i32(cpu_pc, dc->pc); + gen_exception(dc, EXCP_DEBUG); + } else { + gen_jumpi(dc, dc->pc, 0); + } + break; + default: + g_assert_not_reached(); } - gen_tb_end(tb, insn_count); +} =20 -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(pc_start)) { - qemu_log_lock(); - qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc->pc - pc_start); - qemu_log("\n"); - qemu_log_unlock(); - } -#endif - tb->size =3D dc->pc - pc_start; - tb->icount =3D insn_count; +static void xtensa_tr_disas_log(const DisasContextBase *dcbase, CPUState *= cpu) +{ + qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); + log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); +} + +static const TranslatorOps xtensa_translator_ops =3D { + .init_disas_context =3D xtensa_tr_init_disas_context, + .tb_start =3D xtensa_tr_tb_start, + .insn_start =3D xtensa_tr_insn_start, + .breakpoint_check =3D xtensa_tr_breakpoint_check, + .translate_insn =3D xtensa_tr_translate_insn, + .tb_stop =3D xtensa_tr_tb_stop, + .disas_log =3D xtensa_tr_disas_log, +}; + +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +{ + DisasContext dc =3D {}; + translator_loop(&xtensa_translator_ops, &dc.base, cpu, tb); } =20 void xtensa_cpu_dump_state(CPUState *cs, FILE *f, --=20 2.17.0