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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/V/ku6SmT7UDnjk0P7hS1ShPNhtIhUSO+Jw3IebMoWQ=; b=LHyOv8UYJ57cIkCqC1PjTjZREz5YE75rTOkL0aGC/FSsiaax7CBFPd9tyk62x+3zwL TmlLVq7YmGqStqXkSbA2fHE5W5pLATOLKqdHx+4PNPs2OjF2kfgJtMKS06Pf1nAM+n9D +reVcQG8unJ3zuayd3uvEna1xNPL5zXLbOU9A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/V/ku6SmT7UDnjk0P7hS1ShPNhtIhUSO+Jw3IebMoWQ=; b=pPQQ2d9DNRVWu8AsWIKWOVGoJqQ2b1AIrRxBta6pkj6nGngKbEw6LpvL21du2kwp3H KVE/foMZPCgTeEM8AE1LBXRIJUT1NFvtvq7KC4mvavXr2u7Ajtx17/jxcIpN/9PMJ4t6 slSzG01UEj6clMLfWMflm0fxBHZulVd+qfNgc31vHAvAft1Pe4ILqZ0hzY+FdG3DvrVY u4kb2UibmBo5tDQyFqQFIFFOnlMivAV8EUUWz8RnJd1Fq42oivm6E5sA/w7V+Edg7wWk 6MKjQI+YFRvPzJ2xtg2QLmi09W1C4ziyvKrFJdQnIrsw7D2sE8rnb+r8IHCU4ePHz3oY eSOQ== X-Gm-Message-State: ALKqPwcNuKodCtxXqVgxcM6ft7caHkDQA+c1Vep2BXrH14trUF70gJiD 1dNGIY08Mdvcr6QMCMx1t8iToA0Uk30= X-Google-Smtp-Source: AB8JxZpyyJf14X+NnRdWp6JHtPpsvZALMYpH0tq6J4Gt4vJBHPTkr33mvqrw3VIGv9JM0Xt0yDWj6A== X-Received: by 2002:a62:d905:: with SMTP id s5-v6mr1015028pfg.20.1526085805795; Fri, 11 May 2018 17:43:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:42:52 -0700 Message-Id: <20180512004311.9299-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512004311.9299-1-richard.henderson@linaro.org> References: <20180512004311.9299-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v2 08/27] fpu/softfloat: Replace float_class_dnan with parts_default_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" With a canonical representation of NaNs, we can return the default nan directly rather than delay the expansion until the final format is known. Note one case where we uselessly assigned to a.sign, which was overwritten/ignored later when expanding float_class_dnan. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- fpu/softfloat-specialize.h | 37 +++++++++++++++++++++++++++++++++++++ fpu/softfloat.c | 38 +++++++++++--------------------------- 2 files changed, 48 insertions(+), 27 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 515cb12cfa..0d3d81a52b 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -101,6 +101,43 @@ static bool parts_is_snan_frac(uint64_t frac, float_st= atus *status) #endif } =20 +/*------------------------------------------------------------------------= ---- +| The pattern for a default generated deconstructed floating-point NaN. +*-------------------------------------------------------------------------= ---*/ + +static FloatParts parts_default_nan(float_status *status) +{ + bool sign =3D 0; + uint64_t frac; + +#if defined(TARGET_SPARC) || defined(TARGET_M68K) + frac =3D (1ULL << DECOMPOSED_BINARY_POINT) - 1; +#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) = || \ + defined(TARGET_S390X) || defined(TARGET_RISCV) + frac =3D 1ULL << (DECOMPOSED_BINARY_POINT - 1); +#elif defined(TARGET_HPPA) + frac =3D 1ULL << (DECOMPOSED_BINARY_POINT - 2); +#else + if (status->snan_bit_is_one) { + frac =3D (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; + } else { +#if defined(TARGET_MIPS) + frac =3D 1ULL << (DECOMPOSED_BINARY_POINT - 1); +#else + frac =3D 1ULL << (DECOMPOSED_BINARY_POINT - 1); + sign =3D 1; +#endif + } +#endif + + return (FloatParts) { + .cls =3D float_class_qnan, + .sign =3D sign, + .exp =3D INT_MAX, + .frac =3D frac + }; +} + /*------------------------------------------------------------------------= ---- | The pattern for a default generated half-precision NaN. *-------------------------------------------------------------------------= ---*/ diff --git a/fpu/softfloat.c b/fpu/softfloat.c index cb68f2eb20..d16b11a85b 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -188,7 +188,6 @@ typedef enum __attribute__ ((__packed__)) { float_class_inf, float_class_qnan, /* all NaNs from here */ float_class_snan, - float_class_dnan, float_class_msnan, /* maybe silenced */ } FloatClass; =20 @@ -494,8 +493,6 @@ static FloatParts float16_unpack_canonical(float16 f, f= loat_status *s) static float16 float16_round_pack_canonical(FloatParts p, float_status *s) { switch (p.cls) { - case float_class_dnan: - return float16_default_nan(s); case float_class_msnan: p.frac >>=3D float16_params.frac_shift; return float16_maybe_silence_nan(float16_pack_raw(p), s); @@ -513,8 +510,6 @@ static FloatParts float32_unpack_canonical(float32 f, f= loat_status *s) static float32 float32_round_pack_canonical(FloatParts p, float_status *s) { switch (p.cls) { - case float_class_dnan: - return float32_default_nan(s); case float_class_msnan: p.frac >>=3D float32_params.frac_shift; return float32_maybe_silence_nan(float32_pack_raw(p), s); @@ -532,8 +527,6 @@ static FloatParts float64_unpack_canonical(float64 f, f= loat_status *s) static float64 float64_round_pack_canonical(FloatParts p, float_status *s) { switch (p.cls) { - case float_class_dnan: - return float64_default_nan(s); case float_class_msnan: p.frac >>=3D float64_params.frac_shift; return float64_maybe_silence_nan(float64_pack_raw(p), s); @@ -566,7 +559,7 @@ static FloatParts return_nan(FloatParts a, float_status= *s) /* fall through */ case float_class_qnan: if (s->default_nan_mode) { - a.cls =3D float_class_dnan; + return parts_default_nan(s); } break; =20 @@ -583,7 +576,7 @@ static FloatParts pick_nan(FloatParts a, FloatParts b, = float_status *s) } =20 if (s->default_nan_mode) { - a.cls =3D float_class_dnan; + return parts_default_nan(s); } else { if (pickNaN(is_qnan(a.cls), is_snan(a.cls), is_qnan(b.cls), is_snan(b.cls), @@ -614,8 +607,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatPa= rts b, FloatParts c, /* Note that this check is after pickNaNMulAdd so that function * has an opportunity to set the Invalid flag. */ - a.cls =3D float_class_dnan; - return a; + which =3D 3; } =20 switch (which) { @@ -628,8 +620,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatPa= rts b, FloatParts c, a =3D c; break; case 3: - a.cls =3D float_class_dnan; - return a; + return parts_default_nan(s); default: g_assert_not_reached(); } @@ -682,7 +673,7 @@ static FloatParts addsub_floats(FloatParts a, FloatPart= s b, bool subtract, if (a.cls =3D=3D float_class_inf) { if (b.cls =3D=3D float_class_inf) { float_raise(float_flag_invalid, s); - a.cls =3D float_class_dnan; + return parts_default_nan(s); } return a; } @@ -828,9 +819,7 @@ static FloatParts mul_floats(FloatParts a, FloatParts b= , float_status *s) if ((a.cls =3D=3D float_class_inf && b.cls =3D=3D float_class_zero) || (a.cls =3D=3D float_class_zero && b.cls =3D=3D float_class_inf)) { s->float_exception_flags |=3D float_flag_invalid; - a.cls =3D float_class_dnan; - a.sign =3D sign; - return a; + return parts_default_nan(s); } /* Multiply by 0 or Inf */ if (a.cls =3D=3D float_class_inf || a.cls =3D=3D float_class_zero) { @@ -908,8 +897,7 @@ static FloatParts muladd_floats(FloatParts a, FloatPart= s b, FloatParts c, =20 if (inf_zero) { s->float_exception_flags |=3D float_flag_invalid; - a.cls =3D float_class_dnan; - return a; + return parts_default_nan(s); } =20 if (flags & float_muladd_negate_c) { @@ -933,12 +921,12 @@ static FloatParts muladd_floats(FloatParts a, FloatPa= rts b, FloatParts c, if (c.cls =3D=3D float_class_inf) { if (p_class =3D=3D float_class_inf && p_sign !=3D c.sign) { s->float_exception_flags |=3D float_flag_invalid; - a.cls =3D float_class_dnan; + return parts_default_nan(s); } else { a.cls =3D float_class_inf; a.sign =3D c.sign ^ sign_flip; + return a; } - return a; } =20 if (p_class =3D=3D float_class_inf) { @@ -1148,8 +1136,7 @@ static FloatParts div_floats(FloatParts a, FloatParts= b, float_status *s) && (a.cls =3D=3D float_class_inf || a.cls =3D=3D float_class_zero)) { s->float_exception_flags |=3D float_flag_invalid; - a.cls =3D float_class_dnan; - return a; + return parts_default_nan(s); } /* Inf / x or 0 / x */ if (a.cls =3D=3D float_class_inf || a.cls =3D=3D float_class_zero) { @@ -1347,7 +1334,6 @@ static int64_t round_to_int_and_pack(FloatParts in, i= nt rmode, switch (p.cls) { case float_class_snan: case float_class_qnan: - case float_class_dnan: case float_class_msnan: s->float_exception_flags =3D orig_flags | float_flag_invalid; return max; @@ -1439,7 +1425,6 @@ static uint64_t round_to_uint_and_pack(FloatParts in,= int rmode, uint64_t max, switch (p.cls) { case float_class_snan: case float_class_qnan: - case float_class_dnan: case float_class_msnan: s->float_exception_flags =3D orig_flags | float_flag_invalid; return max; @@ -1940,8 +1925,7 @@ static FloatParts sqrt_float(FloatParts a, float_stat= us *s, const FloatFmt *p) } if (a.sign) { s->float_exception_flags |=3D float_flag_invalid; - a.cls =3D float_class_dnan; - return a; + return parts_default_nan(s); } if (a.cls =3D=3D float_class_inf) { return a; /* sqrt(+inf) =3D +inf */ --=20 2.17.0