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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CZ8t3rsGP1Vnm6i0MzTN7S1/lYSmU4XX4UAXyYCKUoA=; b=kAv9PJ7Zw5WZHg57XFZgcQfiJ0wip0nYIcnf7VKsrG8GdR1QD6I35sDs7w+Ug9UYtR sncjMP4gSyZyonOSiKgEHbgE48ciFzQYhyMxsD+5LKZTzKn4NStgZ4DZwXNMQP/uU/2N JQtjGGJE5oSHY8Cv+IhVu2Kf6N7VCgFvOINHI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CZ8t3rsGP1Vnm6i0MzTN7S1/lYSmU4XX4UAXyYCKUoA=; b=dgUbL5+n5I8jbgOaEGYznzDU8mhCXppwDPbOy8SGw4+5wRytKXsWyDAbIC48/XYNjZ e8ltn6XM3QQWgZW+SKwLW5xfd/6/Czm+Rw4ZjlBFJJRyAfweY65m+dDElsMh/CdDZZ0L ytRUcpCdQuH7qIIcY9EsvyL6KvPPkQB46jK7IT08f2GAeXkDsTu42BHT6Wu8SsoB/s8h hzOyz4lXzvLWWgEDa8EBxRoXdkg0T0F1ZPRhZoIg0WIxNPUyXmcNkVPFYmmHWiIUhndW nNV4OQpZZlXYFOxzkxoM2kwzp+Jze+SFm2gnUUHyCo1mg0szr3ExE6OgxkPJeQG6g5c8 oucw== X-Gm-Message-State: ALKqPwfcPIhsfnz3dyDWG1jFPRLNJr2QSciBVKKySJT35C5GTqCuCjbJ 52TcdMFf5SUodC2jB8ujvHMA+Kd0S5k= X-Google-Smtp-Source: AB8JxZp8emkRigt3q6b/fYQ+WdrdJ+LfqToToaUu6QIozY99sh5VfORACKjeOUll6FdBWKof4+JDWQ== X-Received: by 2002:a65:5b4d:: with SMTP id y13-v6mr1005824pgr.152.1526085814061; Fri, 11 May 2018 17:43:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:42:58 -0700 Message-Id: <20180512004311.9299-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512004311.9299-1-richard.henderson@linaro.org> References: <20180512004311.9299-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v2 14/27] target/arm: squash FZ16 behaviour for conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Alex Benn=C3=A9e The ARM ARM specifies FZ16 is suppressed for conversions. Rather than pushing this logic into the softfloat code we can simply save the FZ state and temporarily disable it for the softfloat call. Signed-off-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v4 - float16_to_floatX squished the wrong softfloat bit for FZ16; need to adjust input denormals in this case. --- target/arm/helper.c | 40 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 36 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a1c1dc5bbe..e05c7230d4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11542,22 +11542,54 @@ uint32_t HELPER(set_neon_rmode)(uint32_t rmode, C= PUARMState *env) /* Half precision conversions. */ float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_m= ode) { - return float16_to_float32(a, !ahp_mode, fpstp); + /* Squash FZ16 to 0 for the duration of conversion. In this case, + * it would affect flushing input denormals. + */ + float_status *fpst =3D fpstp; + flag save =3D get_flush_inputs_to_zero(fpst); + set_flush_inputs_to_zero(false, fpst); + float32 r =3D float16_to_float32(a, !ahp_mode, fpst); + set_flush_inputs_to_zero(save, fpst); + return r; } =20 float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_m= ode) { - return float32_to_float16(a, !ahp_mode, fpstp); + /* Squash FZ16 to 0 for the duration of conversion. In this case, + * it would affect flushing output denormals. + */ + float_status *fpst =3D fpstp; + flag save =3D get_flush_to_zero(fpst); + set_flush_to_zero(false, fpst); + float16 r =3D float32_to_float16(a, !ahp_mode, fpst); + set_flush_to_zero(save, fpst); + return r; } =20 float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_m= ode) { - return float16_to_float64(a, !ahp_mode, fpstp); + /* Squash FZ16 to 0 for the duration of conversion. In this case, + * it would affect flushing input denormals. + */ + float_status *fpst =3D fpstp; + flag save =3D get_flush_inputs_to_zero(fpst); + set_flush_inputs_to_zero(false, fpst); + float64 r =3D float16_to_float64(a, !ahp_mode, fpst); + set_flush_inputs_to_zero(save, fpst); + return r; } =20 float16 HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_m= ode) { - return float64_to_float16(a, !ahp_mode, fpstp); + /* Squash FZ16 to 0 for the duration of conversion. In this case, + * it would affect flushing output denormals. + */ + float_status *fpst =3D fpstp; + flag save =3D get_flush_to_zero(fpst); + set_flush_to_zero(false, fpst); + float16 r =3D float64_to_float16(a, !ahp_mode, fpst); + set_flush_to_zero(save, fpst); + return r; } =20 #define float32_two make_float32(0x40000000) --=20 2.17.0