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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id v186-v6sm7599735pfb.45.2018.05.11.17.32.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:32:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Gl9IacEMEk7hTYbHfUyGESBtRu8Edb0SzjekHtJHhvI=; b=U8soI7RGo+8JXIOGQ6PNoFU87O++gLbddTBJRpGQds3qnpzvVqpncg1I+skDk791tG 3aZflIhuFy5UsmyO3KfSQ8Tz5181ld6Pl7f2Ekn/s+z9XmnZnrct4zOCLuPvuMdrj5sV P4IG74m8cTk437f9nxrGg1yrYuYVvTrRI1M+Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Gl9IacEMEk7hTYbHfUyGESBtRu8Edb0SzjekHtJHhvI=; b=SqkN0Y23IHVll+vJNEmX9RhmTLpBLbUgnvfcfBUuIWRQAZpwuTxekDi35+PNihsrf/ L8x6eTlkvG0WPXqu1pq0OE4sNZ9bO/ifpOEww/aTsohz9rCGcdtI7gzeunYsAbJay0hd Ykh49fVCJpNnqEE25XyhC2/Hk37O9lt1wU3s9M2cD2fMFp6rhUNHUAuWdVWe0jNHW1xY b2KJh/Is5ND9IYAz77MDHQNbBOQYXoBdb3wr0MjaFIkSJXdbv/zHb4SEANKMUQ12CVzz w2mk6fhzg93vMJYF/5O+sR6SodTJgJY5WxuXlNxi55oModCgPCRxBkE0y0W1F5zLWkRW 4JPQ== X-Gm-Message-State: ALKqPwcaiIFMwPtMN3TYRnJZdWnPzA8kLznl/S329xl4chKZRGa5nI6w r2tEXFTWfwSrQ1KusHsfVLkOpoQKbkM= X-Google-Smtp-Source: AB8JxZrcsTk3llwlnAX4aZog9SFwh2HCD44mo6GGHbSwTRkwCls/BBLt0YQ35JlKG3EW16x7HlO29A== X-Received: by 2002:a17:902:4545:: with SMTP id m63-v6mr269459pld.268.1526085147619; Fri, 11 May 2018 17:32:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:32:11 -0700 Message-Id: <20180512003217.9105-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512003217.9105-1-richard.henderson@linaro.org> References: <20180512003217.9105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH v4 05/11] target/arm: Introduce and use read_fp_hreg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/translate-a64.c | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d0ed125442..78f12daaf6 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -615,6 +615,14 @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg) return v; } =20 +static TCGv_i32 read_fp_hreg(DisasContext *s, int reg) +{ + TCGv_i32 v =3D tcg_temp_new_i32(); + + tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16)); + return v; +} + /* Clear the bits above an N-bit vector, for N =3D (is_q ? 128 : 64). * If SVE is not enabled, then there are only 128 bits in the vector. */ @@ -4881,11 +4889,9 @@ static void disas_fp_csel(DisasContext *s, uint32_t = insn) static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int r= n) { TCGv_ptr fpst =3D NULL; - TCGv_i32 tcg_op =3D tcg_temp_new_i32(); + TCGv_i32 tcg_op =3D read_fp_hreg(s, rn); TCGv_i32 tcg_res =3D tcg_temp_new_i32(); =20 - read_vec_element_i32(s, tcg_op, rn, 0, MO_16); - switch (opcode) { case 0x0: /* FMOV */ tcg_gen_mov_i32(tcg_res, tcg_op); @@ -7784,13 +7790,10 @@ static void disas_simd_scalar_three_reg_diff(DisasC= ontext *s, uint32_t insn) tcg_temp_free_i64(tcg_op2); tcg_temp_free_i64(tcg_res); } else { - TCGv_i32 tcg_op1 =3D tcg_temp_new_i32(); - TCGv_i32 tcg_op2 =3D tcg_temp_new_i32(); + TCGv_i32 tcg_op1 =3D read_fp_hreg(s, rn); + TCGv_i32 tcg_op2 =3D read_fp_hreg(s, rm); TCGv_i64 tcg_res =3D tcg_temp_new_i64(); =20 - read_vec_element_i32(s, tcg_op1, rn, 0, MO_16); - read_vec_element_i32(s, tcg_op2, rm, 0, MO_16); - gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2); gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_r= es); =20 @@ -8331,13 +8334,10 @@ static void disas_simd_scalar_three_reg_same_fp16(D= isasContext *s, =20 fpst =3D get_fpstatus_ptr(true); =20 - tcg_op1 =3D tcg_temp_new_i32(); - tcg_op2 =3D tcg_temp_new_i32(); + tcg_op1 =3D read_fp_hreg(s, rn); + tcg_op2 =3D read_fp_hreg(s, rm); tcg_res =3D tcg_temp_new_i32(); =20 - read_vec_element_i32(s, tcg_op1, rn, 0, MO_16); - read_vec_element_i32(s, tcg_op2, rm, 0, MO_16); - switch (fpopcode) { case 0x03: /* FMULX */ gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst); @@ -12235,11 +12235,9 @@ static void disas_simd_two_reg_misc_fp16(DisasCont= ext *s, uint32_t insn) } =20 if (is_scalar) { - TCGv_i32 tcg_op =3D tcg_temp_new_i32(); + TCGv_i32 tcg_op =3D read_fp_hreg(s, rn); TCGv_i32 tcg_res =3D tcg_temp_new_i32(); =20 - read_vec_element_i32(s, tcg_op, rn, 0, MO_16); - switch (fpop) { case 0x1a: /* FCVTNS */ case 0x1b: /* FCVTMS */ --=20 2.17.0