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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id r76-v6sm4509462pfl.1.2018.05.10.21.23.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 21:23:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fdKMSpPgSCU+i/C9BazEFLV/D4k9opP07/GXYcH8Yns=; b=ie/c6ReyIfVvTq/ZJQZIhWnuj8VpTQFbeHBiDADiIV159XNOhtmQ+vkB+3xjKehO63 nG10u3d0oVFxhGyXEgfkak3EKyG2m5O1ySQRhy9YMDEpsu3MBFEaoP6kT0QgYZCHwmV5 25CBoTIRJu7ZROGjeYER3gqwztAKsZOS/PrS0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fdKMSpPgSCU+i/C9BazEFLV/D4k9opP07/GXYcH8Yns=; b=Sv5U+/ceWXzWb0cEeWNXYqZXCy9qdB+pE7tuR2sv0qoVp2bFGs3YZvE4m54FZxQobO MWZNDpnkR5kdUoLJSTOcwU1Cy/Y32AZ7OxpIq3OgQo13rWJRoGdGnTOYz0l35LGtIoV2 Uytm3dWEAvldPXx9ARn4rYHe2WcuEV0pcH9toYSiHBa5TxXXiX0yytqQyDsCG8OYBU/6 OpkUt4idXpcvg78HdKh/ZSIqXKPg5ydtSbNAKQvcBZB1p/WfTm6B4OwLClvrWpkCvbUC UTJ2rw9z+tbiUbbYhBb86Z+M/1kwYUmBwHETPlx+H8iqgeM6eHKMFAxXLfuOekvV+8e6 ZMzg== X-Gm-Message-State: ALKqPwcItbE8JdAqTWa49tgJSfqwoGoj4nMd+3VQp2G3OtyU0Si/+0VZ RfFKU3dYFDqcaPuNltYu622w+Qcs7qA= X-Google-Smtp-Source: AB8JxZrcU+XYDbYS9Kzup/1E6xrR84+tTwS0PqxitJ3kOgC02KhR5H9wVFt+9vrE42GLpX2+WnLXmA== X-Received: by 2002:a17:902:28e8:: with SMTP id f95-v6mr4029909plb.250.1526012618423; Thu, 10 May 2018 21:23:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 21:23:19 -0700 Message-Id: <20180511042324.5070-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511042324.5070-1-richard.henderson@linaro.org> References: <20180511042324.5070-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PULL 08/13] target/openrisc: Convert dec_logic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Stafford Horne Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Acked-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 62 +++++++++++++++--------------------- target/openrisc/insns.decode | 6 ++++ 2 files changed, 32 insertions(+), 36 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 8ca01e1a33..f2f9a0c0d2 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -999,42 +999,36 @@ static bool trans_l_msbu(DisasContext *dc, arg_ab *a,= uint32_t insn) return true; } =20 -static void dec_logic(DisasContext *dc, uint32_t insn) +static bool trans_l_slli(DisasContext *dc, arg_dal *a, uint32_t insn) { - uint32_t op0; - uint32_t rd, ra, L6, S6; - op0 =3D extract32(insn, 6, 2); - rd =3D extract32(insn, 21, 5); - ra =3D extract32(insn, 16, 5); - L6 =3D extract32(insn, 0, 6); - S6 =3D L6 & (TARGET_LONG_BITS - 1); + LOG_DIS("l.slli r%d, r%d, %d\n", a->d, a->a, a->l); + check_r0_write(a->d); + tcg_gen_shli_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1= )); + return true; +} =20 - check_r0_write(rd); - switch (op0) { - case 0x00: /* l.slli */ - LOG_DIS("l.slli r%d, r%d, %d\n", rd, ra, L6); - tcg_gen_shli_tl(cpu_R[rd], cpu_R[ra], S6); - break; +static bool trans_l_srli(DisasContext *dc, arg_dal *a, uint32_t insn) +{ + LOG_DIS("l.srli r%d, r%d, %d\n", a->d, a->a, a->l); + check_r0_write(a->d); + tcg_gen_shri_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1= )); + return true; +} =20 - case 0x01: /* l.srli */ - LOG_DIS("l.srli r%d, r%d, %d\n", rd, ra, L6); - tcg_gen_shri_tl(cpu_R[rd], cpu_R[ra], S6); - break; +static bool trans_l_srai(DisasContext *dc, arg_dal *a, uint32_t insn) +{ + LOG_DIS("l.srai r%d, r%d, %d\n", a->d, a->a, a->l); + check_r0_write(a->d); + tcg_gen_sari_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1= )); + return true; +} =20 - case 0x02: /* l.srai */ - LOG_DIS("l.srai r%d, r%d, %d\n", rd, ra, L6); - tcg_gen_sari_tl(cpu_R[rd], cpu_R[ra], S6); - break; - - case 0x03: /* l.rori */ - LOG_DIS("l.rori r%d, r%d, %d\n", rd, ra, L6); - tcg_gen_rotri_tl(cpu_R[rd], cpu_R[ra], S6); - break; - - default: - gen_illegal_exception(dc); - break; - } +static bool trans_l_rori(DisasContext *dc, arg_dal *a, uint32_t insn) +{ + LOG_DIS("l.rori r%d, r%d, %d\n", a->d, a->a, a->l); + check_r0_write(a->d); + tcg_gen_rotri_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - = 1)); + return true; } =20 static void dec_M(DisasContext *dc, uint32_t insn) @@ -1491,10 +1485,6 @@ static void disas_openrisc_insn(DisasContext *dc, Op= enRISCCPU *cpu) dec_M(dc, insn); break; =20 - case 0x2e: - dec_logic(dc, insn); - break; - case 0x2f: dec_compi(dc, insn); break; diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode index 7240c6fb77..fb8ba5812a 100644 --- a/target/openrisc/insns.decode +++ b/target/openrisc/insns.decode @@ -20,6 +20,7 @@ &dab d a b &da d a &ab a b +&dal d a l =20 #### # System Instructions @@ -130,3 +131,8 @@ l_mac 110001 ----- a:5 b:5 ------- 0001 l_macu 110001 ----- a:5 b:5 ------- 0011 l_msb 110001 ----- a:5 b:5 ------- 0010 l_msbu 110001 ----- a:5 b:5 ------- 0100 + +l_slli 101110 d:5 a:5 -------- 00 l:6 +l_srli 101110 d:5 a:5 -------- 01 l:6 +l_srai 101110 d:5 a:5 -------- 10 l:6 +l_rori 101110 d:5 a:5 -------- 11 l:6 --=20 2.17.0