From nobody Thu Oct 30 15:33:07 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526013224506185.0288066312478; Thu, 10 May 2018 21:33:44 -0700 (PDT) Received: from localhost ([::1]:36718 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fGzkV-0002ya-M8 for importer@patchew.org; Fri, 11 May 2018 00:33:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55681) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fGzaq-0000hD-4T for qemu-devel@nongnu.org; Fri, 11 May 2018 00:23:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fGzao-00089D-OL for qemu-devel@nongnu.org; Fri, 11 May 2018 00:23:44 -0400 Received: from mail-pl0-x243.google.com ([2607:f8b0:400e:c01::243]:42027) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fGzao-000890-GE for qemu-devel@nongnu.org; Fri, 11 May 2018 00:23:42 -0400 Received: by mail-pl0-x243.google.com with SMTP id u6-v6so2541759pls.9 for ; Thu, 10 May 2018 21:23:42 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id r76-v6sm4509462pfl.1.2018.05.10.21.23.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 21:23:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FlkcSexzv4clfZ/4+GmlMcHpJQ9S7bQqU4zoMTiVRTA=; b=KtXmRnrGiAl01kV3RDXolu+aWTDuYz60KU17DXbk4Mwy6WIo9DuDxIbl77IlKlIOhc VodTGaG0s897tzH+3KT4mzg9OsciVep2/cjKk8fu+8D3Ormwwo9WL0FQ705lSDNp12ia XQyROqyqRsE2QV+y/mUGhYgxNmDjHZV0N+XgA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FlkcSexzv4clfZ/4+GmlMcHpJQ9S7bQqU4zoMTiVRTA=; b=r7Rb01o02UJkKc88gwyVHIRsNOkF136AHyPeVlwZAIk0c9sS4aB9yMG2swYSSMoygC dbWKlopitfU4w58SKn5qmp9RbkuVfCYx4HHodNMkNvHbuszlsy8poO5OO6UWC9ieFxBM kimriloxKDqkMMi7CMrzBxhBXr7AZGzBwuHyspECRgjki83lGY9qwd/SWbf1lCqpOOVk lHB6WARVaYaLS9lKq7yc8RkoXwWFoS3rrLNpblRo085FrOD82C6hPiC7TvVQczla1+7u NB2iNI1jP63UF04Wr37dzJcMgIBPdsrSh8ej0Dg+SfcQ7b/7lMLMOxcOmQG/RcZ6k7KG LX1g== X-Gm-Message-State: ALKqPweL5zlra3jOoOE9zP+/Fn4AVNS9XWXuJWPiGC6KMs5wJyj7m3Hh 9NB439Cz8sy2j++C3tK5oGAmJQPPhmI= X-Google-Smtp-Source: AB8JxZrxej4jxHio1DSjBG4z05suhhZXiThMNylCoZHMScrgEaR9qb9iNEA8rdf4SeA+U1NrcthrGA== X-Received: by 2002:a17:902:b497:: with SMTP id y23-v6mr3854196plr.309.1526012621289; Thu, 10 May 2018 21:23:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 21:23:21 -0700 Message-Id: <20180511042324.5070-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511042324.5070-1-richard.henderson@linaro.org> References: <20180511042324.5070-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PULL 10/13] target/openrisc: Convert dec_comp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Stafford Horne Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Acked-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 120 +++++++++++++++++------------------ target/openrisc/insns.decode | 15 +++++ 2 files changed, 73 insertions(+), 62 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 548e0230b3..2c15b2713f 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1048,74 +1048,74 @@ static bool trans_l_macrc(DisasContext *dc, arg_l_m= acrc *a, uint32_t insn) return true; } =20 -static void dec_comp(DisasContext *dc, uint32_t insn) +static bool trans_l_sfeq(DisasContext *dc, arg_ab *a, TCGCond cond) { - uint32_t op0; - uint32_t ra, rb; + LOG_DIS("l.sfeq r%d, r%d\n", a->a, a->b); + tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + return true; +} =20 - op0 =3D extract32(insn, 21, 5); - ra =3D extract32(insn, 16, 5); - rb =3D extract32(insn, 11, 5); +static bool trans_l_sfne(DisasContext *dc, arg_ab *a, TCGCond cond) +{ + LOG_DIS("l.sfne r%d, r%d\n", a->a, a->b); + tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + return true; +} =20 - /* unsigned integers */ - tcg_gen_ext32u_tl(cpu_R[ra], cpu_R[ra]); - tcg_gen_ext32u_tl(cpu_R[rb], cpu_R[rb]); +static bool trans_l_sfgtu(DisasContext *dc, arg_ab *a, TCGCond cond) +{ + LOG_DIS("l.sfgtu r%d, r%d\n", a->a, a->b); + tcg_gen_setcond_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + return true; +} =20 - switch (op0) { - case 0x0: /* l.sfeq */ - LOG_DIS("l.sfeq r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[ra], cpu_R[rb]); - break; +static bool trans_l_sfgeu(DisasContext *dc, arg_ab *a, TCGCond cond) +{ + LOG_DIS("l.sfgeu r%d, r%d\n", a->a, a->b); + tcg_gen_setcond_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + return true; +} =20 - case 0x1: /* l.sfne */ - LOG_DIS("l.sfne r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_f, cpu_R[ra], cpu_R[rb]); - break; +static bool trans_l_sfltu(DisasContext *dc, arg_ab *a, TCGCond cond) +{ + LOG_DIS("l.sfltu r%d, r%d\n", a->a, a->b); + tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + return true; +} =20 - case 0x2: /* l.sfgtu */ - LOG_DIS("l.sfgtu r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[ra], cpu_R[rb]); - break; +static bool trans_l_sfleu(DisasContext *dc, arg_ab *a, TCGCond cond) +{ + LOG_DIS("l.sfleu r%d, r%d\n", a->a, a->b); + tcg_gen_setcond_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + return true; +} =20 - case 0x3: /* l.sfgeu */ - LOG_DIS("l.sfgeu r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[ra], cpu_R[rb]); - break; +static bool trans_l_sfgts(DisasContext *dc, arg_ab *a, TCGCond cond) +{ + LOG_DIS("l.sfgts r%d, r%d\n", a->a, a->b); + tcg_gen_setcond_tl(TCG_COND_GT, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + return true; +} =20 - case 0x4: /* l.sfltu */ - LOG_DIS("l.sfltu r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[ra], cpu_R[rb]); - break; +static bool trans_l_sfges(DisasContext *dc, arg_ab *a, TCGCond cond) +{ + LOG_DIS("l.sfges r%d, r%d\n", a->a, a->b); + tcg_gen_setcond_tl(TCG_COND_GE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + return true; +} =20 - case 0x5: /* l.sfleu */ - LOG_DIS("l.sfleu r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[ra], cpu_R[rb]); - break; +static bool trans_l_sflts(DisasContext *dc, arg_ab *a, TCGCond cond) +{ + LOG_DIS("l.sflts r%d, r%d\n", a->a, a->b); + tcg_gen_setcond_tl(TCG_COND_LT, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + return true; +} =20 - case 0xa: /* l.sfgts */ - LOG_DIS("l.sfgts r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_GT, cpu_sr_f, cpu_R[ra], cpu_R[rb]); - break; - - case 0xb: /* l.sfges */ - LOG_DIS("l.sfges r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_GE, cpu_sr_f, cpu_R[ra], cpu_R[rb]); - break; - - case 0xc: /* l.sflts */ - LOG_DIS("l.sflts r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_LT, cpu_sr_f, cpu_R[ra], cpu_R[rb]); - break; - - case 0xd: /* l.sfles */ - LOG_DIS("l.sfles r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_LE, cpu_sr_f, cpu_R[ra], cpu_R[rb]); - break; - - default: - gen_illegal_exception(dc); - break; - } +static bool trans_l_sfles(DisasContext *dc, arg_ab *a, TCGCond cond) +{ + LOG_DIS("l.sfles r%d, r%d\n", a->a, a->b); + tcg_gen_setcond_tl(TCG_COND_LE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + return true; } =20 static void dec_compi(DisasContext *dc, uint32_t insn) @@ -1478,10 +1478,6 @@ static void disas_openrisc_insn(DisasContext *dc, Op= enRISCCPU *cpu) dec_float(dc, insn); break; =20 - case 0x39: - dec_comp(dc, insn); - break; - default: gen_illegal_exception(dc); break; diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode index 84f71c13b3..29d28ff5be 100644 --- a/target/openrisc/insns.decode +++ b/target/openrisc/insns.decode @@ -139,3 +139,18 @@ l_slli 101110 d:5 a:5 -------- 00 l:6 l_srli 101110 d:5 a:5 -------- 01 l:6 l_srai 101110 d:5 a:5 -------- 10 l:6 l_rori 101110 d:5 a:5 -------- 11 l:6 + +#### +# Compare Instructions +#### + +l_sfeq 111001 00000 a:5 b:5 ----------- +l_sfne 111001 00001 a:5 b:5 ----------- +l_sfgtu 111001 00010 a:5 b:5 ----------- +l_sfgeu 111001 00011 a:5 b:5 ----------- +l_sfltu 111001 00100 a:5 b:5 ----------- +l_sfleu 111001 00101 a:5 b:5 ----------- +l_sfgts 111001 01010 a:5 b:5 ----------- +l_sfges 111001 01011 a:5 b:5 ----------- +l_sflts 111001 01100 a:5 b:5 ----------- +l_sfles 111001 01101 a:5 b:5 ----------- --=20 2.17.0