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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id y24-v6sm4216728pfn.23.2018.05.10.17.43.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 17:43:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tFLJR1pEbvSdgTdtmGzVTsnU5+kht680tv9A+aKFDJs=; b=g9rLRavyPOkkEqcT/ND5osw0NtJyWMhNyrOrKzz4FoyyntVVysZDwYh/I+zS5JRhl9 CJJDZdsK6HfGedEMlPhSSaq2MqdpseelbQJHobSaO+pzC7kOOxIAD6HMSn/y5+5dNpv7 ViuYdBShROOrFhZT4f5k0KC/hYTbsN+TO+l+k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tFLJR1pEbvSdgTdtmGzVTsnU5+kht680tv9A+aKFDJs=; b=kewOXEpQHoC27nwvyr/4OK/bdGFKKpgaoj0EC0lj5LOixexNBwWWFW7QcaUZhgC5Bh lBta9vKprpcn6UCcs6R6zD+TwDUrEoz2D9Z4/zzQgRxj40vq6gaimvu0DAXTjCyBRSs6 gwbbVgWKeNlj6ctm4ZOmQPZTn3bQEk1Eupe13Bar4N5Ad/X9HN+AERyPhqFtphURpEHl xTQdD7URwDXqe+99w4sLWnQplAtG+Y5vshbW+23SmO3NOC326jZR5SQWBvmZH595thZR ETDkhJD0B/AUDdWXq22VEsv1cNmgntlJ5ETe/lE4HIyz4ZHzBKqY1TotXsnIgcw+APC/ 3Q1Q== X-Gm-Message-State: ALKqPwcvHD5v0roNVoQ8LG3D4KtoGoQUZUb1lflxb+NY2tjv5ApxQ3pK qua+RBGOBk/+JQaDYpgX2p4RssvEhmc= X-Google-Smtp-Source: AB8JxZorbgna2HotKg63N2eguYkxYwhkcQlFOaPFK7Tp6OtCqcHMdXyyt9g5N+QaI8koVk0m96+nWg== X-Received: by 2002:a17:902:462:: with SMTP id 89-v6mr3278657ple.300.1525999436668; Thu, 10 May 2018 17:43:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 17:43:32 -0700 Message-Id: <20180511004345.26708-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511004345.26708-1-richard.henderson@linaro.org> References: <20180511004345.26708-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH 06/19] fpu/softfloat: Replace float_class_dnan with parts_default_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" With a canonical representation of NaNs, we can return the default nan directly rather than delay the expansion until the final format is known. Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 37 +++++++++++++++++++++++++++++++++++++ fpu/softfloat.c | 38 ++++++++++++-------------------------- 2 files changed, 49 insertions(+), 26 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 82d7a030e7..2ad524b11e 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -101,6 +101,43 @@ static bool parts_is_snan_frac(uint64_t frac, float_st= atus *status) #endif } =20 +/*------------------------------------------------------------------------= ---- +| The pattern for a default generated deconstructed floating-point NaN. +*-------------------------------------------------------------------------= ---*/ + +static FloatParts parts_default_nan(float_status *status) +{ + bool sign =3D 0; + uint64_t frac; + +#if defined(TARGET_SPARC) || defined(TARGET_M68K) + frac =3D (1ULL << DECOMPOSED_BINARY_POINT) - 1; +#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) = || \ + defined(TARGET_S390X) || defined(TARGET_RISCV) + frac =3D 1ULL << (DECOMPOSED_BINARY_POINT - 1); +#elif defined(TARGET_HPPA) + frac =3D 1ULL << (DECOMPOSED_BINARY_POINT - 2); +#else + if (status->snan_bit_is_one) { + frac =3D (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; + } else { +#if defined(TARGET_MIPS) + frac =3D 1ULL << (DECOMPOSED_BINARY_POINT - 1); +#else + frac =3D 1ULL << (DECOMPOSED_BINARY_POINT - 1); + sign =3D 1; +#endif + } +#endif + + return (FloatParts) { + .cls =3D float_class_qnan, + .sign =3D sign, + .exp =3D INT_MAX, + .frac =3D frac + }; +} + /*------------------------------------------------------------------------= ---- | The pattern for a default generated half-precision NaN. *-------------------------------------------------------------------------= ---*/ diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 6dfc992a7f..01036b158e 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -179,7 +179,6 @@ typedef enum __attribute__ ((__packed__)) { float_class_inf, float_class_qnan, /* all NaNs from here */ float_class_snan, - float_class_dnan, float_class_msnan, /* maybe silenced */ } FloatClass; =20 @@ -521,8 +520,6 @@ static float16 float16a_round_pack_canonical(const Floa= tFmt *params, FloatParts p, float_status *s) { switch (p.cls) { - case float_class_dnan: - return float16_default_nan(s); case float_class_msnan: return float16_maybe_silence_nan(float16_pack_raw(p), s); default: @@ -544,8 +541,6 @@ static FloatParts float32_unpack_canonical(float32 f, f= loat_status *s) static float32 float32_round_pack_canonical(FloatParts p, float_status *s) { switch (p.cls) { - case float_class_dnan: - return float32_default_nan(s); case float_class_msnan: return float32_maybe_silence_nan(float32_pack_raw(p), s); default: @@ -562,8 +557,6 @@ static FloatParts float64_unpack_canonical(float64 f, f= loat_status *s) static float64 float64_round_pack_canonical(FloatParts p, float_status *s) { switch (p.cls) { - case float_class_dnan: - return float64_default_nan(s); case float_class_msnan: return float64_maybe_silence_nan(float64_pack_raw(p), s); default: @@ -595,7 +588,7 @@ static FloatParts return_nan(FloatParts a, float_status= *s) /* fall through */ case float_class_qnan: if (s->default_nan_mode) { - a.cls =3D float_class_dnan; + return parts_default_nan(s); } break; =20 @@ -612,7 +605,7 @@ static FloatParts pick_nan(FloatParts a, FloatParts b, = float_status *s) } =20 if (s->default_nan_mode) { - a.cls =3D float_class_dnan; + return parts_default_nan(s); } else { if (pickNaN(is_qnan(a.cls), is_snan(a.cls), is_qnan(b.cls), is_snan(b.cls), @@ -633,7 +626,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatPa= rts b, FloatParts c, } =20 if (s->default_nan_mode) { - a.cls =3D float_class_dnan; + return parts_default_nan(s); } else { switch (pickNaNMulAdd(is_qnan(a.cls), is_snan(a.cls), is_qnan(b.cls), is_snan(b.cls), @@ -648,8 +641,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatPa= rts b, FloatParts c, a =3D c; break; case 3: - a.cls =3D float_class_dnan; - return a; + return parts_default_nan(s); default: g_assert_not_reached(); } @@ -703,7 +695,7 @@ static FloatParts addsub_floats(FloatParts a, FloatPart= s b, bool subtract, if (a.cls =3D=3D float_class_inf) { if (b.cls =3D=3D float_class_inf) { float_raise(float_flag_invalid, s); - a.cls =3D float_class_dnan; + return parts_default_nan(s); } return a; } @@ -849,7 +841,7 @@ static FloatParts mul_floats(FloatParts a, FloatParts b= , float_status *s) if ((a.cls =3D=3D float_class_inf && b.cls =3D=3D float_class_zero) || (a.cls =3D=3D float_class_zero && b.cls =3D=3D float_class_inf)) { s->float_exception_flags |=3D float_flag_invalid; - a.cls =3D float_class_dnan; + a =3D parts_default_nan(s); a.sign =3D sign; return a; } @@ -929,8 +921,7 @@ static FloatParts muladd_floats(FloatParts a, FloatPart= s b, FloatParts c, =20 if (inf_zero) { s->float_exception_flags |=3D float_flag_invalid; - a.cls =3D float_class_dnan; - return a; + return parts_default_nan(s); } =20 if (flags & float_muladd_negate_c) { @@ -954,12 +945,12 @@ static FloatParts muladd_floats(FloatParts a, FloatPa= rts b, FloatParts c, if (c.cls =3D=3D float_class_inf) { if (p_class =3D=3D float_class_inf && p_sign !=3D c.sign) { s->float_exception_flags |=3D float_flag_invalid; - a.cls =3D float_class_dnan; + return parts_default_nan(s); } else { a.cls =3D float_class_inf; a.sign =3D c.sign ^ sign_flip; + return a; } - return a; } =20 if (p_class =3D=3D float_class_inf) { @@ -1169,8 +1160,7 @@ static FloatParts div_floats(FloatParts a, FloatParts= b, float_status *s) && (a.cls =3D=3D float_class_inf || a.cls =3D=3D float_class_zero)) { s->float_exception_flags |=3D float_flag_invalid; - a.cls =3D float_class_dnan; - return a; + return parts_default_nan(s); } /* Inf / x or 0 / x */ if (a.cls =3D=3D float_class_inf || a.cls =3D=3D float_class_zero) { @@ -1253,8 +1243,7 @@ static FloatParts float_to_float(FloatParts a, } =20 if (s->default_nan_mode) { - a.cls =3D float_class_dnan; - return a; + return parts_default_nan(s); } =20 /* @@ -1470,7 +1459,6 @@ static int64_t round_to_int_and_pack(FloatParts in, i= nt rmode, switch (p.cls) { case float_class_snan: case float_class_qnan: - case float_class_dnan: case float_class_msnan: s->float_exception_flags =3D orig_flags | float_flag_invalid; return max; @@ -1562,7 +1550,6 @@ static uint64_t round_to_uint_and_pack(FloatParts in,= int rmode, uint64_t max, switch (p.cls) { case float_class_snan: case float_class_qnan: - case float_class_dnan: case float_class_msnan: s->float_exception_flags =3D orig_flags | float_flag_invalid; return max; @@ -2063,8 +2050,7 @@ static FloatParts sqrt_float(FloatParts a, float_stat= us *s, const FloatFmt *p) } if (a.sign) { s->float_exception_flags |=3D float_flag_invalid; - a.cls =3D float_class_dnan; - return a; + return parts_default_nan(s); } if (a.cls =3D=3D float_class_inf) { return a; /* sqrt(+inf) =3D +inf */ --=20 2.17.0