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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id y24-v6sm4216728pfn.23.2018.05.10.17.44.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 17:44:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MS+jabeFcvUCqsXLya/uB7mpbDAjQtdDouXTp4BblTw=; b=cNa6kqeUw781oBrG3DN3GEbNEo386oD2PAYucm8puPLnrFkcyj0F16xUF6eMFK5tzE fjhO+SPbT9iYJtrfKC/IFRga0heFFWW7w9SzHaOZXCzKoJ7zrctpEAKNQ5sX88zY17pT JGlZTx7htcZJ4gqCqTBqg/Kn4NA5oag5EWrEc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MS+jabeFcvUCqsXLya/uB7mpbDAjQtdDouXTp4BblTw=; b=f9b1uUwvzmocOBjj/NTGM1qGG+FYFzizWsmEVNUO5s9GV3VOXTBFfDajQx17E9mXWy en8n2Wd9tWEfwVLxTbO581Cbd8/lzIVfNxXqYY8ib4FVNOaEi4a5e4xni15ieVegCZqe I5HaeX9VMuDA++QMexfe6kjjRRlKX32jHNxeWeIfP+TzGw1WX7kAG3sAWrKiW8jdPa2K 9bF/YHjfvOsg7oc6o8o2aLmPxvxt/0zXDku32tZZcLjWU0oFJqQ79Pw1n/fznyPHS3UV uAkvRARjb/zTMNtGzqgkGAFzRLwoMp65T23FEEDjbgUEXFNNP3DJGZf1T3WK2eqjVNx/ 37cA== X-Gm-Message-State: ALKqPwcKaeROmAPPQteurF8V+HG0DVcywiubqRfu3+oFGcQbkrdOKoMj AEHFnZA6SfhRvtAF7GPNjzJ3TwW1iWI= X-Google-Smtp-Source: AB8JxZqu3mFKLNqCeJjh5IIp+310dlBFGZo0TdXnGR92GMySGmYDNqL621qH/mmAxOjoj7vGXazlCg== X-Received: by 2002:a65:6645:: with SMTP id z5-v6mr2746957pgv.43.1525999453950; Thu, 10 May 2018 17:44:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 17:43:45 -0700 Message-Id: <20180511004345.26708-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511004345.26708-1-richard.henderson@linaro.org> References: <20180511004345.26708-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH 19/19] fpu/softfloat: Pass FloatClass to pickNaNMulAdd X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For each operand, pass a single enumeration instead of a pair of booleans. Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 70 +++++++++++++++----------------------- fpu/softfloat.c | 11 +++--- 2 files changed, 31 insertions(+), 50 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 83e5bf83b9..637f1ea1be 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -583,15 +583,14 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | information. | Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN *-------------------------------------------------------------------------= ---*/ -#if defined(TARGET_ARM) -static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bI= sSNaN, - flag cIsQNaN, flag cIsSNaN, flag infzero, - float_status *status) +static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_= cls, + bool infzero, float_status *status) { +#if defined(TARGET_ARM) /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns * the default NaN */ - if (infzero && cIsQNaN) { + if (infzero && is_qnan(c_cls)) { float_raise(float_flag_invalid, status); return 3; } @@ -599,25 +598,20 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, = flag bIsQNaN, flag bIsSNaN, /* This looks different from the ARM ARM pseudocode, because the ARM A= RM * puts the operands to a fused mac operation (a*b)+c in the order c,a= ,b. */ - if (cIsSNaN) { + if (is_snan(c_cls)) { return 2; - } else if (aIsSNaN) { + } else if (is_snan(a_cls)) { return 0; - } else if (bIsSNaN) { + } else if (is_snan(b_cls)) { return 1; - } else if (cIsQNaN) { + } else if (is_qnan(c_cls)) { return 2; - } else if (aIsQNaN) { + } else if (is_qnan(a_cls)) { return 0; } else { return 1; } -} #elif defined(TARGET_MIPS) -static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bI= sSNaN, - flag cIsQNaN, flag cIsSNaN, flag infzero, - float_status *status) -{ /* For MIPS, the (inf,zero,qnan) case sets InvalidOp and returns * the default NaN */ @@ -628,41 +622,36 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, = flag bIsQNaN, flag bIsSNaN, =20 if (SNAN_BIT_IS_ONE(status)) { /* Prefer sNaN over qNaN, in the a, b, c order. */ - if (aIsSNaN) { + if (is_snan(a_cls)) { return 0; - } else if (bIsSNaN) { + } else if (is_snan(b_cls)) { return 1; - } else if (cIsSNaN) { + } else if (is_snan(c_cls)) { return 2; - } else if (aIsQNaN) { + } else if (is_qnan(a_cls)) { return 0; - } else if (bIsQNaN) { + } else if (is_qnan(b_cls)) { return 1; } else { return 2; } } else { /* Prefer sNaN over qNaN, in the c, a, b order. */ - if (cIsSNaN) { + if (is_snan(c_cls)) { return 2; - } else if (aIsSNaN) { + } else if (is_snan(a_cls)) { return 0; - } else if (bIsSNaN) { + } else if (is_snan(b_cls)) { return 1; - } else if (cIsQNaN) { + } else if (is_qnan(c_cls)) { return 2; - } else if (aIsQNaN) { + } else if (is_qnan(a_cls)) { return 0; } else { return 1; } } -} #elif defined(TARGET_PPC) -static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bI= sSNaN, - flag cIsQNaN, flag cIsSNaN, flag infzero, - float_status *status) -{ /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer * to return an input NaN if we have one (ie c) rather than generating * a default NaN @@ -675,31 +664,26 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, = flag bIsQNaN, flag bIsSNaN, /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB */ - if (aIsSNaN || aIsQNaN) { + if (is_nan(a_cls)) { return 0; - } else if (cIsSNaN || cIsQNaN) { + } else if (is_nan(c_cls)) { return 2; } else { return 1; } -} #else -/* A default implementation: prefer a to b to c. - * This is unlikely to actually match any real implementation. - */ -static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bI= sSNaN, - flag cIsQNaN, flag cIsSNaN, flag infzero, - float_status *status) -{ - if (aIsSNaN || aIsQNaN) { + /* A default implementation: prefer a to b to c. + * This is unlikely to actually match any real implementation. + */ + if (is_nan(a_cls)) { return 0; - } else if (bIsSNaN || bIsQNaN) { + } else if (is_nan(b_cls)) { return 1; } else { return 2; } -} #endif +} =20 /*------------------------------------------------------------------------= ---- | Takes two single-precision floating-point values `a' and `b', one of whi= ch diff --git a/fpu/softfloat.c b/fpu/softfloat.c index cd56beb277..4e957a5d6f 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -182,17 +182,17 @@ typedef enum __attribute__ ((__packed__)) { } FloatClass; =20 /* Simple helpers for checking if what NaN we have */ -static bool is_nan(FloatClass c) +static inline __attribute__((unused)) bool is_nan(FloatClass c) { return unlikely(c >=3D float_class_qnan); } =20 -static bool is_snan(FloatClass c) +static inline __attribute__((unused)) bool is_snan(FloatClass c) { return c =3D=3D float_class_snan; } =20 -static bool is_qnan(FloatClass c) +static inline __attribute__((unused)) bool is_qnan(FloatClass c) { return c =3D=3D float_class_qnan; } @@ -612,10 +612,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatP= arts b, FloatParts c, if (s->default_nan_mode) { return parts_default_nan(s); } else { - switch (pickNaNMulAdd(is_qnan(a.cls), is_snan(a.cls), - is_qnan(b.cls), is_snan(b.cls), - is_qnan(c.cls), is_snan(c.cls), - inf_zero, s)) { + switch (pickNaNMulAdd(a.cls, b.cls, c.cls, inf_zero, s)) { case 0: break; case 1: --=20 2.17.0