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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 10/21] target/xtensa: Use new min/max expanders X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson The generic expanders replace nearly identical code in the translator. Acked-by: Max Filippov Signed-off-by: Richard Henderson Message-id: 20180508151437.4232-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/xtensa/translate.c | 50 ++++++++++++++++++++++++++------------- 1 file changed, 33 insertions(+), 17 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 4f6d03059f..bad5cdb009 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1527,10 +1527,8 @@ static void translate_clamps(DisasContext *dc, const= uint32_t arg[], TCGv_i32 tmp1 =3D tcg_const_i32(-1u << arg[2]); TCGv_i32 tmp2 =3D tcg_const_i32((1 << arg[2]) - 1); =20 - tcg_gen_movcond_i32(TCG_COND_GT, tmp1, - cpu_R[arg[1]], tmp1, cpu_R[arg[1]], tmp1); - tcg_gen_movcond_i32(TCG_COND_LT, cpu_R[arg[0]], - tmp1, tmp2, tmp1, tmp2); + tcg_gen_smax_i32(tmp1, tmp1, cpu_R[arg[1]]); + tcg_gen_smin_i32(cpu_R[arg[0]], tmp1, tmp2); tcg_temp_free(tmp1); tcg_temp_free(tmp2); } @@ -1855,13 +1853,35 @@ static void translate_memw(DisasContext *dc, const = uint32_t arg[], tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); } =20 -static void translate_minmax(DisasContext *dc, const uint32_t arg[], - const uint32_t par[]) +static void translate_smin(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) { if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { - tcg_gen_movcond_i32(par[0], cpu_R[arg[0]], - cpu_R[arg[1]], cpu_R[arg[2]], - cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_smin_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + } +} + +static void translate_umin(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + tcg_gen_umin_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + } +} + +static void translate_smax(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + tcg_gen_smax_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + } +} + +static void translate_umax(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + tcg_gen_umax_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); } } =20 @@ -2984,23 +3004,19 @@ static const XtensaOpcodeOps core_ops[] =3D { .par =3D (const uint32_t[]){TCG_COND_NE}, }, { .name =3D "max", - .translate =3D translate_minmax, - .par =3D (const uint32_t[]){TCG_COND_GE}, + .translate =3D translate_smax, }, { .name =3D "maxu", - .translate =3D translate_minmax, - .par =3D (const uint32_t[]){TCG_COND_GEU}, + .translate =3D translate_umax, }, { .name =3D "memw", .translate =3D translate_memw, }, { .name =3D "min", - .translate =3D translate_minmax, - .par =3D (const uint32_t[]){TCG_COND_LT}, + .translate =3D translate_smin, }, { .name =3D "minu", - .translate =3D translate_minmax, - .par =3D (const uint32_t[]){TCG_COND_LTU}, + .translate =3D translate_umin, }, { .name =3D "mov", .translate =3D translate_mov, --=20 2.17.0