From nobody Wed Oct 29 22:58:37 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1525890253749238.1713979172314; Wed, 9 May 2018 11:24:13 -0700 (PDT) Received: from localhost ([::1]:58335 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fGTl6-00026I-Lz for importer@patchew.org; Wed, 09 May 2018 14:24:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48845) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fGTJh-0005f7-Tr for qemu-devel@nongnu.org; Wed, 09 May 2018 13:56:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fGTJZ-0006GW-VJ for qemu-devel@nongnu.org; Wed, 09 May 2018 13:55:53 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:42109) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fGTJZ-0006F9-LG for qemu-devel@nongnu.org; Wed, 09 May 2018 13:55:45 -0400 Received: by mail-pf0-x241.google.com with SMTP id p14so14621730pfh.9 for ; Wed, 09 May 2018 10:55:45 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id l90sm60332813pfb.149.2018.05.09.10.55.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 09 May 2018 10:55:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nsHlhsxYsaQlaLmojpAq1OySe60jzy62mwvSrLMWkZM=; b=QU1Of9QWYEXBZTLnVCQimvKwrBalm5Qnr5G/d6AhHkCIsFmHYtnkd2aJr1iCmU32Z0 xyE59LtJ9D84UKA2ZftGfYpOnAW78R4VVs2IM3jAFNsRh8sSf1YOvQUYUeCYUahpfTZV BTWm7aMk1DV3EChGdrcgpREjBqqqnhcTF5tWI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nsHlhsxYsaQlaLmojpAq1OySe60jzy62mwvSrLMWkZM=; b=h3mVbEqEzBtl9tFmsx8tmRF/LGdhgLLfFP/Pvzne/UzWpTG6SQKED8QAwNq27p0A4b t6ErkULzFrmodpWmcKBAS4mrFzC3cGEK1JNHfJ2/t8+eWXaw7ZiufxFmEeXGpDoJVWzi 1fzBsYDRODBHwegwW+Rt1XSkgbiGzdgBx7Cabhlzc+ITII8h8qGPLDNJP7CxKWKxCKuK 4YIVZV3VC+HpNqlRij+aWQSve/iByes1ahYUONgCrCmQuEicpgUDPFRIJvY+lC+0HQov qcUX0JzjgqD9K5/KZXipBkTKLsseLXIoIKfr6T448yJeIrjhTY0eQEzx3zMOsv/1Ndao zY3w== X-Gm-Message-State: ALQs6tCQmbxYZ3Nw1hJ+1JugM9Tv9hHtoAHcVlc8+cMgN49Sev27h83l txAWl5XU3hcanbFBitobk4VBFpRLkFc= X-Google-Smtp-Source: AB8JxZom+Q4Eo1nEKqVdqmLwZYiHDe9/RjMNSs01yGmjojErFG1Kvk/31d6ar4wqaOeL7u2y2CouYQ== X-Received: by 10.98.211.82 with SMTP id q79mr45256335pfg.45.1525888544202; Wed, 09 May 2018 10:55:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 May 2018 10:54:55 -0700 Message-Id: <20180509175458.15642-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180509175458.15642-1-richard.henderson@linaro.org> References: <20180509175458.15642-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PULL 25/28] target/openrisc: convert to TranslatorOps X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Sagar Karandikar , David Hildenbrand , Palmer Dabbelt , Mark Cave-Ayland , Max Filippov , Michael Clark , "Edgar E. Iglesias" , Guan Xuetao , Yongbok Kim , Alexander Graf , "Emilio G. Cota" , Richard Henderson , Artyom Tarasenko , Eduardo Habkost , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, Stafford Horne , David Gibson , Peter Crosthwaite , Bastian Koppelmann , Cornelia Huck , Michael Walle , qemu-ppc@nongnu.org, Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Notes: - Changed the num_insns test in insn_start to check for dc->base.num_insns > 1, since when tb_start is first called in a TB, base.num_insns is already set to 1. - Removed DISAS_NEXT from the switch in tb_stop; use DISAS_TOO_MANY instead. - Added an assert_not_reached on tb_stop for DISAS_NEXT and the default case. - Merged the two separate log_target_disas calls into the disas_log op. Reviewed-by: Richard Henderson Cc: Stafford Horne Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 165 +++++++++++++++++------------------- 1 file changed, 80 insertions(+), 85 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index b37414fb27..7cf29cd5b0 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1520,46 +1520,22 @@ static void disas_openrisc_insn(DisasContext *dc, O= penRISCCPU *cpu) } } =20 -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +static void openrisc_tr_init_disas_context(DisasContextBase *dcb, CPUState= *cs) { + DisasContext *dc =3D container_of(dcb, DisasContext, base); CPUOpenRISCState *env =3D cs->env_ptr; - OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); - struct DisasContext ctx, *dc =3D &ctx; - uint32_t pc_start; - uint32_t next_page_start; - int num_insns; - int max_insns; + int bound; =20 - pc_start =3D tb->pc; - - dc->base.tb =3D tb; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; - dc->base.pc_next =3D pc_start; - dc->base.is_jmp =3D DISAS_NEXT; - - dc->mem_idx =3D cpu_mmu_index(&cpu->env, false); + dc->mem_idx =3D cpu_mmu_index(env, false); dc->tb_flags =3D dc->base.tb->flags; dc->delayed_branch =3D (dc->tb_flags & TB_FLAGS_DFLAG) !=3D 0; + bound =3D -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; + dc->base.max_insns =3D MIN(dc->base.max_insns, bound); +} =20 - next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; - num_insns =3D 0; - max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; - - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } - - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(pc_start)) { - qemu_log_lock(); - qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); - } - - gen_tb_start(tb); +static void openrisc_tr_tb_start(DisasContextBase *db, CPUState *cs) +{ + DisasContext *dc =3D container_of(db, DisasContext, base); =20 /* Allow the TCG optimizer to see that R0 =3D=3D 0, when it's true, which is the common case. */ @@ -1568,50 +1544,55 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) } else { cpu_R[0] =3D cpu_R0; } +} =20 - do { - tcg_gen_insn_start(dc->base.pc_next, (dc->delayed_branch ? 1 : 0) - | (num_insns ? 2 : 0)); - num_insns++; +static void openrisc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); =20 - if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, BP_ANY))) { - tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); - gen_exception(dc, EXCP_DEBUG); - dc->base.is_jmp =3D DISAS_NORETURN; - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - dc->base.pc_next +=3D 4; - break; + tcg_gen_insn_start(dc->base.pc_next, (dc->delayed_branch ? 1 : 0) + | (dc->base.num_insns > 1 ? 2 : 0)); +} + +static bool openrisc_tr_breakpoint_check(DisasContextBase *dcbase, CPUStat= e *cs, + const CPUBreakpoint *bp) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); + gen_exception(dc, EXCP_DEBUG); + dc->base.is_jmp =3D DISAS_NORETURN; + /* The address covered by the breakpoint must be included in + [tb->pc, tb->pc + tb->size) in order to for it to be + properly cleared -- thus we increment the PC here so that + the logic setting tb->size below does the right thing. */ + dc->base.pc_next +=3D 4; + return true; +} + +static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState = *cs) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); + + disas_openrisc_insn(dc, cpu); + dc->base.pc_next +=3D 4; + + /* delay slot */ + if (dc->delayed_branch) { + dc->delayed_branch--; + if (!dc->delayed_branch) { + tcg_gen_mov_tl(cpu_pc, jmp_pc); + tcg_gen_discard_tl(jmp_pc); + dc->base.is_jmp =3D DISAS_UPDATE; + return; } - - if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { - gen_io_start(); - } - disas_openrisc_insn(dc, cpu); - dc->base.pc_next +=3D 4; - - /* delay slot */ - if (dc->delayed_branch) { - dc->delayed_branch--; - if (!dc->delayed_branch) { - tcg_gen_mov_tl(cpu_pc, jmp_pc); - tcg_gen_discard_tl(jmp_pc); - dc->base.is_jmp =3D DISAS_UPDATE; - break; - } - } - } while (!dc->base.is_jmp - && !tcg_op_buf_full() - && !dc->base.singlestep_enabled - && !singlestep - && (dc->base.pc_next < next_page_start) - && num_insns < max_insns); - - if (tb_cflags(tb) & CF_LAST_IO) { - gen_io_end(); } +} + +static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); =20 if ((dc->tb_flags & TB_FLAGS_DFLAG ? 1 : 0) !=3D (dc->delayed_branch != =3D 0)) { tcg_gen_movi_i32(cpu_dflag, dc->delayed_branch !=3D 0); @@ -1626,10 +1607,9 @@ void gen_intermediate_code(CPUState *cs, struct Tran= slationBlock *tb) gen_exception(dc, EXCP_DEBUG); } else { switch (dc->base.is_jmp) { - case DISAS_NEXT: + case DISAS_TOO_MANY: gen_goto_tb(dc, 0, dc->base.pc_next); break; - default: case DISAS_NORETURN: case DISAS_JUMP: case DISAS_TB_JUMP: @@ -1639,20 +1619,35 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) to find the next TB */ tcg_gen_exit_tb(0); break; + default: + g_assert_not_reached(); } } +} =20 - gen_tb_end(tb, num_insns); +static void openrisc_tr_disas_log(const DisasContextBase *dcbase, CPUState= *cs) +{ + DisasContext *s =3D container_of(dcbase, DisasContext, base); =20 - tb->size =3D dc->base.pc_next - pc_start; - tb->icount =3D num_insns; + qemu_log("IN: %s\n", lookup_symbol(s->base.pc_first)); + log_target_disas(cs, s->base.pc_first, s->base.tb->size); +} =20 - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(pc_start)) { - log_target_disas(cs, pc_start, tb->size); - qemu_log("\n"); - qemu_log_unlock(); - } +static const TranslatorOps openrisc_tr_ops =3D { + .init_disas_context =3D openrisc_tr_init_disas_context, + .tb_start =3D openrisc_tr_tb_start, + .insn_start =3D openrisc_tr_insn_start, + .breakpoint_check =3D openrisc_tr_breakpoint_check, + .translate_insn =3D openrisc_tr_translate_insn, + .tb_stop =3D openrisc_tr_tb_stop, + .disas_log =3D openrisc_tr_disas_log, +}; + +void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +{ + DisasContext ctx; + + translator_loop(&openrisc_tr_ops, &ctx.base, cs, tb); } =20 void openrisc_cpu_dump_state(CPUState *cs, FILE *f, --=20 2.17.0