From nobody Wed Oct 29 11:35:40 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1525815891236492.5185411853631; Tue, 8 May 2018 14:44:51 -0700 (PDT) Received: from localhost ([::1]:53432 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fGAPX-0000tx-Gx for importer@patchew.org; Tue, 08 May 2018 17:44:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35876) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fGAOG-00008K-LO for qemu-devel@nongnu.org; Tue, 08 May 2018 17:43:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fGAOD-0000rp-MR for qemu-devel@nongnu.org; Tue, 08 May 2018 17:43:20 -0400 Received: from chuckie.co.uk ([82.165.15.123]:52430 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fGAOD-0000od-C5 for qemu-devel@nongnu.org; Tue, 08 May 2018 17:43:17 -0400 Received: from host109-153-37-159.range109-153.btcentralplus.com ([109.153.37.159] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1fGAOI-0001Iv-Nd; Tue, 08 May 2018 22:43:24 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, atar4qemu@gmail.com Date: Tue, 8 May 2018 22:42:57 +0100 Message-Id: <20180508214257.23990-2-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180508214257.23990-1-mark.cave-ayland@ilande.co.uk> References: <20180508214257.23990-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 109.153.37.159 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [RFC PATCH 1/1] SPARC64: add icount support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch adds gen_io_start()/gen_io_end() to various instructions as requ= ired in order to boot my OpenBIOS test images on qemu-system-sparc64 with icount enabled. Signed-off-by: Mark Cave-Ayland --- target/sparc/translate.c | 97 ++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 97 insertions(+) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 5aa367a182..416197ae52 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -3401,11 +3401,17 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) r_const =3D tcg_const_i32(dc->mem_idx); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState, tick)); + if (dc->tb->cflags & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_tick_get_count(cpu_dst, cpu_env, r_tick= ptr, r_const); tcg_temp_free_ptr(r_tickptr); tcg_temp_free_i32(r_const); gen_store_gpr(dc, rd, cpu_dst); + if (dc->tb->cflags & CF_USE_ICOUNT) { + gen_io_end(); + } } break; case 0x5: /* V9 rdpc */ @@ -3448,11 +3454,17 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) r_const =3D tcg_const_i32(dc->mem_idx); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState, stick)); + if (dc->tb->cflags & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_tick_get_count(cpu_dst, cpu_env, r_tick= ptr, r_const); tcg_temp_free_ptr(r_tickptr); tcg_temp_free_i32(r_const); gen_store_gpr(dc, rd, cpu_dst); + if (dc->tb->cflags & CF_USE_ICOUNT) { + gen_io_end(); + } } break; case 0x19: /* System tick compare */ @@ -3577,10 +3589,16 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) r_const =3D tcg_const_i32(dc->mem_idx); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState, tick)); + if (dc->tb->cflags & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_tick_get_count(cpu_tmp0, cpu_env, r_tickptr, r_const); tcg_temp_free_ptr(r_tickptr); tcg_temp_free_i32(r_const); + if (dc->tb->cflags & CF_USE_ICOUNT) { + gen_io_end(); + } } break; case 5: // tba @@ -4386,9 +4404,20 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) r_tickptr =3D tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState,= tick)); + if (dc->tb->cflags & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_tick_set_limit(r_tickptr, cpu_tick_cmp= r); tcg_temp_free_ptr(r_tickptr); + if (dc->tb->cflags & CF_USE_ICOUNT) { + gen_io_end(); + /* End TB to handle timer interrup= t */ + save_state(dc); + gen_op_next_insn(); + tcg_gen_exit_tb(0); + dc->is_br =3D 1; + } } break; case 0x18: /* System tick */ @@ -4404,9 +4433,20 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) r_tickptr =3D tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState,= stick)); + if (dc->tb->cflags & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_tick_set_count(r_tickptr, cpu_tmp0); tcg_temp_free_ptr(r_tickptr); + if (dc->tb->cflags & CF_USE_ICOUNT) { + gen_io_end(); + /* End TB to handle timer interrup= t */ + save_state(dc); + gen_op_next_insn(); + tcg_gen_exit_tb(0); + dc->is_br =3D 1; + } } break; case 0x19: /* System tick compare */ @@ -4422,9 +4462,20 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) r_tickptr =3D tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState,= stick)); + if (dc->tb->cflags & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_tick_set_limit(r_tickptr, cpu_stick_cm= pr); tcg_temp_free_ptr(r_tickptr); + if (dc->tb->cflags & CF_USE_ICOUNT) { + gen_io_end(); + /* End TB to handle timer interrup= t */ + save_state(dc); + gen_op_next_insn(); + tcg_gen_exit_tb(0); + dc->is_br =3D 1; + } } break; =20 @@ -4532,9 +4583,20 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) r_tickptr =3D tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState,= tick)); + if (dc->tb->cflags & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_tick_set_count(r_tickptr, cpu_tmp0); tcg_temp_free_ptr(r_tickptr); + if (dc->tb->cflags & CF_USE_ICOUNT) { + gen_io_end(); + /* End TB to handle timer interrup= t */ + save_state(dc); + gen_op_next_insn(); + tcg_gen_exit_tb(0); + dc->is_br =3D 1; + } } break; case 5: // tba @@ -4542,7 +4604,13 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) break; case 6: // pstate save_state(dc); + if (dc->tb->cflags & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_wrpstate(cpu_env, cpu_tmp0); + if (dc->tb->cflags & CF_USE_ICOUNT) { + gen_io_end(); + } dc->npc =3D DYNAMIC_PC; break; case 7: // tl @@ -4552,7 +4620,13 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) dc->npc =3D DYNAMIC_PC; break; case 8: // pil + if (dc->tb->cflags & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_wrpil(cpu_env, cpu_tmp0); + if (dc->tb->cflags & CF_USE_ICOUNT) { + gen_io_end(); + } break; case 9: // cwp gen_helper_wrcwp(cpu_env, cpu_tmp0); @@ -4643,9 +4717,20 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) r_tickptr =3D tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState,= hstick)); + if (dc->tb->cflags & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_tick_set_limit(r_tickptr, cpu_hstick_c= mpr); tcg_temp_free_ptr(r_tickptr); + if (dc->tb->cflags & CF_USE_ICOUNT) { + gen_io_end(); + /* End TB to handle timer interrup= t */ + save_state(dc); + gen_op_next_insn(); + tcg_gen_exit_tb(0); + dc->is_br =3D 1; + } } break; case 6: // hver readonly @@ -5266,14 +5351,26 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) goto priv_insn; dc->npc =3D DYNAMIC_PC; dc->pc =3D DYNAMIC_PC; + if (dc->tb->cflags & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_done(cpu_env); + if (dc->tb->cflags & CF_USE_ICOUNT) { + gen_io_end(); + } goto jmp_insn; case 1: if (!supervisor(dc)) goto priv_insn; dc->npc =3D DYNAMIC_PC; dc->pc =3D DYNAMIC_PC; + if (dc->tb->cflags & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_retry(cpu_env); + if (dc->tb->cflags & CF_USE_ICOUNT) { + gen_io_end(); + } goto jmp_insn; default: goto illegal_insn; --=20 2.11.0