From nobody Thu Oct 30 15:21:18 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1525801975984149.72959916603554; Tue, 8 May 2018 10:52:55 -0700 (PDT) Received: from localhost ([::1]:52669 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fG6nH-0004ni-53 for importer@patchew.org; Tue, 08 May 2018 13:52:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44296) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fG6To-0000JD-M4 for qemu-devel@nongnu.org; Tue, 08 May 2018 13:32:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fG6Tj-0005bB-VF for qemu-devel@nongnu.org; Tue, 08 May 2018 13:32:48 -0400 Received: from mail-lf0-x244.google.com ([2a00:1450:4010:c07::244]:36898) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fG6Tj-0005ap-J4 for qemu-devel@nongnu.org; Tue, 08 May 2018 13:32:43 -0400 Received: by mail-lf0-x244.google.com with SMTP id r2-v6so10919609lff.4 for ; Tue, 08 May 2018 10:32:43 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id x130-v6sm5361749lff.33.2018.05.08.10.32.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 May 2018 10:32:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VC0Usz1uTosFLFE6uGufMyfmAiVgwqGZEy8d71XK7nQ=; b=LCzDmeMRyLEIPvfrMTynwL0RDuVkFD9wqUhYW3V/Mv8aRzPsh2jKGdOI4rNUS1xJxD cFVqgLQlfX9ww7B3qiLjTSXJ98rPKUfOh/7J0dsSioE/m21yK3Fpc/My6ZfO7iA3apSk GOCqb1g469aQki0Y335uTSKfqp6NwwqUpVd/IHRcf2Mfp2yq35Ej72JdkjQ/EKPUPGk4 kiJuUChjSIldWoXWsuqDqj+e8iSwp5grB2qNyv9S+k7A2HPhagBeLfQjeVZqsv+ZFsup FCOujA9YxlGZIxr00/XEhY/nQWiDgaNouZABD3OGGH+VtBkWZstITwm1j8rlY9Uy/CxZ U6Gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VC0Usz1uTosFLFE6uGufMyfmAiVgwqGZEy8d71XK7nQ=; b=AU2DiGipw/SMPd6qK8JFGS49Kdv+MqHXO7G4pP8EGZwL6UOHojGUQRm1MJLTYV1eXD JokHT9zR7HKvREPzb7H3VVYJ9+cbWRVKVEXMhkFutt+LUF82YeRwrRMgypeFjkH4ql7E dUjv4PmCJqxDnMPxmFyMxmibh5vEeY7DBdR2DsgMfYeullij0spcnLTCHlmWpn+OnsFM 6dbExLX+6pRTl2RNRyC5GLwT/1n6FVmTY6Ipq5bEaZVEFRazIMyeNNyEcA9IMaGezG8s 9n5gdD/cDr+WUklEcVxLrxikWVf3HKJxuoz8aKajP7Wa6QDb5wUqFYgRwAxKUqibJg4H YmhQ== X-Gm-Message-State: ALQs6tBGTnZAbBny8/KW+uGJAQ70enCIifd+LPf0O+IvhQbGgAugedBH BKFtYiTbncpBUFicPg9MR4F8mA== X-Google-Smtp-Source: AB8JxZo9ziKWqzgOvwl6b+qiLAmBDlhrEB2r8qv14s8JqM8oQCa581VyoMnwl6PkiBbIMjJGJMM6Ag== X-Received: by 2002:a19:cfc8:: with SMTP id f191-v6mr25591444lfg.92.1525800761988; Tue, 08 May 2018 10:32:41 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 8 May 2018 19:31:47 +0200 Message-Id: <20180508173152.29327-32-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180508173152.29327-1-edgar.iglesias@gmail.com> References: <20180508173152.29327-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::244 Subject: [Qemu-devel] [PATCH v2 31/36] target-microblaze: mmu: Cleanup debug log messages X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, frederic.konrad@adacore.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Cleanup debug log messages: * Avoid long 80+ character lines. * Remove D() macro and use qemu_log_mask. * Remove logs that are not very useful Suggested-by: Alistair Francis Signed-off-by: Edgar E. Iglesias Reviewed-by: Richard Henderson --- target/microblaze/mmu.c | 39 +++++++++++++++++++-------------------- 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 9ecffb2c9c..f4ceaea520 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -22,8 +22,6 @@ #include "cpu.h" #include "exec/exec-all.h" =20 -#define D(x) - static unsigned int tlb_decode_size(unsigned int f) { static const unsigned int sizes[] =3D { @@ -90,25 +88,20 @@ unsigned int mmu_translate(struct microblaze_mmu *mmu, =20 /* Lookup and decode. */ t =3D mmu->rams[RAM_TAG][i]; - D(qemu_log("TLB %d valid=3D%" PRId64 "\n", i, t & TLB_VALID)); if (t & TLB_VALID) { tlb_size =3D tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7); if (tlb_size < TARGET_PAGE_SIZE) { - qemu_log("%d pages not supported\n", tlb_size); + qemu_log_mask(LOG_UNIMP, "%d pages not supported\n", tlb_s= ize); abort(); } =20 mask =3D ~((uint64_t)tlb_size - 1); tlb_tag =3D t & TLB_EPN_MASK; if ((vaddr & mask) !=3D (tlb_tag & mask)) { - D(qemu_log("TLB %d vaddr=3D%" PRIx64 " !=3D tag=3D%" PRIx6= 4 "\n", - i, vaddr & mask, tlb_tag & mask)); continue; } if (mmu->tids[i] && ((mmu->regs[MMU_R_PID] & 0xff) !=3D mmu->tids[i])) { - D(qemu_log("TLB %d pid=3D%x !=3D tid=3D%x\n", - i, mmu->regs[MMU_R_PID], mmu->tids[i])); continue; } =20 @@ -123,7 +116,8 @@ unsigned int mmu_translate(struct microblaze_mmu *mmu, t0 &=3D 0x3; =20 if (tlb_zsel > mmu->c_mmu_zones) { - qemu_log_mask(LOG_GUEST_ERROR, "tlb zone select out of ran= ge! %d\n", tlb_zsel); + qemu_log_mask(LOG_GUEST_ERROR, + "tlb zone select out of range! %d\n", tlb_zs= el); t0 =3D 1; /* Ignore. */ } =20 @@ -174,8 +168,9 @@ unsigned int mmu_translate(struct microblaze_mmu *mmu, } } done: - D(qemu_log("MMU vaddr=3D%" PRIx64 " rw=3D%d tlb_wr=3D%d tlb_ex=3D%d hi= t=3D%d\n", - vaddr, rw, tlb_wr, tlb_ex, hit)); + qemu_log_mask(CPU_LOG_MMU, + "MMU vaddr=3D%" PRIx64 " rw=3D%d tlb_wr=3D%d tlb_ex=3D%d= hit=3D%d\n", + vaddr, rw, tlb_wr, tlb_ex, hit); return hit; } =20 @@ -199,7 +194,8 @@ uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t r= n) case MMU_R_TLBLO: case MMU_R_TLBHI: if (!(env->mmu.c_mmu_tlb_access & 1)) { - qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg = %d\n", rn); + qemu_log_mask(LOG_GUEST_ERROR, + "Invalid access to MMU reg %d\n", rn); return 0; } =20 @@ -211,7 +207,8 @@ uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t r= n) case MMU_R_PID: case MMU_R_ZPR: if (!(env->mmu.c_mmu_tlb_access & 1)) { - qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg = %d\n", rn); + qemu_log_mask(LOG_GUEST_ERROR, + "Invalid access to MMU reg %d\n", rn); return 0; } r =3D env->mmu.regs[rn]; @@ -226,7 +223,7 @@ uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t r= n) qemu_log_mask(LOG_GUEST_ERROR, "Invalid MMU register %d.\n", r= n); break; } - D(qemu_log("%s rn=3D%d=3D%x\n", __func__, rn, r)); + qemu_log_mask(CPU_LOG_MMU, "%s rn=3D%d=3D%x\n", __func__, rn, r); return r; } =20 @@ -235,7 +232,8 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, = uint32_t v) MicroBlazeCPU *cpu =3D mb_env_get_cpu(env); uint64_t tmp64; unsigned int i; - D(qemu_log("%s rn=3D%d=3D%x old=3D%x\n", __func__, rn, v, env->mmu.reg= s[rn])); + qemu_log_mask(CPU_LOG_MMU, + "%s rn=3D%d=3D%x old=3D%x\n", __func__, rn, v, env->mmu.= regs[rn]); =20 if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) { qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n"); @@ -261,12 +259,11 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn= , uint32_t v) } tmp64 =3D env->mmu.rams[rn & 1][i]; env->mmu.rams[rn & 1][i] =3D deposit64(tmp64, ext * 32, 32, v); - - D(qemu_log("%s ram[%d][%d]=3D%x\n", __func__, rn & 1, i, v)); break; case MMU_R_ZPR: if (env->mmu.c_mmu_tlb_access <=3D 1) { - qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg = %d\n", rn); + qemu_log_mask(LOG_GUEST_ERROR, + "Invalid access to MMU reg %d\n", rn); return; } =20 @@ -279,7 +276,8 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, = uint32_t v) break; case MMU_R_PID: if (env->mmu.c_mmu_tlb_access <=3D 1) { - qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg = %d\n", rn); + qemu_log_mask(LOG_GUEST_ERROR, + "Invalid access to MMU reg %d\n", rn); return; } =20 @@ -298,7 +296,8 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, = uint32_t v) int hit; =20 if (env->mmu.c_mmu_tlb_access <=3D 1) { - qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg = %d\n", rn); + qemu_log_mask(LOG_GUEST_ERROR, + "Invalid access to MMU reg %d\n", rn); return; } =20 --=20 2.14.1