From nobody Thu Oct 30 15:21:18 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1525802248767414.3683633152051; Tue, 8 May 2018 10:57:28 -0700 (PDT) Received: from localhost ([::1]:52702 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fG6rf-0000ij-VY for importer@patchew.org; Tue, 08 May 2018 13:57:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44228) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fG6Td-00009h-8c for qemu-devel@nongnu.org; Tue, 08 May 2018 13:32:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fG6Tc-0005YK-7R for qemu-devel@nongnu.org; Tue, 08 May 2018 13:32:37 -0400 Received: from mail-lf0-x241.google.com ([2a00:1450:4010:c07::241]:39206) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fG6Tb-0005Y3-W5 for qemu-devel@nongnu.org; Tue, 08 May 2018 13:32:36 -0400 Received: by mail-lf0-x241.google.com with SMTP id j193-v6so47054095lfg.6 for ; Tue, 08 May 2018 10:32:35 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id q18-v6sm4520558lfi.97.2018.05.08.10.32.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 May 2018 10:32:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1JH4AXK1bKD3WNWicaFFd/WvhlIGwcRDUsr7FwuCfVY=; b=bGpMmbUTBxGriyVeyjsPs41HXzxxECXLOraeXN6DlfjRJlK9Sbuo5iKvwm/4jZNDH3 Wm6rN/5BW/Z3R9C48RnOq+n/Gx5xA/2NQyw3IY7d7383YoFtouk1h2pNvpS5KqNbzYUP s6YxDGrpCUP0WKWlToGJtOY/w9BmqRzi1mqMdfdZ1d7z6yM3lnWthbRVSMjY8zKkXn48 ecEvY2OEVc/wFeAIp6XIgKaYcAW2avOe8/iw/s3kiUbH3RYu5nevQEn/rZmpm3Xf7kwr eTYlRs0qaKlD5RZ/Gys5hoJS4WvW/PJ+YVMfF0ENtGXDfBFNdIxuVHgjIfwLqS/mZjB6 Cz6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1JH4AXK1bKD3WNWicaFFd/WvhlIGwcRDUsr7FwuCfVY=; b=IW5eGZ1jpOhNZUg5Ds2qxzf48CQokp+ulhzja9BGxBpQQJ0NHD3oxl5qAQEkVThd7D YCm1/QlIp3R2bg7KgMOHheHo7frRDDqf2ssy/4naFdeHQVOeTpAED+fhRH07/nXhO5zy W0ni1r+BDTpyiU8bhzOGTtsncATm3JGBCQYYurIHWisJkZxNLdVDK50kqrr70DKaUvXC H+8i4k+ILUG3FhtguwFnhlaOXH7RB7NeoB823FDHsWpGhl/3VkFK1b6E4zSCirQP7TSy kpgW+3ucw7KHbw4ZBaFzOl0alXOUyh4aEJ3gTrLqrym8TbRIj62bT6a2zauRPb907EBC Kpkg== X-Gm-Message-State: ALQs6tAGeHOjod3s7gVNrvh1tmDT1zX6qCJmEEv/RrsZR5QVkD6J7rKs W/JO4EeWJ7TbSr3wFGKkJ58XLA== X-Google-Smtp-Source: AB8JxZpzVJyjy6pjktaX2wnZQfahZpPLqw8rcgpRfktgZ4vGveZI3KSBIhndfOmir+ZuhYKG2XsQzA== X-Received: by 2002:a19:964b:: with SMTP id y72-v6mr19925849lfd.96.1525800754451; Tue, 08 May 2018 10:32:34 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 8 May 2018 19:31:42 +0200 Message-Id: <20180508173152.29327-27-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180508173152.29327-1-edgar.iglesias@gmail.com> References: <20180508173152.29327-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::241 Subject: [Qemu-devel] [PATCH v2 26/36] target-microblaze: mmu: Prepare for 64-bit addresses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, frederic.konrad@adacore.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Prepare for 64-bit addresses. This makes no functional difference as the upper parts of the 64-bit addresses are not yet reachable. Signed-off-by: Edgar E. Iglesias Reviewed-by: Richard Henderson --- target/microblaze/mmu.c | 14 +++++++------- target/microblaze/mmu.h | 6 +++--- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 231803ceea..a379968618 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -81,16 +81,16 @@ unsigned int mmu_translate(struct microblaze_mmu *mmu, { unsigned int i, hit =3D 0; unsigned int tlb_ex =3D 0, tlb_wr =3D 0, tlb_zsel; - unsigned int tlb_size; - uint32_t tlb_tag, tlb_rpn, mask, t0; + uint64_t tlb_tag, tlb_rpn, mask; + uint32_t tlb_size, t0; =20 lu->err =3D ERR_MISS; for (i =3D 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) { - uint32_t t, d; + uint64_t t, d; =20 /* Lookup and decode. */ t =3D mmu->rams[RAM_TAG][i]; - D(qemu_log("TLB %d valid=3D%d\n", i, t & TLB_VALID)); + D(qemu_log("TLB %d valid=3D%" PRId64 "\n", i, t & TLB_VALID)); if (t & TLB_VALID) { tlb_size =3D tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7); if (tlb_size < TARGET_PAGE_SIZE) { @@ -98,10 +98,10 @@ unsigned int mmu_translate(struct microblaze_mmu *mmu, abort(); } =20 - mask =3D ~(tlb_size - 1); + mask =3D ~((uint64_t)tlb_size - 1); tlb_tag =3D t & TLB_EPN_MASK; if ((vaddr & mask) !=3D (tlb_tag & mask)) { - D(qemu_log("TLB %d vaddr=3D%x !=3D tag=3D%x\n", + D(qemu_log("TLB %d vaddr=3D%" PRIx64 " !=3D tag=3D%" PRIx6= 4 "\n", i, vaddr & mask, tlb_tag & mask)); continue; } @@ -173,7 +173,7 @@ unsigned int mmu_translate(struct microblaze_mmu *mmu, } } done: - D(qemu_log("MMU vaddr=3D%x rw=3D%d tlb_wr=3D%d tlb_ex=3D%d hit=3D%d\n", + D(qemu_log("MMU vaddr=3D%" PRIx64 " rw=3D%d tlb_wr=3D%d tlb_ex=3D%d hi= t=3D%d\n", vaddr, rw, tlb_wr, tlb_ex, hit)); return hit; } diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h index 624becfded..1714caf82e 100644 --- a/target/microblaze/mmu.h +++ b/target/microblaze/mmu.h @@ -28,7 +28,7 @@ #define RAM_TAG 0 =20 /* Tag portion */ -#define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */ +#define TLB_EPN_MASK MAKE_64BIT_MASK(10, 64 - 10) #define TLB_PAGESZ_MASK 0x00000380 #define TLB_PAGESZ(x) (((x) & 0x7) << 7) #define PAGESZ_1K 0 @@ -42,7 +42,7 @@ #define TLB_VALID 0x00000040 /* Entry is valid */ =20 /* Data portion */ -#define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */ +#define TLB_RPN_MASK MAKE_64BIT_MASK(10, 64 - 10) #define TLB_PERM_MASK 0x00000300 #define TLB_EX 0x00000200 /* Instruction execution allowed = */ #define TLB_WR 0x00000100 /* Writes permitted */ @@ -63,7 +63,7 @@ struct microblaze_mmu { /* Data and tag brams. */ - uint32_t rams[2][TLB_ENTRIES]; + uint64_t rams[2][TLB_ENTRIES]; /* We keep a separate ram for the tids to avoid the 48 bit tag width. = */ uint8_t tids[TLB_ENTRIES]; /* Control flops. */ --=20 2.14.1