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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id r8-v6sm16987413pgn.2.2018.05.04.11.30.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 04 May 2018 11:30:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ThPvhn6D+UVVPyfam//ZDBRKSjR9Wis18Q00SIwCn4E=; b=X9KfoqKqpbum7f63Qqa7Y6q2RS+TNVn2kvWZljpyJvM+1KDguuQbSwdZ/hpL2rymMD hVkq3afSZKgWMuTCX1MObOInefrq0F8QZgw0dKqiKavmQdXZ17ac+8OBKC0DYS+sBvsP a8NVHveBbovW5hyLqBYVif7HxOz++r24B8QzE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ThPvhn6D+UVVPyfam//ZDBRKSjR9Wis18Q00SIwCn4E=; b=krSAQ7UuMTunOMmwhbmXhb1BxrpV2kO3DHNUM/4uGIV9xuGlJptG7yADhGxTO/y/L1 gq6bajji/DlF8tQGDLtC28w4NkA6oi7OOUwI4Z7OjeW3lvgtfESuk/7Dlb4S0s95aR4Y tf6HWZPcHZy0rlg8EiRpwiEz2Y7kFW1ySVz3xLA0zS8fYrWwraN4TX/KElEAnVVOZYQQ UE+1DD6jFvW9bBv+MTdiIfmC8Z9iIRVJjBWQP+G3imi6NSqoMsZmW55Cr3xbcWnRo5Da ajm9j5ETIlTpwXK8zSEugHWLKTtNsSw2VyAKrRtXPFFFOpyVhE2SAiK9DmDdG/ieZZnF FfMQ== X-Gm-Message-State: ALQs6tAjg/5ZnIqdVc0zut9UXVeAJc7Zn0Y6Gq2cJkmZz6hy7LOnlgyI 4YqK8MsTVnHNqD+dPRuqsVGlbUDVTWc= X-Google-Smtp-Source: AB8JxZoqUwGSi4Pb1LxPZbrJ34bbY0tp+TUwSJG1SRXntplPvzjg0QGS7luSDI+DmY4coRVa845SOw== X-Received: by 2002:a17:902:a60d:: with SMTP id u13-v6mr10205339plq.40.1525458634738; Fri, 04 May 2018 11:30:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 4 May 2018 11:30:19 -0700 Message-Id: <20180504183021.19318-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180504183021.19318-1-richard.henderson@linaro.org> References: <20180504183021.19318-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v2 08/10] target/arm: Fill in disas_ldst_atomic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This implements all of the v8.1-Atomics instructions except for compare-and-swap, which is decoded elsewhere. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 38 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 6acad791e6..5af6028089 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -84,6 +84,7 @@ typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64); typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr); typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); +typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, TCGMemO= p); =20 /* Note that the gvec expanders operate on offsets + sizes. */ typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t); @@ -2772,6 +2773,8 @@ static void disas_ldst_atomic(DisasContext *s, uint32= _t insn, int rn =3D extract32(insn, 5, 5); int o3_opc =3D extract32(insn, 12, 4); int feature =3D ARM_FEATURE_V8_ATOMICS; + TCGv_i64 tcg_rn, tcg_rs; + AtomicThreeOpFn *fn; =20 if (is_vector) { unallocated_encoding(s); @@ -2779,14 +2782,32 @@ static void disas_ldst_atomic(DisasContext *s, uint= 32_t insn, } switch (o3_opc) { case 000: /* LDADD */ + fn =3D tcg_gen_atomic_fetch_add_i64; + break; case 001: /* LDCLR */ + fn =3D tcg_gen_atomic_fetch_and_i64; + break; case 002: /* LDEOR */ + fn =3D tcg_gen_atomic_fetch_xor_i64; + break; case 003: /* LDSET */ + fn =3D tcg_gen_atomic_fetch_or_i64; + break; case 004: /* LDSMAX */ + fn =3D tcg_gen_atomic_fetch_smax_i64; + break; case 005: /* LDSMIN */ + fn =3D tcg_gen_atomic_fetch_smin_i64; + break; case 006: /* LDUMAX */ + fn =3D tcg_gen_atomic_fetch_umax_i64; + break; case 007: /* LDUMIN */ + fn =3D tcg_gen_atomic_fetch_umin_i64; + break; case 010: /* SWP */ + fn =3D tcg_gen_atomic_xchg_i64; + break; default: unallocated_encoding(s); return; @@ -2796,8 +2817,21 @@ static void disas_ldst_atomic(DisasContext *s, uint3= 2_t insn, return; } =20 - (void)rs; - (void)rn; + if (rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + tcg_rn =3D cpu_reg_sp(s, rn); + tcg_rs =3D read_cpu_reg(s, rs, false); + + if (o3_opc =3D=3D 1) { /* LDCLR */ + tcg_gen_not_i64(tcg_rs, tcg_rs); + } + + /* The tcg atomic primitives are all full barriers. Therefore we + * can ignore the Acquire and Release bits of this instruction. + */ + fn(cpu_reg(s, rt), tcg_rn, tcg_rs, get_mem_index(s), + s->be_data | size | MO_ALIGN); } =20 /* Load/store register (all forms) */ --=20 2.14.3