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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id r8-v6sm16987413pgn.2.2018.05.04.11.30.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 04 May 2018 11:30:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8liVC1EvOhXEjQqPTbUiUiso0NQryYqSK+kZmW2XosI=; b=auTPZvxOL43cPk1dHmLGtoavykFo4zabs/busrfaqJA9CjiIIPvXbcsnQ5zh9s6p9o 3zkNeGOpxsLrzsejsckcj4frw62YLwWTgQmbcdDD9orA4UN0RAMoHJpt0jFooI8NX2oq JjxHRKbojPIlaiLTIokkks9XXUlUxggcQ/wbA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8liVC1EvOhXEjQqPTbUiUiso0NQryYqSK+kZmW2XosI=; b=IRTH6mExWD3voyWgG4u2ALloU0x4YehfcWvTfr5bgcBORvpvg2M4z5ZMxHnR96hiBJ jF5J+oTbDUNRngx+3aSL1CpMowEolF55uhAjoAquH5m1MZWjLXV9GZ9VOfIsXooOKBBT l1qIuM+RjJOTQdZSAVArATGHSyGZVPTSsBeQvK6VqXHUu58ZCRIbw9os2w43z23stKdO rbeP2JjPobXkRi61oA9RE1vC9nht+LN0a59+4NB3d0Z/mfmpIZ5jKinsSuYudOFx2aP8 rb1OW530YVGdG7qgsDToQSwtfgvokVYmwjTd3Yt5r+w5s7VGAuy1JoMdxy/pV435QdHt SWUQ== X-Gm-Message-State: ALQs6tDJwTBpPCU2qpL0nilObqUBc/14fbpc6hiBHAfVP/a5GkDGF7wW +54rekzKvoVqJwcf+r6pok2qUClW24A= X-Google-Smtp-Source: AB8JxZqFXCHyY7kBODFTQaf1VnA4VADMwzjkz3k3v4lwKd5iUiQvKSd4Q6Z8jkLl04rEF+6pDl3G2w== X-Received: by 2002:a65:5d0f:: with SMTP id e15-v6mr23701692pgr.119.1525458626756; Fri, 04 May 2018 11:30:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 4 May 2018 11:30:13 -0700 Message-Id: <20180504183021.19318-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180504183021.19318-1-richard.henderson@linaro.org> References: <20180504183021.19318-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v2 02/10] target/arm: Use new min/max expanders X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The generic expanders replace nearly identical code in the translator. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 46 ++++++++++++++----------------------------= ---- 1 file changed, 14 insertions(+), 32 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index bff4e13bf6..d916fea3a3 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -6021,15 +6021,18 @@ static void disas_simd_across_lanes(DisasContext *s= , uint32_t insn) tcg_gen_add_i64(tcg_res, tcg_res, tcg_elt); break; case 0x0a: /* SMAXV / UMAXV */ - tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE, - tcg_res, - tcg_res, tcg_elt, tcg_res, tcg_elt); + if (is_u) { + tcg_gen_umax_i64(tcg_res, tcg_res, tcg_elt); + } else { + tcg_gen_smax_i64(tcg_res, tcg_res, tcg_elt); + } break; case 0x1a: /* SMINV / UMINV */ - tcg_gen_movcond_i64(is_u ? TCG_COND_LEU : TCG_COND_LE, - tcg_res, - tcg_res, tcg_elt, tcg_res, tcg_elt); - break; + if (is_u) { + tcg_gen_umin_i64(tcg_res, tcg_res, tcg_elt); + } else { + tcg_gen_smin_i64(tcg_res, tcg_res, tcg_elt); + } break; default: g_assert_not_reached(); @@ -9931,27 +9934,6 @@ static void disas_simd_3same_logic(DisasContext *s, = uint32_t insn) } } =20 -/* Helper functions for 32 bit comparisons */ -static void gen_max_s32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2) -{ - tcg_gen_movcond_i32(TCG_COND_GE, res, op1, op2, op1, op2); -} - -static void gen_max_u32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2) -{ - tcg_gen_movcond_i32(TCG_COND_GEU, res, op1, op2, op1, op2); -} - -static void gen_min_s32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2) -{ - tcg_gen_movcond_i32(TCG_COND_LE, res, op1, op2, op1, op2); -} - -static void gen_min_u32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2) -{ - tcg_gen_movcond_i32(TCG_COND_LEU, res, op1, op2, op1, op2); -} - /* Pairwise op subgroup of C3.6.16. * * This is called directly or via the handle_3same_float for float pairwise @@ -10051,7 +10033,7 @@ static void handle_simd_3same_pair(DisasContext *s,= int is_q, int u, int opcode, static NeonGenTwoOpFn * const fns[3][2] =3D { { gen_helper_neon_pmax_s8, gen_helper_neon_pmax_u8 }, { gen_helper_neon_pmax_s16, gen_helper_neon_pmax_u16 }, - { gen_max_s32, gen_max_u32 }, + { tcg_gen_smax_i32, tcg_gen_umax_i32 }, }; genfn =3D fns[size][u]; break; @@ -10061,7 +10043,7 @@ static void handle_simd_3same_pair(DisasContext *s,= int is_q, int u, int opcode, static NeonGenTwoOpFn * const fns[3][2] =3D { { gen_helper_neon_pmin_s8, gen_helper_neon_pmin_u8 }, { gen_helper_neon_pmin_s16, gen_helper_neon_pmin_u16 }, - { gen_min_s32, gen_min_u32 }, + { tcg_gen_smin_i32, tcg_gen_umin_i32 }, }; genfn =3D fns[size][u]; break; @@ -10516,7 +10498,7 @@ static void disas_simd_3same_int(DisasContext *s, u= int32_t insn) static NeonGenTwoOpFn * const fns[3][2] =3D { { gen_helper_neon_max_s8, gen_helper_neon_max_u8 }, { gen_helper_neon_max_s16, gen_helper_neon_max_u16 }, - { gen_max_s32, gen_max_u32 }, + { tcg_gen_smax_i32, tcg_gen_umax_i32 }, }; genfn =3D fns[size][u]; break; @@ -10527,7 +10509,7 @@ static void disas_simd_3same_int(DisasContext *s, u= int32_t insn) static NeonGenTwoOpFn * const fns[3][2] =3D { { gen_helper_neon_min_s8, gen_helper_neon_min_u8 }, { gen_helper_neon_min_s16, gen_helper_neon_min_u16 }, - { gen_min_s32, gen_min_u32 }, + { tcg_gen_smin_i32, tcg_gen_umin_i32 }, }; genfn =3D fns[size][u]; break; --=20 2.14.3