From nobody Thu Dec 18 17:55:28 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1525454469247595.7280170329615; Fri, 4 May 2018 10:21:09 -0700 (PDT) Received: from localhost ([::1]:35633 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fEeOK-0000v3-BY for importer@patchew.org; Fri, 04 May 2018 13:21:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51672) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fEeJ9-0005bu-Pk for qemu-devel@nongnu.org; Fri, 04 May 2018 13:15:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fEeJ8-0000XT-9u for qemu-devel@nongnu.org; Fri, 04 May 2018 13:15:47 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:41480) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fEeJ8-0000Tm-3C for qemu-devel@nongnu.org; Fri, 04 May 2018 13:15:46 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fEeJ6-00031C-UM for qemu-devel@nongnu.org; Fri, 04 May 2018 18:15:44 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 4 May 2018 18:15:21 +0100 Message-Id: <20180504171540.25813-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180504171540.25813-1-peter.maydell@linaro.org> References: <20180504171540.25813-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 05/24] hw/net/smc91c111: Convert away from old_mmio X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Convert the smc91c111 device away from using the old_mmio field of MemoryRegionOps. This device is used by several Arm board models. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20180427173611.10281-3-peter.maydell@linaro.org --- hw/net/smc91c111.c | 54 +++++++++++++++++++++------------------------- 1 file changed, 25 insertions(+), 29 deletions(-) diff --git a/hw/net/smc91c111.c b/hw/net/smc91c111.c index 3b16dcf5a1..c8cc5379b7 100644 --- a/hw/net/smc91c111.c +++ b/hw/net/smc91c111.c @@ -625,37 +625,33 @@ static uint32_t smc91c111_readb(void *opaque, hwaddr = offset) return 0; } =20 -static void smc91c111_writew(void *opaque, hwaddr offset, - uint32_t value) +static uint64_t smc91c111_readfn(void *opaque, hwaddr addr, unsigned size) { - smc91c111_writeb(opaque, offset, value & 0xff); - smc91c111_writeb(opaque, offset + 1, value >> 8); + int i; + uint32_t val =3D 0; + + for (i =3D 0; i < size; i++) { + val |=3D smc91c111_readb(opaque, addr + i) << (i * 8); + } + return val; } =20 -static void smc91c111_writel(void *opaque, hwaddr offset, - uint32_t value) +static void smc91c111_writefn(void *opaque, hwaddr addr, + uint64_t value, unsigned size) { + int i =3D 0; + /* 32-bit writes to offset 0xc only actually write to the bank select - register (offset 0xe) */ - if (offset !=3D 0xc) - smc91c111_writew(opaque, offset, value & 0xffff); - smc91c111_writew(opaque, offset + 2, value >> 16); -} + * register (offset 0xe), so skip the first two bytes we would write. + */ + if (addr =3D=3D 0xc && size =3D=3D 4) { + i +=3D 2; + } =20 -static uint32_t smc91c111_readw(void *opaque, hwaddr offset) -{ - uint32_t val; - val =3D smc91c111_readb(opaque, offset); - val |=3D smc91c111_readb(opaque, offset + 1) << 8; - return val; -} - -static uint32_t smc91c111_readl(void *opaque, hwaddr offset) -{ - uint32_t val; - val =3D smc91c111_readw(opaque, offset); - val |=3D smc91c111_readw(opaque, offset + 2) << 16; - return val; + for (; i < size; i++) { + smc91c111_writeb(opaque, addr + i, + extract32(value, i * 8, 8)); + } } =20 static int smc91c111_can_receive_nc(NetClientState *nc) @@ -747,10 +743,10 @@ static const MemoryRegionOps smc91c111_mem_ops =3D { /* The special case for 32 bit writes to 0xc means we can't just * set .impl.min/max_access_size to 1, unfortunately */ - .old_mmio =3D { - .read =3D { smc91c111_readb, smc91c111_readw, smc91c111_readl, }, - .write =3D { smc91c111_writeb, smc91c111_writew, smc91c111_writel,= }, - }, + .read =3D smc91c111_readfn, + .write =3D smc91c111_writefn, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 4, .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 --=20 2.17.0