From nobody Wed Oct 29 11:33:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1525413719231133.29087108172598; Thu, 3 May 2018 23:01:59 -0700 (PDT) Received: from localhost ([::1]:60650 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fETmy-0007fA-Gg for importer@patchew.org; Fri, 04 May 2018 02:01:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43200) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fETkr-00062i-Mo for qemu-devel@nongnu.org; Fri, 04 May 2018 01:59:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fETkq-0007NC-ME for qemu-devel@nongnu.org; Fri, 04 May 2018 01:59:41 -0400 Received: from ozlabs.org ([203.11.71.1]:58705) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fETkq-0007IK-18; Fri, 04 May 2018 01:59:40 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 40chDQ4HVFz9s7T; Fri, 4 May 2018 15:59:34 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1525413574; bh=jl4R0ehcXlzrh7UisxrjFQAqchYQ/+5uHUWvYvlwG0k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YWw2zxcDjPIrSY6ry2dGSwX3oV0/sYNCWAVptXRrBAEpp78alzxztUPLSYQ0KWKhZ iKoD+SExQjmmvirlam/acTfsG2uSLXGHfeit7m5hb3ekkWqTkpk54mA4WzkXPQaYrl iFPZpd83Mq3UmcjluMoM4Orbbs1gXrol+AwnQKfQ= From: David Gibson To: peter.maydell@linaro.org Date: Fri, 4 May 2018 15:59:21 +1000 Message-Id: <20180504055930.3786-9-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180504055930.3786-1-david@gibson.dropbear.id.au> References: <20180504055930.3786-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 08/17] spapr: Clean up LPCR updates from hypercalls X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, groug@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" There are several places in spapr_hcall.c where we need to update the LPCR value on all CPUs. We do this with the set_spr() helper. That's not really correct because this directly sets the SPR value, without going through the ppc_store_lpcr() helper which may need to update state based on the LPCR change. In fact, set_spr() is only ever used for the LPCR, so replace it with an explicit LPCR updated which uses the right low-level helper. While we're there, move the CPU_FOREACH() which was in every one of the callers into the new helper: set_all_lpcrs(). Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater Tested-by: C=C3=A9dric Le Goater --- hw/ppc/spapr_hcall.c | 50 ++++++++++++++++++-------------------------- 1 file changed, 20 insertions(+), 30 deletions(-) diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 16bccdd5c0..ca9702e667 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -15,32 +15,35 @@ #include "hw/ppc/spapr_ovec.h" #include "mmu-book3s-v3.h" =20 -struct SPRSyncState { - int spr; +struct LPCRSyncState { target_ulong value; target_ulong mask; }; =20 -static void do_spr_sync(CPUState *cs, run_on_cpu_data arg) +static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) { - struct SPRSyncState *s =3D arg.host_ptr; + struct LPCRSyncState *s =3D arg.host_ptr; PowerPCCPU *cpu =3D POWERPC_CPU(cs); CPUPPCState *env =3D &cpu->env; + target_ulong lpcr; =20 cpu_synchronize_state(cs); - env->spr[s->spr] &=3D ~s->mask; - env->spr[s->spr] |=3D s->value; + lpcr =3D env->spr[SPR_LPCR]; + lpcr &=3D ~s->mask; + lpcr |=3D s->value; + ppc_store_lpcr(cpu, lpcr); } =20 -static void set_spr(CPUState *cs, int spr, target_ulong value, - target_ulong mask) +static void set_all_lpcrs(target_ulong value, target_ulong mask) { - struct SPRSyncState s =3D { - .spr =3D spr, + CPUState *cs; + struct LPCRSyncState s =3D { .value =3D value, .mask =3D mask }; - run_on_cpu(cs, do_spr_sync, RUN_ON_CPU_HOST_PTR(&s)); + CPU_FOREACH(cs) { + run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); + } } =20 static bool has_spr(PowerPCCPU *cpu, int spr) @@ -1235,8 +1238,6 @@ static target_ulong h_set_mode_resource_le(PowerPCCPU= *cpu, target_ulong value1, target_ulong value2) { - CPUState *cs; - if (value1) { return H_P3; } @@ -1246,16 +1247,12 @@ static target_ulong h_set_mode_resource_le(PowerPCC= PU *cpu, =20 switch (mflags) { case H_SET_MODE_ENDIAN_BIG: - CPU_FOREACH(cs) { - set_spr(cs, SPR_LPCR, 0, LPCR_ILE); - } + set_all_lpcrs(0, LPCR_ILE); spapr_pci_switch_vga(true); return H_SUCCESS; =20 case H_SET_MODE_ENDIAN_LITTLE: - CPU_FOREACH(cs) { - set_spr(cs, SPR_LPCR, LPCR_ILE, LPCR_ILE); - } + set_all_lpcrs(LPCR_ILE, LPCR_ILE); spapr_pci_switch_vga(false); return H_SUCCESS; } @@ -1268,7 +1265,6 @@ static target_ulong h_set_mode_resource_addr_trans_mo= de(PowerPCCPU *cpu, target_ulong value= 1, target_ulong value= 2) { - CPUState *cs; PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); =20 if (!(pcc->insns_flags2 & PPC2_ISA207S)) { @@ -1285,9 +1281,7 @@ static target_ulong h_set_mode_resource_addr_trans_mo= de(PowerPCCPU *cpu, return H_UNSUPPORTED_FLAG; } =20 - CPU_FOREACH(cs) { - set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SHIFT, LPCR_AIL); - } + set_all_lpcrs(mflags << LPCR_AIL_SHIFT, LPCR_AIL); =20 return H_SUCCESS; } @@ -1364,7 +1358,6 @@ static target_ulong h_register_process_table(PowerPCC= PU *cpu, target_ulong opcode, target_ulong *args) { - CPUState *cs; target_ulong flags =3D args[0]; target_ulong proc_tbl =3D args[1]; target_ulong page_size =3D args[2]; @@ -1422,12 +1415,9 @@ static target_ulong h_register_process_table(PowerPC= CPU *cpu, spapr->patb_entry =3D cproc; /* Save new process table */ =20 /* Update the UPRT and GTSE bits in the LPCR for all cpus */ - CPU_FOREACH(cs) { - set_spr(cs, SPR_LPCR, - ((flags & (FLAG_RADIX | FLAG_HASH_PROC_TBL)) ? LPCR_UPRT := 0) | - ((flags & FLAG_GTSE) ? LPCR_GTSE : 0), - LPCR_UPRT | LPCR_GTSE); - } + set_all_lpcrs(((flags & (FLAG_RADIX | FLAG_HASH_PROC_TBL)) ? LPCR_UPRT= : 0) | + ((flags & FLAG_GTSE) ? LPCR_GTSE : 0), + LPCR_UPRT | LPCR_GTSE); =20 if (kvm_enabled()) { return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX, --=20 2.17.0