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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id t23-v6sm26550809pgu.41.2018.05.03.22.40.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 May 2018 22:40:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=auk9ouSb7QU3BsQaEvGx0Fez2ojdqLsT2S6s/wdoReI=; b=c2p2mWA36dto8SV7UZA6QOosz0JsNdJWAfFmI++bGUiSI1H5MTrY23z3n8k0nOtVVG R57ze9WNGfo3ub/3Jh9yQ/lfiYK2q0STeYk6CxmxbyLS3gKqF27/19gOHGvfyHoq6cW0 2XUXbaJL6Q8Lch6PjjNiCNeKma2RYYcHnu4jM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=auk9ouSb7QU3BsQaEvGx0Fez2ojdqLsT2S6s/wdoReI=; b=Z+LXVfx1QAma0nx0VAxWgKQPxCuFzhBXX1SVCh5do2jEJeaSem8a4av0II+9awqqXy 0qCCt7e/kI5mWoJVam8gHR3cHqkl3jWcOfYZgqFuIosbd8SzhDxOSSSKIo1ayFmKjmVB p7LceDDPCOhxyd0x9IptEjwp+vcBkAfY6yj1tj0ZQCdxqgN4cYwej2GjDLfXlxOJW9AI 1clRiUq7dLq6T38Fls+qjc7SrLtw+RwI5Wmd1QqssuPZmfl6jBMq1N16rKqPxHJNjccD OWI+MjU0cl0Oj99ys2fAgGv9feX/wCYANrEWjyEH/wPBUY5PZ2HJWg0OP06JCGwD97DX en2w== X-Gm-Message-State: ALQs6tDw7kU3a62PfyNUsnQ5ORrsjeZIS2mbKlKEhu8Xc4D5Fwz+jTIz G55z1PtvGJzNOtpgbeX2zU9YqYcH0Us= X-Google-Smtp-Source: AB8JxZrhS1nONnycAYV429Ppb82dkndLtzs9XL6VFQ2j5+Jn31WwByt8n0pOKrMbs/lVy0XsSSTaFg== X-Received: by 2002:a17:902:14d:: with SMTP id 71-v6mr1749479plb.275.1525412439399; Thu, 03 May 2018 22:40:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 May 2018 22:40:22 -0700 Message-Id: <20180504054030.24527-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180504054030.24527-1-richard.henderson@linaro.org> References: <20180504054030.24527-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH 05/13] target/openrisc: Convert remainder of dec_misc insns X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Acked-by: Stafford Horne --- target/openrisc/translate.c | 279 +++++++++++++++++++--------------------= ---- target/openrisc/insns.decode | 35 +++++- 2 files changed, 151 insertions(+), 163 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 794002aaaa..0100fbc460 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -829,174 +829,118 @@ static bool trans_l_sh(DisasContext *dc, arg_store = *a, uint32_t insn) return true; } =20 -static void dec_misc(DisasContext *dc, uint32_t insn) +static bool trans_l_nop(DisasContext *dc, arg_l_nop *a, uint32_t insn) +{ + LOG_DIS("l.nop %d\n", a->k); + return true; +} + +static bool trans_l_addi(DisasContext *dc, arg_rri *a, uint32_t insn) { - uint32_t op0, op1; - uint32_t ra, rb, rd; - uint32_t L6, K5, K16, K5_11; - int32_t I16; TCGv t0; =20 - op0 =3D extract32(insn, 26, 6); - op1 =3D extract32(insn, 24, 2); - ra =3D extract32(insn, 16, 5); - rb =3D extract32(insn, 11, 5); - rd =3D extract32(insn, 21, 5); - L6 =3D extract32(insn, 5, 6); - K5 =3D extract32(insn, 0, 5); - K16 =3D extract32(insn, 0, 16); - I16 =3D (int16_t)K16; - K5_11 =3D (extract32(insn, 21, 5) << 11) | extract32(insn, 0, 11); + LOG_DIS("l.addi r%d, r%d, %d\n", a->d, a->a, a->i); + check_r0_write(a->d); + t0 =3D tcg_const_tl(a->i); + gen_add(dc, cpu_R[a->d], cpu_R[a->a], t0); + tcg_temp_free(t0); + return true; +} =20 - switch (op0) { - case 0x05: - switch (op1) { - case 0x01: /* l.nop */ - LOG_DIS("l.nop %d\n", I16); - break; +static bool trans_l_addic(DisasContext *dc, arg_rri *a, uint32_t insn) +{ + TCGv t0; =20 - default: - gen_illegal_exception(dc); - break; - } - break; + LOG_DIS("l.addic r%d, r%d, %d\n", a->d, a->a, a->i); + check_r0_write(a->d); + t0 =3D tcg_const_tl(a->i); + gen_addc(dc, cpu_R[a->d], cpu_R[a->a], t0); + tcg_temp_free(t0); + return true; +} =20 - case 0x13: /* l.maci */ - LOG_DIS("l.maci r%d, %d\n", ra, I16); - t0 =3D tcg_const_tl(I16); - gen_mac(dc, cpu_R[ra], t0); - tcg_temp_free(t0); - break; +static bool trans_l_muli(DisasContext *dc, arg_rri *a, uint32_t insn) +{ + TCGv t0; =20 - case 0x09: /* l.rfe */ - LOG_DIS("l.rfe\n"); - { -#if defined(CONFIG_USER_ONLY) - return; + LOG_DIS("l.muli r%d, r%d, %d\n", a->d, a->a, a->i); + check_r0_write(a->d); + t0 =3D tcg_const_tl(a->i); + gen_mul(dc, cpu_R[a->d], cpu_R[a->a], t0); + tcg_temp_free(t0); + return true; +} + +static bool trans_l_maci(DisasContext *dc, arg_l_maci *a, uint32_t insn) +{ + TCGv t0; + + LOG_DIS("l.maci r%d, %d\n", a->a, a->i); + t0 =3D tcg_const_tl(a->i); + gen_mac(dc, cpu_R[a->a], t0); + tcg_temp_free(t0); + return true; +} + +static bool trans_l_andi(DisasContext *dc, arg_rrk *a, uint32_t insn) +{ + LOG_DIS("l.andi r%d, r%d, %d\n", a->d, a->a, a->k); + check_r0_write(a->d); + tcg_gen_andi_tl(cpu_R[a->d], cpu_R[a->a], a->k); + return true; +} + +static bool trans_l_ori(DisasContext *dc, arg_rrk *a, uint32_t insn) +{ + LOG_DIS("l.ori r%d, r%d, %d\n", a->d, a->a, a->k); + check_r0_write(a->d); + tcg_gen_ori_tl(cpu_R[a->d], cpu_R[a->a], a->k); + return true; +} + +static bool trans_l_xori(DisasContext *dc, arg_rri *a, uint32_t insn) +{ + LOG_DIS("l.xori r%d, r%d, %d\n", a->d, a->a, a->i); + check_r0_write(a->d); + tcg_gen_xori_tl(cpu_R[a->d], cpu_R[a->a], a->i); + return true; +} + +static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a, uint32_t insn) +{ + LOG_DIS("l.mfspr r%d, r%d, %d\n", a->d, a->a, a->k); + check_r0_write(a->d); + +#ifdef CONFIG_USER_ONLY + gen_illegal_exception(dc); #else - if (dc->mem_idx =3D=3D MMU_USER_IDX) { - gen_illegal_exception(dc); - return; - } - gen_helper_rfe(cpu_env); - dc->is_jmp =3D DISAS_UPDATE; -#endif - } - break; - - case 0x1c: /* l.cust1 */ - LOG_DIS("l.cust1\n"); - break; - - case 0x1d: /* l.cust2 */ - LOG_DIS("l.cust2\n"); - break; - - case 0x1e: /* l.cust3 */ - LOG_DIS("l.cust3\n"); - break; - - case 0x1f: /* l.cust4 */ - LOG_DIS("l.cust4\n"); - break; - - case 0x3c: /* l.cust5 */ - LOG_DIS("l.cust5 r%d, r%d, r%d, %d, %d\n", rd, ra, rb, L6, K5); - break; - - case 0x3d: /* l.cust6 */ - LOG_DIS("l.cust6\n"); - break; - - case 0x3e: /* l.cust7 */ - LOG_DIS("l.cust7\n"); - break; - - case 0x3f: /* l.cust8 */ - LOG_DIS("l.cust8\n"); - break; - - case 0x27: /* l.addi */ - LOG_DIS("l.addi r%d, r%d, %d\n", rd, ra, I16); - check_r0_write(rd); - t0 =3D tcg_const_tl(I16); - gen_add(dc, cpu_R[rd], cpu_R[ra], t0); - tcg_temp_free(t0); - break; - - case 0x28: /* l.addic */ - LOG_DIS("l.addic r%d, r%d, %d\n", rd, ra, I16); - check_r0_write(rd); - t0 =3D tcg_const_tl(I16); - gen_addc(dc, cpu_R[rd], cpu_R[ra], t0); - tcg_temp_free(t0); - break; - - case 0x29: /* l.andi */ - LOG_DIS("l.andi r%d, r%d, %d\n", rd, ra, K16); - check_r0_write(rd); - tcg_gen_andi_tl(cpu_R[rd], cpu_R[ra], K16); - break; - - case 0x2a: /* l.ori */ - LOG_DIS("l.ori r%d, r%d, %d\n", rd, ra, K16); - check_r0_write(rd); - tcg_gen_ori_tl(cpu_R[rd], cpu_R[ra], K16); - break; - - case 0x2b: /* l.xori */ - LOG_DIS("l.xori r%d, r%d, %d\n", rd, ra, I16); - check_r0_write(rd); - tcg_gen_xori_tl(cpu_R[rd], cpu_R[ra], I16); - break; - - case 0x2c: /* l.muli */ - LOG_DIS("l.muli r%d, r%d, %d\n", rd, ra, I16); - check_r0_write(rd); - t0 =3D tcg_const_tl(I16); - gen_mul(dc, cpu_R[rd], cpu_R[ra], t0); - tcg_temp_free(t0); - break; - - case 0x2d: /* l.mfspr */ - LOG_DIS("l.mfspr r%d, r%d, %d\n", rd, ra, K16); - check_r0_write(rd); - { -#if defined(CONFIG_USER_ONLY) - return; -#else - TCGv_i32 ti =3D tcg_const_i32(K16); - if (dc->mem_idx =3D=3D MMU_USER_IDX) { - gen_illegal_exception(dc); - return; - } - gen_helper_mfspr(cpu_R[rd], cpu_env, cpu_R[rd], cpu_R[ra], ti); - tcg_temp_free_i32(ti); -#endif - } - break; - - case 0x30: /* l.mtspr */ - LOG_DIS("l.mtspr r%d, r%d, %d\n", ra, rb, K5_11); - { -#if defined(CONFIG_USER_ONLY) - return; -#else - TCGv_i32 im =3D tcg_const_i32(K5_11); - if (dc->mem_idx =3D=3D MMU_USER_IDX) { - gen_illegal_exception(dc); - return; - } - gen_helper_mtspr(cpu_env, cpu_R[ra], cpu_R[rb], im); - tcg_temp_free_i32(im); -#endif - } - break; - - default: + if (dc->mem_idx =3D=3D MMU_USER_IDX) { gen_illegal_exception(dc); - break; + } else { + TCGv_i32 ti =3D tcg_const_i32(a->k); + gen_helper_mfspr(cpu_R[a->d], cpu_env, cpu_R[a->d], cpu_R[a->a], t= i); + tcg_temp_free_i32(ti); } +#endif + return true; +} + +static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn) +{ + LOG_DIS("l.mtspr r%d, r%d, %d\n", a->a, a->b, a->k); + +#ifdef CONFIG_USER_ONLY + gen_illegal_exception(dc); +#else + if (dc->mem_idx =3D=3D MMU_USER_IDX) { + gen_illegal_exception(dc); + } else { + TCGv_i32 ti =3D tcg_const_i32(a->k); + gen_helper_mtspr(cpu_env, cpu_R[a->a], cpu_R[a->b], ti); + tcg_temp_free_i32(ti); + } +#endif + return true; } =20 static void dec_mac(DisasContext *dc, uint32_t insn) @@ -1272,6 +1216,23 @@ static bool trans_l_csync(DisasContext *dc, arg_l_cs= ync *a, uint32_t insn) return true; } =20 +static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a, uint32_t insn) +{ + LOG_DIS("l.rfe\n"); + +#ifdef CONFIG_USER_ONLY + gen_illegal_exception(dc); +#else + if (dc->mem_idx =3D=3D MMU_USER_IDX) { + gen_illegal_exception(dc); + } else { + gen_helper_rfe(cpu_env); + dc->is_jmp =3D DISAS_UPDATE; + } +#endif + return true; +} + static void dec_float(DisasContext *dc, uint32_t insn) { uint32_t op0; @@ -1534,7 +1495,7 @@ static void disas_openrisc_insn(DisasContext *dc, Ope= nRISCCPU *cpu) break; =20 default: - dec_misc(dc, insn); + gen_illegal_exception(dc); break; } } diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode index ba5356abe1..247a2e14f2 100644 --- a/target/openrisc/insns.decode +++ b/target/openrisc/insns.decode @@ -27,6 +27,8 @@ l_msync 001000 1000000000 00000000 00000000 l_psync 001000 1010000000 00000000 00000000 l_csync 001000 1100000000 00000000 00000000 =20 +l_rfe 001001 ----- ----- -------- -------- + #### # Branch Instructions #### @@ -58,7 +60,32 @@ l_lbs 100100 ..... ..... ........ ........ = @load l_lhz 100101 ..... ..... ........ ........ @load l_lhs 100110 ..... ..... ........ ........ @load =20 -l_swa 110011 ..... ..... ........ ........ @store -l_sw 110101 ..... ..... ........ ........ @store -l_sb 110110 ..... ..... ........ ........ @store -l_sh 110111 ..... ..... ........ ........ @store +l_swa 110011 ..... ..... ..... ........... @store +l_sw 110101 ..... ..... ..... ........... @store +l_sb 110110 ..... ..... ..... ........... @store +l_sh 110111 ..... ..... ..... ........... @store + +#### +# Immediate Operand Instructions +#### + +%mtspr_k 21:5 0:11 + +&rri d a i +&rrk d a k +@rri ...... d:5 a:5 i:s16 &rri +@rrk ...... d:5 a:5 k:16 &rrk + +l_nop 000101 01--- ----- k:16 + +l_addi 100111 ..... ..... ........ ........ @rri +l_addic 101000 ..... ..... ........ ........ @rri +l_andi 101001 ..... ..... ........ ........ @rrk +l_ori 101010 ..... ..... ........ ........ @rrk +l_xori 101011 ..... ..... ........ ........ @rri +l_muli 101100 ..... ..... ........ ........ @rri + +l_mfspr 101101 ..... ..... ........ ........ @rrk +l_mtspr 110000 ..... a:5 b:5 ........... k=3D%mtspr_k + +l_maci 010011 ----- a:5 i:s16 --=20 2.14.3