From nobody Wed Oct 29 20:26:45 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1525412567734201.57519417214212; Thu, 3 May 2018 22:42:47 -0700 (PDT) Received: from localhost ([::1]:60549 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fETUU-0001Cg-U8 for importer@patchew.org; Fri, 04 May 2018 01:42:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38319) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fETST-0008RT-LK for qemu-devel@nongnu.org; Fri, 04 May 2018 01:40:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fETSR-0004if-Lr for qemu-devel@nongnu.org; Fri, 04 May 2018 01:40:41 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:40427) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fETSR-0004hk-Ce for qemu-devel@nongnu.org; Fri, 04 May 2018 01:40:39 -0400 Received: by mail-pf0-x243.google.com with SMTP id f189so16571837pfa.7 for ; Thu, 03 May 2018 22:40:39 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id t23-v6sm26550809pgu.41.2018.05.03.22.40.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 May 2018 22:40:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qcI067d96aG0Nz/l27DvJ4pYg6jKEJqh69cpBEc9Hpk=; b=CWoWsGSyEpTGmm838GZgDFcGIkLWiRaXvSYySft5hm1R1vVXmKGLwzYiajPQ8bbH8K O+8oMIPu+lyGVRF21b/NjK4BrIYqi9NyDUmz6JaYqMKTzU0vVoMotcWGt0TEERrfzvT9 k4ddIPf+8sMW6fbN1HWKdFs6lD+DOlejgiBSU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qcI067d96aG0Nz/l27DvJ4pYg6jKEJqh69cpBEc9Hpk=; b=QbewXT1abYEYGJVnY/pBF+oCFC3JLMg0TQM37MgIVm5w5kahUYzZgNIG8cwO2SGXTr vKGe7w1ab9+dtIAdChV0NMgaNR/4dILh7XsE57EHZhKxochs3d7zF+oLEiQhJbFdwq2b oDyIbNBBqiy7VF9S6Vj1OTyDk9XI6LMAsw48qD2zLaTc9kWJV9A27IYoKvxUAefVo41o ViDnTGm9hLPXI0MUcPI/YgtL3HdExY7w8BzNbu/6zeSULI8psqobPQFh/Ns0PeKHhsnX 1ac3pSgQQkFDdmiZz30uw+paBzyRAbWHtUKS2VPtBz4mYk/RCiJ/eiCKjWb7/1+26WEX A11w== X-Gm-Message-State: ALQs6tBZ1LSTCHMRuikx9S+e5HMVxZ9NJVV4eXPq+qys9mq2gUygUqWT mb3uoywHMy7upVUQQZ8qr/wBeOe0jP0= X-Google-Smtp-Source: AB8JxZoJ13i6BpjNP9hWpnUvV7hr9c/JQ+NObNJb81kGFsHo4hfdYS4TTgp428vnF6mX/CrKsVsxtg== X-Received: by 2002:a17:902:b591:: with SMTP id a17-v6mr26250578pls.211.1525412438011; Thu, 03 May 2018 22:40:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 May 2018 22:40:21 -0700 Message-Id: <20180504054030.24527-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180504054030.24527-1-richard.henderson@linaro.org> References: <20180504054030.24527-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH 04/13] target/openrisc: Convert memory insns X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Acked-by: Stafford Horne --- target/openrisc/translate.c | 275 +++++++++++++++++++++------------------= ---- target/openrisc/insns.decode | 24 ++++ 2 files changed, 160 insertions(+), 139 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 95e4f17b8a..794002aaaa 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -457,51 +457,6 @@ static void gen_msbu(DisasContext *dc, TCGv srca, TCGv= srcb) gen_ove_cy(dc); } =20 -static void gen_lwa(DisasContext *dc, TCGv rd, TCGv ra, int32_t ofs) -{ - TCGv ea =3D tcg_temp_new(); - - tcg_gen_addi_tl(ea, ra, ofs); - tcg_gen_qemu_ld_tl(rd, ea, dc->mem_idx, MO_TEUL); - tcg_gen_mov_tl(cpu_lock_addr, ea); - tcg_gen_mov_tl(cpu_lock_value, rd); - tcg_temp_free(ea); -} - -static void gen_swa(DisasContext *dc, int b, TCGv ra, int32_t ofs) -{ - TCGv ea, val; - TCGLabel *lab_fail, *lab_done; - - ea =3D tcg_temp_new(); - tcg_gen_addi_tl(ea, ra, ofs); - - /* For TB_FLAGS_R0_0, the branch below invalidates the temporary assig= ned - to cpu_R[0]. Since l.swa is quite often immediately followed by a - branch, don't bother reallocating; finish the TB using the "real" R= 0. - This also takes care of RB input across the branch. */ - cpu_R[0] =3D cpu_R0; - - lab_fail =3D gen_new_label(); - lab_done =3D gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_NE, ea, cpu_lock_addr, lab_fail); - tcg_temp_free(ea); - - val =3D tcg_temp_new(); - tcg_gen_atomic_cmpxchg_tl(val, cpu_lock_addr, cpu_lock_value, - cpu_R[b], dc->mem_idx, MO_TEUL); - tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, val, cpu_lock_value); - tcg_temp_free(val); - - tcg_gen_br(lab_done); - - gen_set_label(lab_fail); - tcg_gen_movi_tl(cpu_sr_f, 0); - - gen_set_label(lab_done); - tcg_gen_movi_tl(cpu_lock_addr, -1); -} - static void dec_calc(DisasContext *dc, uint32_t insn) { uint32_t op0, op1, op2; @@ -739,13 +694,147 @@ static bool trans_l_jalr(DisasContext *dc, arg_l_jal= r *a, uint32_t insn) return true; } =20 +static bool trans_l_lwa(DisasContext *dc, arg_load *a, uint32_t insn) +{ + TCGv ea; + + LOG_DIS("l.lwa r%d, r%d, %d\n", a->d, a->a, a->i); + + check_r0_write(a->d); + ea =3D tcg_temp_new(); + tcg_gen_addi_tl(ea, cpu_R[a->a], a->i); + tcg_gen_qemu_ld_tl(cpu_R[a->d], ea, dc->mem_idx, MO_TEUL); + tcg_gen_mov_tl(cpu_lock_addr, ea); + tcg_gen_mov_tl(cpu_lock_value, cpu_R[a->d]); + tcg_temp_free(ea); + return true; +} + +static void do_load(DisasContext *dc, arg_load *a, TCGMemOp mop) +{ + TCGv ea; + + check_r0_write(a->d); + ea =3D tcg_temp_new(); + tcg_gen_addi_tl(ea, cpu_R[a->a], a->i); + tcg_gen_qemu_ld_tl(cpu_R[a->d], ea, dc->mem_idx, mop); + tcg_temp_free(ea); +} + +static bool trans_l_lwz(DisasContext *dc, arg_load *a, uint32_t insn) +{ + LOG_DIS("l.lwz r%d, r%d, %d\n", a->d, a->a, a->i); + do_load(dc, a, MO_TEUL); + return true; +} + +static bool trans_l_lws(DisasContext *dc, arg_load *a, uint32_t insn) +{ + LOG_DIS("l.lws r%d, r%d, %d\n", a->d, a->a, a->i); + do_load(dc, a, MO_TESL); + return true; +} + +static bool trans_l_lbz(DisasContext *dc, arg_load *a, uint32_t insn) +{ + LOG_DIS("l.lbz r%d, r%d, %d\n", a->d, a->a, a->i); + do_load(dc, a, MO_UB); + return true; +} + +static bool trans_l_lbs(DisasContext *dc, arg_load *a, uint32_t insn) +{ + LOG_DIS("l.lbs r%d, r%d, %d\n", a->d, a->a, a->i); + do_load(dc, a, MO_SB); + return true; +} + +static bool trans_l_lhz(DisasContext *dc, arg_load *a, uint32_t insn) +{ + LOG_DIS("l.lhz r%d, r%d, %d\n", a->d, a->a, a->i); + do_load(dc, a, MO_TEUW); + return true; +} + +static bool trans_l_lhs(DisasContext *dc, arg_load *a, uint32_t insn) +{ + LOG_DIS("l.lhs r%d, r%d, %d\n", a->d, a->a, a->i); + do_load(dc, a, MO_TESW); + return true; +} + +static bool trans_l_swa(DisasContext *dc, arg_store *a, uint32_t insn) +{ + TCGv ea, val; + TCGLabel *lab_fail, *lab_done; + + LOG_DIS("l.swa r%d, r%d, %d\n", a->a, a->b, a->i); + + ea =3D tcg_temp_new(); + tcg_gen_addi_tl(ea, cpu_R[a->a], a->i); + + /* For TB_FLAGS_R0_0, the branch below invalidates the temporary assig= ned + to cpu_R[0]. Since l.swa is quite often immediately followed by a + branch, don't bother reallocating; finish the TB using the "real" R= 0. + This also takes care of RB input across the branch. */ + cpu_R[0] =3D cpu_R0; + + lab_fail =3D gen_new_label(); + lab_done =3D gen_new_label(); + tcg_gen_brcond_tl(TCG_COND_NE, ea, cpu_lock_addr, lab_fail); + tcg_temp_free(ea); + + val =3D tcg_temp_new(); + tcg_gen_atomic_cmpxchg_tl(val, cpu_lock_addr, cpu_lock_value, + cpu_R[a->b], dc->mem_idx, MO_TEUL); + tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, val, cpu_lock_value); + tcg_temp_free(val); + + tcg_gen_br(lab_done); + + gen_set_label(lab_fail); + tcg_gen_movi_tl(cpu_sr_f, 0); + + gen_set_label(lab_done); + tcg_gen_movi_tl(cpu_lock_addr, -1); + return true; +} + +static void do_store(DisasContext *dc, arg_store *a, TCGMemOp mop) +{ + TCGv t0 =3D tcg_temp_new(); + tcg_gen_addi_tl(t0, cpu_R[a->a], a->i); + tcg_gen_qemu_st_tl(cpu_R[a->b], t0, dc->mem_idx, mop); + tcg_temp_free(t0); +} + +static bool trans_l_sw(DisasContext *dc, arg_store *a, uint32_t insn) +{ + LOG_DIS("l.sw r%d, r%d, %d\n", a->a, a->b, a->i); + do_store(dc, a, MO_TEUL); + return true; +} + +static bool trans_l_sb(DisasContext *dc, arg_store *a, uint32_t insn) +{ + LOG_DIS("l.sb r%d, r%d, %d\n", a->a, a->b, a->i); + do_store(dc, a, MO_UB); + return true; +} + +static bool trans_l_sh(DisasContext *dc, arg_store *a, uint32_t insn) +{ + LOG_DIS("l.sh r%d, r%d, %d\n", a->a, a->b, a->i); + do_store(dc, a, MO_TEUW); + return true; +} + static void dec_misc(DisasContext *dc, uint32_t insn) { uint32_t op0, op1; uint32_t ra, rb, rd; uint32_t L6, K5, K16, K5_11; - int32_t I16, I5_11; - TCGMemOp mop; + int32_t I16; TCGv t0; =20 op0 =3D extract32(insn, 26, 6); @@ -758,7 +847,6 @@ static void dec_misc(DisasContext *dc, uint32_t insn) K16 =3D extract32(insn, 0, 16); I16 =3D (int16_t)K16; K5_11 =3D (extract32(insn, 21, 5) << 11) | extract32(insn, 0, 11); - I5_11 =3D (int16_t)K5_11; =20 switch (op0) { case 0x05: @@ -796,12 +884,6 @@ static void dec_misc(DisasContext *dc, uint32_t insn) } break; =20 - case 0x1b: /* l.lwa */ - LOG_DIS("l.lwa r%d, r%d, %d\n", rd, ra, I16); - check_r0_write(rd); - gen_lwa(dc, cpu_R[rd], cpu_R[ra], I16); - break; - case 0x1c: /* l.cust1 */ LOG_DIS("l.cust1\n"); break; @@ -834,53 +916,6 @@ static void dec_misc(DisasContext *dc, uint32_t insn) LOG_DIS("l.cust8\n"); break; =20 -/* not used yet, open it when we need or64. */ -/*#ifdef TARGET_OPENRISC64 - case 0x20: l.ld - LOG_DIS("l.ld r%d, r%d, %d\n", rd, ra, I16); - check_ob64s(dc); - mop =3D MO_TEQ; - goto do_load; -#endif*/ - - case 0x21: /* l.lwz */ - LOG_DIS("l.lwz r%d, r%d, %d\n", rd, ra, I16); - mop =3D MO_TEUL; - goto do_load; - - case 0x22: /* l.lws */ - LOG_DIS("l.lws r%d, r%d, %d\n", rd, ra, I16); - mop =3D MO_TESL; - goto do_load; - - case 0x23: /* l.lbz */ - LOG_DIS("l.lbz r%d, r%d, %d\n", rd, ra, I16); - mop =3D MO_UB; - goto do_load; - - case 0x24: /* l.lbs */ - LOG_DIS("l.lbs r%d, r%d, %d\n", rd, ra, I16); - mop =3D MO_SB; - goto do_load; - - case 0x25: /* l.lhz */ - LOG_DIS("l.lhz r%d, r%d, %d\n", rd, ra, I16); - mop =3D MO_TEUW; - goto do_load; - - case 0x26: /* l.lhs */ - LOG_DIS("l.lhs r%d, r%d, %d\n", rd, ra, I16); - mop =3D MO_TESW; - goto do_load; - - do_load: - check_r0_write(rd); - t0 =3D tcg_temp_new(); - tcg_gen_addi_tl(t0, cpu_R[ra], I16); - tcg_gen_qemu_ld_tl(cpu_R[rd], t0, dc->mem_idx, mop); - tcg_temp_free(t0); - break; - case 0x27: /* l.addi */ LOG_DIS("l.addi r%d, r%d, %d\n", rd, ra, I16); check_r0_write(rd); @@ -958,44 +993,6 @@ static void dec_misc(DisasContext *dc, uint32_t insn) } break; =20 - case 0x33: /* l.swa */ - LOG_DIS("l.swa r%d, r%d, %d\n", ra, rb, I5_11); - gen_swa(dc, rb, cpu_R[ra], I5_11); - break; - -/* not used yet, open it when we need or64. */ -/*#ifdef TARGET_OPENRISC64 - case 0x34: l.sd - LOG_DIS("l.sd r%d, r%d, %d\n", ra, rb, I5_11); - check_ob64s(dc); - mop =3D MO_TEQ; - goto do_store; -#endif*/ - - case 0x35: /* l.sw */ - LOG_DIS("l.sw r%d, r%d, %d\n", ra, rb, I5_11); - mop =3D MO_TEUL; - goto do_store; - - case 0x36: /* l.sb */ - LOG_DIS("l.sb r%d, r%d, %d\n", ra, rb, I5_11); - mop =3D MO_UB; - goto do_store; - - case 0x37: /* l.sh */ - LOG_DIS("l.sh r%d, r%d, %d\n", ra, rb, I5_11); - mop =3D MO_TEUW; - goto do_store; - - do_store: - { - TCGv t0 =3D tcg_temp_new(); - tcg_gen_addi_tl(t0, cpu_R[ra], I5_11); - tcg_gen_qemu_st_tl(cpu_R[rb], t0, dc->mem_idx, mop); - tcg_temp_free(t0); - } - break; - default: gen_illegal_exception(dc); break; diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode index 8d35011eab..ba5356abe1 100644 --- a/target/openrisc/insns.decode +++ b/target/openrisc/insns.decode @@ -38,3 +38,27 @@ l_bf 000100 n:s26 =20 l_jr 010001 ---------- b:5 ----------- l_jalr 010010 ---------- b:5 ----------- + +#### +# Memory Instructions +#### + +&load d a i +@load ...... d:5 a:5 i:s16 &load + +%store_i 21:s5 0:11 +&store a b i +@store ...... ..... a:5 b:5 ........... &store i=3D%store_i + +l_lwa 011011 ..... ..... ........ ........ @load +l_lwz 100001 ..... ..... ........ ........ @load +l_lws 100010 ..... ..... ........ ........ @load +l_lbz 100011 ..... ..... ........ ........ @load +l_lbs 100100 ..... ..... ........ ........ @load +l_lhz 100101 ..... ..... ........ ........ @load +l_lhs 100110 ..... ..... ........ ........ @load + +l_swa 110011 ..... ..... ........ ........ @store +l_sw 110101 ..... ..... ........ ........ @store +l_sb 110110 ..... ..... ........ ........ @store +l_sh 110111 ..... ..... ........ ........ @store --=20 2.14.3