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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id t23-v6sm26550809pgu.41.2018.05.03.22.40.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 May 2018 22:40:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uTUwI4k4ccg7w5Uqa4MDHdVf4A7NlUSzJff8QpydOYQ=; b=Sb98MaW1p253DugHMLEDD/bmBJ8q0eygbO3ufINyHlGrDOBBt6znW+jpaGxuTMqjf8 9IgBrwOCu8Q/YDCGkyP4epxPoI9TIUB3+6DN17ImaRKSOFVliZO2FUZ5MSskNfQT8Zn1 imZUQIuaC89olYcojf5uiy2v1IT4X6YxQ4HsI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uTUwI4k4ccg7w5Uqa4MDHdVf4A7NlUSzJff8QpydOYQ=; b=MOJql4ldQ5pualJXfxkVa5+1wl+vwKr9nhlSW+lhRdrNMK8s+3ctIOJanVz+a9zF8n qXeblMhBMQFmGyyS9cFXiwD0a7XEUWigXgzJxm9nANdJqx5pLWZSYAKHTbWVjSbtkfzb nQwD1wmwNCWkTImpX+fBLr46Oa4wBFDl5nS5YUFsFwOCHO64dbetFK5zDlXpPnpTc/8K JBBzcrFp/fuE4ydNtQTtGucoZcoPehKSHxILiayCjLLLy1EUM0DVC7whGYBVym38FeFx P0ApYzX+FjE4qB1Hus2hXQjJruv4ul6j110LUotwuFSxb0VB5aJhSThHOEcq0wYNoY+v wFFQ== X-Gm-Message-State: ALQs6tAsQkR3JflN4X7cAcfK7jllK2Gq3QXSRx4kuQlTI3Xmfq7o8COW HPC8a1uCJOPDVyZzBYOQEqJX7cFCIDk= X-Google-Smtp-Source: AB8JxZrWdZ7/B6QRbroU8mKqvdsC2dPo5ZIV8kZ/DbAQ4Z2RthjO784yCwwWnklLkhT3xub10d7vjA== X-Received: by 2002:a17:902:5502:: with SMTP id f2-v6mr26514072pli.108.1525412446960; Thu, 03 May 2018 22:40:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 May 2018 22:40:28 -0700 Message-Id: <20180504054030.24527-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180504054030.24527-1-richard.henderson@linaro.org> References: <20180504054030.24527-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH 11/13] target/openrisc: Convert dec_compi X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Acked-by: Stafford Horne --- target/openrisc/translate.c | 116 +++++++++++++++++++++------------------= ---- target/openrisc/insns.decode | 12 +++++ 2 files changed, 70 insertions(+), 58 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 2c15b2713f..f02d04cbce 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1118,70 +1118,74 @@ static bool trans_l_sfles(DisasContext *dc, arg_ab = *a, TCGCond cond) return true; } =20 -static void dec_compi(DisasContext *dc, uint32_t insn) +static bool trans_l_sfeqi(DisasContext *dc, arg_ai *a, TCGCond cond) { - uint32_t op0, ra; - int32_t I16; + LOG_DIS("l.sfeqi r%d, %d\n", a->a, a->i); + tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[a->a], a->i); + return true; +} =20 - op0 =3D extract32(insn, 21, 5); - ra =3D extract32(insn, 16, 5); - I16 =3D sextract32(insn, 0, 16); +static bool trans_l_sfnei(DisasContext *dc, arg_ai *a, TCGCond cond) +{ + LOG_DIS("l.sfnei r%d, %d\n", a->a, a->i); + tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_f, cpu_R[a->a], a->i); + return true; +} =20 - switch (op0) { - case 0x0: /* l.sfeqi */ - LOG_DIS("l.sfeqi r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[ra], I16); - break; +static bool trans_l_sfgtui(DisasContext *dc, arg_ai *a, TCGCond cond) +{ + LOG_DIS("l.sfgtui r%d, %d\n", a->a, a->i); + tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[a->a], a->i); + return true; +} =20 - case 0x1: /* l.sfnei */ - LOG_DIS("l.sfnei r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_f, cpu_R[ra], I16); - break; +static bool trans_l_sfgeui(DisasContext *dc, arg_ai *a, TCGCond cond) +{ + LOG_DIS("l.sfgeui r%d, %d\n", a->a, a->i); + tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[a->a], a->i); + return true; +} =20 - case 0x2: /* l.sfgtui */ - LOG_DIS("l.sfgtui r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[ra], I16); - break; +static bool trans_l_sfltui(DisasContext *dc, arg_ai *a, TCGCond cond) +{ + LOG_DIS("l.sfltui r%d, %d\n", a->a, a->i); + tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[a->a], a->i); + return true; +} =20 - case 0x3: /* l.sfgeui */ - LOG_DIS("l.sfgeui r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[ra], I16); - break; +static bool trans_l_sfleui(DisasContext *dc, arg_ai *a, TCGCond cond) +{ + LOG_DIS("l.sfleui r%d, %d\n", a->a, a->i); + tcg_gen_setcondi_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[a->a], a->i); + return true; +} =20 - case 0x4: /* l.sfltui */ - LOG_DIS("l.sfltui r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[ra], I16); - break; +static bool trans_l_sfgtsi(DisasContext *dc, arg_ai *a, TCGCond cond) +{ + LOG_DIS("l.sfgtsi r%d, %d\n", a->a, a->i); + tcg_gen_setcondi_tl(TCG_COND_GT, cpu_sr_f, cpu_R[a->a], a->i); + return true; +} =20 - case 0x5: /* l.sfleui */ - LOG_DIS("l.sfleui r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[ra], I16); - break; +static bool trans_l_sfgesi(DisasContext *dc, arg_ai *a, TCGCond cond) +{ + LOG_DIS("l.sfgesi r%d, %d\n", a->a, a->i); + tcg_gen_setcondi_tl(TCG_COND_GE, cpu_sr_f, cpu_R[a->a], a->i); + return true; +} =20 - case 0xa: /* l.sfgtsi */ - LOG_DIS("l.sfgtsi r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_GT, cpu_sr_f, cpu_R[ra], I16); - break; +static bool trans_l_sfltsi(DisasContext *dc, arg_ai *a, TCGCond cond) +{ + LOG_DIS("l.sfltsi r%d, %d\n", a->a, a->i); + tcg_gen_setcondi_tl(TCG_COND_LT, cpu_sr_f, cpu_R[a->a], a->i); + return true; +} =20 - case 0xb: /* l.sfgesi */ - LOG_DIS("l.sfgesi r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_GE, cpu_sr_f, cpu_R[ra], I16); - break; - - case 0xc: /* l.sfltsi */ - LOG_DIS("l.sfltsi r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_LT, cpu_sr_f, cpu_R[ra], I16); - break; - - case 0xd: /* l.sflesi */ - LOG_DIS("l.sflesi r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_LE, cpu_sr_f, cpu_R[ra], I16); - break; - - default: - gen_illegal_exception(dc); - break; - } +static bool trans_l_sflesi(DisasContext *dc, arg_ai *a, TCGCond cond) +{ + LOG_DIS("l.sflesi r%d, %d\n", a->a, a->i); + tcg_gen_setcondi_tl(TCG_COND_LE, cpu_sr_f, cpu_R[a->a], a->i); + return true; } =20 static bool trans_l_sys(DisasContext *dc, arg_l_sys *a, uint32_t insn) @@ -1470,10 +1474,6 @@ static void disas_openrisc_insn(DisasContext *dc, Op= enRISCCPU *cpu) =20 op0 =3D extract32(insn, 26, 6); switch (op0) { - case 0x2f: - dec_compi(dc, insn); - break; - case 0x32: dec_float(dc, insn); break; diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode index 29d28ff5be..4ec0e2de3a 100644 --- a/target/openrisc/insns.decode +++ b/target/openrisc/insns.decode @@ -21,6 +21,7 @@ &da d a &ab a b &dal d a l +&ai a i =20 #### # System Instructions @@ -154,3 +155,14 @@ l_sfgts 111001 01010 a:5 b:5 ----------- l_sfges 111001 01011 a:5 b:5 ----------- l_sflts 111001 01100 a:5 b:5 ----------- l_sfles 111001 01101 a:5 b:5 ----------- + +l_sfeqi 101111 00000 a:5 i:s16 +l_sfnei 101111 00001 a:5 i:s16 +l_sfgtui 101111 00010 a:5 i:s16 +l_sfgeui 101111 00011 a:5 i:s16 +l_sfltui 101111 00100 a:5 i:s16 +l_sfleui 101111 00101 a:5 i:s16 +l_sfgtsi 101111 01010 a:5 i:s16 +l_sfgesi 101111 01011 a:5 i:s16 +l_sfltsi 101111 01100 a:5 i:s16 +l_sflesi 101111 01101 a:5 i:s16 --=20 2.14.3