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Iglesias" To: qemu-devel@nongnu.org Date: Thu, 3 May 2018 11:19:08 +0200 Message-Id: <20180503091922.28733-16-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180503091922.28733-1-edgar.iglesias@gmail.com> References: <20180503091922.28733-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PATCH v1 15/29] target-microblaze: Break out trap_userspace() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Break out trap_userspace() to avoid open coding it everywhere. For privileged insns, we now always stop translation of the current insn for cores without exceptions. Signed-off-by: Edgar E. Iglesias Reviewed-by: Richard Henderson --- target/microblaze/translate.c | 76 +++++++++++++++------------------------= ---- 1 file changed, 27 insertions(+), 49 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 57cd00ab3e..c0e8879416 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -179,6 +179,22 @@ static void write_carryi(DisasContext *dc, bool carry) tcg_temp_free_i32(t0); } =20 +/* + * Returns true if the insn is illegal in userspace. + * If exceptions are enabled, an exception is raised. + */ +static bool trap_userspace(DisasContext *dc, bool cond) +{ + int mem_index =3D cpu_mmu_index(&dc->cpu->env, false); + bool cond_user =3D cond && mem_index =3D=3D MMU_USER_IDX; + + if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) { + tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); + t_gen_raise_exception(dc, EXCP_HW_EXCP); + } + return cond_user; +} + /* True if ALU operand b is a small immediate that may deserve faster treatment. */ static inline int dec_alu_op_b_is_small_imm(DisasContext *dc) @@ -432,7 +448,6 @@ static void dec_msr(DisasContext *dc) CPUState *cs =3D CPU(dc->cpu); TCGv_i32 t0, t1; unsigned int sr, to, rn; - int mem_index =3D cpu_mmu_index(&dc->cpu->env, false); =20 sr =3D dc->imm & ((1 << 14) - 1); to =3D dc->imm & (1 << 14); @@ -452,10 +467,7 @@ static void dec_msr(DisasContext *dc) return; } =20 - if ((dc->tb_flags & MSR_EE_FLAG) - && mem_index =3D=3D MMU_USER_IDX && (dc->imm !=3D 4 && dc->imm= !=3D 0)) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + if (trap_userspace(dc, dc->imm !=3D 4 && dc->imm !=3D 0)) { return; } =20 @@ -480,13 +492,8 @@ static void dec_msr(DisasContext *dc) return; } =20 - if (to) { - if ((dc->tb_flags & MSR_EE_FLAG) - && mem_index =3D=3D MMU_USER_IDX) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); - return; - } + if (trap_userspace(dc, to)) { + return; } =20 #if !defined(CONFIG_USER_ONLY) @@ -738,7 +745,6 @@ static void dec_bit(DisasContext *dc) CPUState *cs =3D CPU(dc->cpu); TCGv_i32 t0; unsigned int op; - int mem_index =3D cpu_mmu_index(&dc->cpu->env, false); =20 op =3D dc->ir & ((1 << 9) - 1); switch (op) { @@ -784,22 +790,12 @@ static void dec_bit(DisasContext *dc) case 0x76: /* wdc. */ LOG_DIS("wdc r%d\n", dc->ra); - if ((dc->tb_flags & MSR_EE_FLAG) - && mem_index =3D=3D MMU_USER_IDX) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); - return; - } + trap_userspace(dc, true); break; case 0x68: /* wic. */ LOG_DIS("wic r%d\n", dc->ra); - if ((dc->tb_flags & MSR_EE_FLAG) - && mem_index =3D=3D MMU_USER_IDX) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); - return; - } + trap_userspace(dc, true); break; case 0xe0: if ((dc->tb_flags & MSR_EE_FLAG) @@ -1199,7 +1195,6 @@ static void dec_bcc(DisasContext *dc) static void dec_br(DisasContext *dc) { unsigned int dslot, link, abs, mbar; - int mem_index =3D cpu_mmu_index(&dc->cpu->env, false); =20 dslot =3D dc->ir & (1 << 20); abs =3D dc->ir & (1 << 19); @@ -1254,9 +1249,7 @@ static void dec_br(DisasContext *dc) if (!(dc->tb_flags & IMM_FLAG) && (dc->imm =3D=3D 8 || dc->imm= =3D=3D 0x18)) t_gen_raise_exception(dc, EXCP_BREAK); if (dc->imm =3D=3D 0) { - if ((dc->tb_flags & MSR_EE_FLAG) && mem_index =3D=3D MMU_U= SER_IDX) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + if (trap_userspace(dc, true)) { return; } =20 @@ -1331,12 +1324,15 @@ static inline void do_rte(DisasContext *dc) static void dec_rts(DisasContext *dc) { unsigned int b_bit, i_bit, e_bit; - int mem_index =3D cpu_mmu_index(&dc->cpu->env, false); =20 i_bit =3D dc->ir & (1 << 21); b_bit =3D dc->ir & (1 << 22); e_bit =3D dc->ir & (1 << 23); =20 + if (trap_userspace(dc, i_bit || b_bit || e_bit)) { + return; + } + dc->delayed_branch =3D 2; dc->tb_flags |=3D D_FLAG; tcg_gen_st_i32(tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG)), @@ -1344,27 +1340,12 @@ static void dec_rts(DisasContext *dc) =20 if (i_bit) { LOG_DIS("rtid ir=3D%x\n", dc->ir); - if ((dc->tb_flags & MSR_EE_FLAG) - && mem_index =3D=3D MMU_USER_IDX) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); - } dc->tb_flags |=3D DRTI_FLAG; } else if (b_bit) { LOG_DIS("rtbd ir=3D%x\n", dc->ir); - if ((dc->tb_flags & MSR_EE_FLAG) - && mem_index =3D=3D MMU_USER_IDX) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); - } dc->tb_flags |=3D DRTB_FLAG; } else if (e_bit) { LOG_DIS("rted ir=3D%x\n", dc->ir); - if ((dc->tb_flags & MSR_EE_FLAG) - && mem_index =3D=3D MMU_USER_IDX) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); - } dc->tb_flags |=3D DRTE_FLAG; } else LOG_DIS("rts ir=3D%x\n", dc->ir); @@ -1503,16 +1484,13 @@ static void dec_null(DisasContext *dc) /* Insns connected to FSL or AXI stream attached devices. */ static void dec_stream(DisasContext *dc) { - int mem_index =3D cpu_mmu_index(&dc->cpu->env, false); TCGv_i32 t_id, t_ctrl; int ctrl; =20 LOG_DIS("%s%s imm=3D%x\n", dc->rd ? "get" : "put", dc->type_b ? "" : "d", dc->imm); =20 - if ((dc->tb_flags & MSR_EE_FLAG) && (mem_index =3D=3D MMU_USER_IDX)) { - tcg_gen_movi_i32(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + if (trap_userspace(dc, true)) { return; } =20 --=20 2.14.1