From nobody Wed Oct 29 09:06:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1525328884446198.28665963539936; Wed, 2 May 2018 23:28:04 -0700 (PDT) Received: from localhost ([::1]:54202 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fE7il-0003pm-OB for importer@patchew.org; Thu, 03 May 2018 02:28:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40955) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fE7cr-00074q-RF for qemu-devel@nongnu.org; Thu, 03 May 2018 02:21:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fE7cn-0002NQ-4C for qemu-devel@nongnu.org; Thu, 03 May 2018 02:21:57 -0400 Received: from ozlabs.org ([203.11.71.1]:39273) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fE7cm-0002MO-8u; Thu, 03 May 2018 02:21:53 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 40c4mY4BWfz9s3Z; Thu, 3 May 2018 16:21:49 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1525328509; bh=DeNMrc1bCnpQKWo2jjIPOjiO6DUv8IivY+Hr+Kgaufs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fdD7XQkHSjQEpVySWtoR6dFk7f8LX+MiqvDFvac7azvcAJ9zLUiJvAR8zEZ1yhJoU 4fqROF2pV7B93LDrtAcTn3fTmZLlJaeK/ZZY/vaE28uxf5y8K/hPAWqCklzyuJYgxo yA16vcO2pFODKB2HpZ2++aa4lJGrDV29UGdaghIM= From: David Gibson To: groug@kaod.org, clg@kaod.org Date: Thu, 3 May 2018 16:21:38 +1000 Message-Id: <20180503062145.17899-2-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180503062145.17899-1-david@gibson.dropbear.id.au> References: <20180503062145.17899-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PATCH 1/8] target/ppc: Add ppc_store_lpcr() helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There are some fields in the cpu state which need to be updated when the LPCR register is changed, which is done by ppc_hash64_update_rmls() and ppc_hash64_update_vrma(). Code which alters env->spr[SPR_LPCR] needs to call them afterwards to make sure the state is up to date. That's easy to get wrong. The normal way of dealing with sitautions like that is to use a helper which both updates the basic register value and the derived state. So, do that. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Greg Kurz --- target/ppc/mmu-hash64.c | 15 +++++++++++---- target/ppc/mmu-hash64.h | 3 +-- target/ppc/translate_init.c | 6 +----- 3 files changed, 13 insertions(+), 11 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 7e0adecfd9..a1db20e3a8 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -942,7 +942,7 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_= ulong ptex, cpu->env.tlb_need_flush =3D TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLU= SH; } =20 -void ppc_hash64_update_rmls(PowerPCCPU *cpu) +static void ppc_hash64_update_rmls(PowerPCCPU *cpu) { CPUPPCState *env =3D &cpu->env; uint64_t lpcr =3D env->spr[SPR_LPCR]; @@ -977,7 +977,7 @@ void ppc_hash64_update_rmls(PowerPCCPU *cpu) } } =20 -void ppc_hash64_update_vrma(PowerPCCPU *cpu) +static void ppc_hash64_update_vrma(PowerPCCPU *cpu) { CPUPPCState *env =3D &cpu->env; const PPCHash64SegmentPageSizes *sps =3D NULL; @@ -1028,9 +1028,9 @@ void ppc_hash64_update_vrma(PowerPCCPU *cpu) slb->sps =3D sps; } =20 -void helper_store_lpcr(CPUPPCState *env, target_ulong val) +void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + CPUPPCState *env =3D &cpu->env; uint64_t lpcr =3D 0; =20 /* Filter out bits */ @@ -1096,6 +1096,13 @@ void helper_store_lpcr(CPUPPCState *env, target_ulon= g val) ppc_hash64_update_vrma(cpu); } =20 +void helper_store_lpcr(CPUPPCState *env, target_ulong val) +{ + PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + + ppc_store_lpcr(cpu, val); +} + void ppc_hash64_init(PowerPCCPU *cpu) { CPUPPCState *env =3D &cpu->env; diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h index f6349ccdb3..53dcec5b93 100644 --- a/target/ppc/mmu-hash64.h +++ b/target/ppc/mmu-hash64.h @@ -17,8 +17,7 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong pte0, target_ulong pte1); unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu, uint64_t pte0, uint64_t pte1); -void ppc_hash64_update_vrma(PowerPCCPU *cpu); -void ppc_hash64_update_rmls(PowerPCCPU *cpu); +void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val); void ppc_hash64_init(PowerPCCPU *cpu); void ppc_hash64_finalize(PowerPCCPU *cpu); #endif diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index c83c910a29..3fd380dad6 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -8940,15 +8940,11 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHy= pervisor *vhyp) /* We should be followed by a CPU reset but update the active value * just in case... */ - env->spr[SPR_LPCR] =3D lpcr->default_value; + ppc_store_lpcr(cpu, lpcr->default_value); =20 /* Set a full AMOR so guest can use the AMR as it sees fit */ env->spr[SPR_AMOR] =3D amor->default_value =3D 0xffffffffffffffffull; =20 - /* Update some env bits based on new LPCR value */ - ppc_hash64_update_rmls(cpu); - ppc_hash64_update_vrma(cpu); - /* Tell KVM that we're in PAPR mode */ if (kvm_enabled()) { kvmppc_set_papr(cpu); --=20 2.17.0 From nobody Wed Oct 29 09:06:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1525329055035844.836602190577; Wed, 2 May 2018 23:30:55 -0700 (PDT) Received: from localhost ([::1]:54232 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fE7lU-0006Hj-C3 for importer@patchew.org; Thu, 03 May 2018 02:30:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41141) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fE7dL-0007cH-U8 for qemu-devel@nongnu.org; Thu, 03 May 2018 02:22:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fE7dH-0002bQ-82 for qemu-devel@nongnu.org; Thu, 03 May 2018 02:22:27 -0400 Received: from ozlabs.org ([203.11.71.1]:40159) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fE7dG-0002ZI-JI; Thu, 03 May 2018 02:22:23 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 40c4mY5HVsz9s47; Thu, 3 May 2018 16:21:49 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1525328509; bh=/Ryi3PIrpIC+SGjFlZHGEmcHxvAnR6f7Cge1NZiZFOk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=G/jQCqA1vgf9YA2IrmelTzZaUrIr862zriRarvvW6F+8SXaMTE50wOHeZLu35iBZ0 abY5nYL5khYhqsFseXBEsgx1MhldfMb5Nw1kMrYPyVekJTYNRMPukMjvZx3iIKX7Zw gPDiyvYG/PUVgfdCB1oFSzJ9JUq59emUxEr2mnIc= From: David Gibson To: groug@kaod.org, clg@kaod.org Date: Thu, 3 May 2018 16:21:39 +1000 Message-Id: <20180503062145.17899-3-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180503062145.17899-1-david@gibson.dropbear.id.au> References: <20180503062145.17899-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PATCH 2/8] spapr: Clean up rtas_start_cpu() & rtas_stop_self() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This makes several minor cleanups to these functions: * Follow usual convention of an early exit on error, rather than having most of the body in an if * Clearer naming of cpu and cpu_. Now callcpu is the cpu from which the RTAS call is invoked, newcpu is the cpu which we're starting * Use cpu_synchronize_state() instead of kvm_cpu_synchronize_state() directly * Remove pointless comment describing what cpu_synchronize_state() does * Use ppc_store_lpcr() instead of directly writing the register field Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Greg Kurz --- hw/ppc/spapr_rtas.c | 66 ++++++++++++++++++++++----------------------- 1 file changed, 32 insertions(+), 34 deletions(-) diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index 0ec5fa4cfe..b251c130cb 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -32,7 +32,7 @@ #include "hw/qdev.h" #include "sysemu/device_tree.h" #include "sysemu/cpus.h" -#include "sysemu/kvm.h" +#include "sysemu/hw_accel.h" =20 #include "hw/ppc/spapr.h" #include "hw/ppc/spapr_vio.h" @@ -45,6 +45,7 @@ #include "qemu/cutils.h" #include "trace.h" #include "hw/ppc/fdt.h" +#include "target/ppc/mmu-hash64.h" =20 static void rtas_display_character(PowerPCCPU *cpu, sPAPRMachineState *spa= pr, uint32_t token, uint32_t nargs, @@ -140,13 +141,15 @@ static void spapr_cpu_set_endianness(PowerPCCPU *cpu) } } =20 -static void rtas_start_cpu(PowerPCCPU *cpu_, sPAPRMachineState *spapr, +static void rtas_start_cpu(PowerPCCPU *callcpu, sPAPRMachineState *spapr, uint32_t token, uint32_t nargs, target_ulong args, uint32_t nret, target_ulong rets) { target_ulong id, start, r3; - PowerPCCPU *cpu; + PowerPCCPU *newcpu; + CPUPPCState *env; + PowerPCCPUClass *pcc; =20 if (nargs !=3D 3 || nret !=3D 1) { rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); @@ -157,41 +160,37 @@ static void rtas_start_cpu(PowerPCCPU *cpu_, sPAPRMac= hineState *spapr, start =3D rtas_ld(args, 1); r3 =3D rtas_ld(args, 2); =20 - cpu =3D spapr_find_cpu(id); - if (cpu !=3D NULL) { - CPUState *cs =3D CPU(cpu); - CPUPPCState *env =3D &cpu->env; - PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); + newcpu =3D spapr_find_cpu(id); + if (!newcpu) { + /* Didn't find a matching cpu */ + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); + return; + } =20 - if (!cs->halted) { - rtas_st(rets, 0, RTAS_OUT_HW_ERROR); - return; - } + env =3D &newcpu->env; + pcc =3D POWERPC_CPU_GET_CLASS(newcpu); =20 - /* This will make sure qemu state is up to date with kvm, and - * mark it dirty so our changes get flushed back before the - * new cpu enters */ - kvm_cpu_synchronize_state(cs); + if (!CPU(newcpu)->halted) { + rtas_st(rets, 0, RTAS_OUT_HW_ERROR); + return; + } =20 - env->msr =3D (1ULL << MSR_SF) | (1ULL << MSR_ME); + cpu_synchronize_state(CPU(newcpu)); =20 - /* Enable Power-saving mode Exit Cause exceptions for the new CPU = */ - env->spr[SPR_LPCR] |=3D pcc->lpcr_pm; + env->msr =3D (1ULL << MSR_SF) | (1ULL << MSR_ME); + spapr_cpu_set_endianness(newcpu); + spapr_cpu_update_tb_offset(newcpu); + /* Enable Power-saving mode Exit Cause exceptions for the new CPU */ + ppc_store_lpcr(newcpu, env->spr[SPR_LPCR] | pcc->lpcr_pm); =20 - env->nip =3D start; - env->gpr[3] =3D r3; - cs->halted =3D 0; - spapr_cpu_set_endianness(cpu); - spapr_cpu_update_tb_offset(cpu); + env->nip =3D start; + env->gpr[3] =3D r3; =20 - qemu_cpu_kick(cs); + CPU(newcpu)->halted =3D 0; =20 - rtas_st(rets, 0, RTAS_OUT_SUCCESS); - return; - } + qemu_cpu_kick(CPU(newcpu)); =20 - /* Didn't find a matching cpu */ - rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); + rtas_st(rets, 0, RTAS_OUT_SUCCESS); } =20 static void rtas_stop_self(PowerPCCPU *cpu, sPAPRMachineState *spapr, @@ -203,13 +202,12 @@ static void rtas_stop_self(PowerPCCPU *cpu, sPAPRMach= ineState *spapr, CPUPPCState *env =3D &cpu->env; PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); =20 - cs->halted =3D 1; - qemu_cpu_kick(cs); - /* Disable Power-saving mode Exit Cause exceptions for the CPU. * This could deliver an interrupt on a dying CPU and crash the * guest */ - env->spr[SPR_LPCR] &=3D ~pcc->lpcr_pm; + ppc_store_lpcr(cpu, env->spr[SPR_LPCR] & ~pcc->lpcr_pm); + cs->halted =3D 1; + qemu_cpu_kick(cs); } =20 static inline int sysparm_st(target_ulong addr, target_ulong len, --=20 2.17.0 From nobody Wed Oct 29 09:06:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1525329202830739.2314070965303; Wed, 2 May 2018 23:33:22 -0700 (PDT) Received: from localhost ([::1]:54245 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fE7nu-0008EY-3t for importer@patchew.org; Thu, 03 May 2018 02:33:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41139) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fE7dL-0007cD-T1 for qemu-devel@nongnu.org; Thu, 03 May 2018 02:22:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fE7dH-0002bP-7e for qemu-devel@nongnu.org; Thu, 03 May 2018 02:22:27 -0400 Received: from ozlabs.org ([203.11.71.1]:59967) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fE7dG-0002ZP-KO; Thu, 03 May 2018 02:22:23 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 40c4mZ07VBz9s4Z; Thu, 3 May 2018 16:21:49 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1525328510; bh=GrzdhMq7wCrp683Cv5bEUxN+xi5UwBi5kezBI2bl/H0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZCe7LOjlV0buvGfHJw6wZIYfTjjkrjyxc6mlIR2TS6GVwkKg3druRE9BYTA2WEzz+ T+4c1Na9ctBYtV1V9f5oFNUuJtRDcybBJanvVYXN7ilyNohmcQCLcsPRZs068k8D4i 22Q5/wkcY/S8zXC+y9YgRWWDJH6MzgpNv32NEEYA= From: David Gibson To: groug@kaod.org, clg@kaod.org Date: Thu, 3 May 2018 16:21:40 +1000 Message-Id: <20180503062145.17899-4-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180503062145.17899-1-david@gibson.dropbear.id.au> References: <20180503062145.17899-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PATCH 3/8] spapr: Remove unhelpful helpers from rtas_start_cpu() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" rtas_start_cpu() calls spapr_cpu_update_tb_offset() and spapr_cpu_set_endianness() to initialize certain things in the new cpu's state. This is the only caller of those helpers, and they're each only a few lines long, so we might as well just fold them into the caller. In addition, those helpers initialize state on the new cpu to match that of the first cpu. That will generally work, but might be at least logically incorrect if the first cpu has been set offline by the guest. So, instead base the state on that of the cpu invoking the RTAS call, which is obviously active already. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Greg Kurz --- hw/ppc/spapr_rtas.c | 38 ++++++++++++++------------------------ 1 file changed, 14 insertions(+), 24 deletions(-) diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index b251c130cb..df073447c5 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -120,27 +120,6 @@ static void rtas_query_cpu_stopped_state(PowerPCCPU *c= pu_, rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); } =20 -/* - * Set the timebase offset of the CPU to that of first CPU. - * This helps hotplugged CPU to have the correct timebase offset. - */ -static void spapr_cpu_update_tb_offset(PowerPCCPU *cpu) -{ - PowerPCCPU *fcpu =3D POWERPC_CPU(first_cpu); - - cpu->env.tb_env->tb_offset =3D fcpu->env.tb_env->tb_offset; -} - -static void spapr_cpu_set_endianness(PowerPCCPU *cpu) -{ - PowerPCCPU *fcpu =3D POWERPC_CPU(first_cpu); - PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(fcpu); - - if (!pcc->interrupts_big_endian(fcpu)) { - cpu->env.spr[SPR_LPCR] |=3D LPCR_ILE; - } -} - static void rtas_start_cpu(PowerPCCPU *callcpu, sPAPRMachineState *spapr, uint32_t token, uint32_t nargs, target_ulong args, @@ -150,6 +129,7 @@ static void rtas_start_cpu(PowerPCCPU *callcpu, sPAPRMa= chineState *spapr, PowerPCCPU *newcpu; CPUPPCState *env; PowerPCCPUClass *pcc; + target_ulong lpcr; =20 if (nargs !=3D 3 || nret !=3D 1) { rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); @@ -178,10 +158,20 @@ static void rtas_start_cpu(PowerPCCPU *callcpu, sPAPR= MachineState *spapr, cpu_synchronize_state(CPU(newcpu)); =20 env->msr =3D (1ULL << MSR_SF) | (1ULL << MSR_ME); - spapr_cpu_set_endianness(newcpu); - spapr_cpu_update_tb_offset(newcpu); + /* Enable Power-saving mode Exit Cause exceptions for the new CPU */ - ppc_store_lpcr(newcpu, env->spr[SPR_LPCR] | pcc->lpcr_pm); + lpcr =3D env->spr[SPR_LPCR] | pcc->lpcr_pm; + if (!pcc->interrupts_big_endian(callcpu)) { + lpcr |=3D LPCR_ILE; + } + ppc_store_lpcr(newcpu, lpcr); + + /* + * Set the timebase offset of the new CPU to that of the invoking + * CPU. This helps hotplugged CPU to have the correct timebase + * offset. + */ + newcpu->env.tb_env->tb_offset =3D callcpu->env.tb_env->tb_offset; =20 env->nip =3D start; env->gpr[3] =3D r3; --=20 2.17.0 From nobody Wed Oct 29 09:06:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152532883249890.58392148680616; Wed, 2 May 2018 23:27:12 -0700 (PDT) Received: from localhost ([::1]:54200 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fE7hv-000320-NF for importer@patchew.org; Thu, 03 May 2018 02:27:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41137) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fE7dL-0007c9-QN for qemu-devel@nongnu.org; Thu, 03 May 2018 02:22:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fE7dH-0002bm-H9 for qemu-devel@nongnu.org; Thu, 03 May 2018 02:22:27 -0400 Received: from ozlabs.org ([203.11.71.1]:56543) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fE7dG-0002ZZ-TN; Thu, 03 May 2018 02:22:23 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 40c4mZ1Djcz9s4q; Thu, 3 May 2018 16:21:49 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1525328510; bh=RFN7eQLrLTOlb5OPnXdK03zjkFg1+sueMJmp0B2TlTI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aluqE62dn1xkaSPV5LcauNUEqyteVt6LKuAb7gJ1tQf0lhtKJ8sBtD+k+5jUyLCZD bPBxAhMLy3rkVKcD/3+NCuNakU3OLpJjafFJrSfh0jD0nQ1rlGgXKHr4lOh3AYyRAF eLQEh0oMZvfzRuwdFU0soqvCOruFl5CT90nNNIXA= From: David Gibson To: groug@kaod.org, clg@kaod.org Date: Thu, 3 May 2018 16:21:41 +1000 Message-Id: <20180503062145.17899-5-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180503062145.17899-1-david@gibson.dropbear.id.au> References: <20180503062145.17899-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PATCH 4/8] spapr: Make a helper to set up cpu entry point state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Under PAPR, only the boot CPU is active when the system starts. Other cpus must be explicitly activated using an RTAS call. The entry state for the boot and secondary cpus isn't identical, but it has some things in common. We're going to add a bit more common setup later, too, so to simplify make a helper which sets up the common entry state for both boot and secondary cpu threads. Signed-off-by: David Gibson Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Greg Kurz --- hw/ppc/spapr.c | 4 +--- hw/ppc/spapr_cpu_core.c | 9 +++++++++ hw/ppc/spapr_rtas.c | 6 ++---- include/hw/ppc/spapr_cpu_core.h | 3 +++ 4 files changed, 15 insertions(+), 7 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index b35aff5d81..944bee7a71 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1668,10 +1668,8 @@ static void spapr_machine_reset(void) g_free(fdt); =20 /* Set up the entry state */ - first_ppc_cpu->env.gpr[3] =3D fdt_addr; + spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); first_ppc_cpu->env.gpr[5] =3D 0; - first_cpu->halted =3D 0; - first_ppc_cpu->env.nip =3D SPAPR_ENTRY_POINT; =20 spapr->cas_reboot =3D false; } diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 01dbc69424..a98c7b04c6 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -52,6 +52,15 @@ static void spapr_cpu_reset(void *opaque) =20 } =20 +void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_u= long r3) +{ + CPUPPCState *env =3D &cpu->env; + + env->nip =3D nip; + env->gpr[3] =3D r3; + CPU(cpu)->halted =3D 0; +} + static void spapr_cpu_destroy(PowerPCCPU *cpu) { qemu_unregister_reset(spapr_cpu_reset, cpu); diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index df073447c5..840d198a8d 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -37,6 +37,7 @@ #include "hw/ppc/spapr.h" #include "hw/ppc/spapr_vio.h" #include "hw/ppc/spapr_rtas.h" +#include "hw/ppc/spapr_cpu_core.h" #include "hw/ppc/ppc.h" #include "hw/boards.h" =20 @@ -173,10 +174,7 @@ static void rtas_start_cpu(PowerPCCPU *callcpu, sPAPRM= achineState *spapr, */ newcpu->env.tb_env->tb_offset =3D callcpu->env.tb_env->tb_offset; =20 - env->nip =3D start; - env->gpr[3] =3D r3; - - CPU(newcpu)->halted =3D 0; + spapr_cpu_set_entry_state(newcpu, start, r3); =20 qemu_cpu_kick(CPU(newcpu)); =20 diff --git a/include/hw/ppc/spapr_cpu_core.h b/include/hw/ppc/spapr_cpu_cor= e.h index 1129f344aa..47dcfda12b 100644 --- a/include/hw/ppc/spapr_cpu_core.h +++ b/include/hw/ppc/spapr_cpu_core.h @@ -12,6 +12,7 @@ #include "hw/qdev.h" #include "hw/cpu/core.h" #include "target/ppc/cpu-qom.h" +#include "target/ppc/cpu.h" =20 #define TYPE_SPAPR_CPU_CORE "spapr-cpu-core" #define SPAPR_CPU_CORE(obj) \ @@ -38,4 +39,6 @@ typedef struct sPAPRCPUCoreClass { } sPAPRCPUCoreClass; =20 const char *spapr_get_cpu_core_type(const char *cpu_type); +void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_u= long r3); + #endif --=20 2.17.0 From nobody Wed Oct 29 09:06:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152532881832499.49639723551877; Wed, 2 May 2018 23:26:58 -0700 (PDT) Received: from localhost ([::1]:54199 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fE7hd-0002kN-H4 for importer@patchew.org; Thu, 03 May 2018 02:26:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40960) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fE7cs-00074w-2T for qemu-devel@nongnu.org; Thu, 03 May 2018 02:21:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fE7cq-0002Oe-7C for qemu-devel@nongnu.org; Thu, 03 May 2018 02:21:58 -0400 Received: from ozlabs.org ([203.11.71.1]:54075) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fE7cp-0002Ni-Hk; Thu, 03 May 2018 02:21:56 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 40c4mZ2fy7z9s4t; Thu, 3 May 2018 16:21:49 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1525328510; bh=9RpUHMQH050Aq+2UyiVgESkAulJuwB+o8P1TolCgnOc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SXIzfH4tzTmDo/XM9Ecjcp/vlK/f7UaufFn3fPkSi5kArms8YBT6/Ez2TEg4UyGyg Ph0QgLmreoUxHJ0VwO9Ii0hoMjW+AJDZKE00XNnq76aKxwPqiVXWzAVj9yiZm6PVZa uC2MW+wf6eL2/4A/Gv5vI811CwbwPoT47N1tBh0M= From: David Gibson To: groug@kaod.org, clg@kaod.org Date: Thu, 3 May 2018 16:21:42 +1000 Message-Id: <20180503062145.17899-6-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180503062145.17899-1-david@gibson.dropbear.id.au> References: <20180503062145.17899-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PATCH 5/8] spapr: Clean up LPCR updates from hypercalls X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There are several places in spapr_hcall.c where we need to update the LPCR value on all CPUs. We do this with the set_spr() helper. That's not really correct because this directly sets the SPR value, without going through the ppc_store_lpcr() helper which may need to update state based on the LPCR change. In fact, set_spr() is only ever used for the LPCR, so replace it with an explicit LPCR updated which uses the right low-level helper. While we're there, move the CPU_FOREACH() which was in every one of the callers into the new helper: set_all_lpcrs(). Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/spapr_hcall.c | 50 ++++++++++++++++++-------------------------- 1 file changed, 20 insertions(+), 30 deletions(-) diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 16bccdd5c0..ca9702e667 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -15,32 +15,35 @@ #include "hw/ppc/spapr_ovec.h" #include "mmu-book3s-v3.h" =20 -struct SPRSyncState { - int spr; +struct LPCRSyncState { target_ulong value; target_ulong mask; }; =20 -static void do_spr_sync(CPUState *cs, run_on_cpu_data arg) +static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) { - struct SPRSyncState *s =3D arg.host_ptr; + struct LPCRSyncState *s =3D arg.host_ptr; PowerPCCPU *cpu =3D POWERPC_CPU(cs); CPUPPCState *env =3D &cpu->env; + target_ulong lpcr; =20 cpu_synchronize_state(cs); - env->spr[s->spr] &=3D ~s->mask; - env->spr[s->spr] |=3D s->value; + lpcr =3D env->spr[SPR_LPCR]; + lpcr &=3D ~s->mask; + lpcr |=3D s->value; + ppc_store_lpcr(cpu, lpcr); } =20 -static void set_spr(CPUState *cs, int spr, target_ulong value, - target_ulong mask) +static void set_all_lpcrs(target_ulong value, target_ulong mask) { - struct SPRSyncState s =3D { - .spr =3D spr, + CPUState *cs; + struct LPCRSyncState s =3D { .value =3D value, .mask =3D mask }; - run_on_cpu(cs, do_spr_sync, RUN_ON_CPU_HOST_PTR(&s)); + CPU_FOREACH(cs) { + run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); + } } =20 static bool has_spr(PowerPCCPU *cpu, int spr) @@ -1235,8 +1238,6 @@ static target_ulong h_set_mode_resource_le(PowerPCCPU= *cpu, target_ulong value1, target_ulong value2) { - CPUState *cs; - if (value1) { return H_P3; } @@ -1246,16 +1247,12 @@ static target_ulong h_set_mode_resource_le(PowerPCC= PU *cpu, =20 switch (mflags) { case H_SET_MODE_ENDIAN_BIG: - CPU_FOREACH(cs) { - set_spr(cs, SPR_LPCR, 0, LPCR_ILE); - } + set_all_lpcrs(0, LPCR_ILE); spapr_pci_switch_vga(true); return H_SUCCESS; =20 case H_SET_MODE_ENDIAN_LITTLE: - CPU_FOREACH(cs) { - set_spr(cs, SPR_LPCR, LPCR_ILE, LPCR_ILE); - } + set_all_lpcrs(LPCR_ILE, LPCR_ILE); spapr_pci_switch_vga(false); return H_SUCCESS; } @@ -1268,7 +1265,6 @@ static target_ulong h_set_mode_resource_addr_trans_mo= de(PowerPCCPU *cpu, target_ulong value= 1, target_ulong value= 2) { - CPUState *cs; PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); =20 if (!(pcc->insns_flags2 & PPC2_ISA207S)) { @@ -1285,9 +1281,7 @@ static target_ulong h_set_mode_resource_addr_trans_mo= de(PowerPCCPU *cpu, return H_UNSUPPORTED_FLAG; } =20 - CPU_FOREACH(cs) { - set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SHIFT, LPCR_AIL); - } + set_all_lpcrs(mflags << LPCR_AIL_SHIFT, LPCR_AIL); =20 return H_SUCCESS; } @@ -1364,7 +1358,6 @@ static target_ulong h_register_process_table(PowerPCC= PU *cpu, target_ulong opcode, target_ulong *args) { - CPUState *cs; target_ulong flags =3D args[0]; target_ulong proc_tbl =3D args[1]; target_ulong page_size =3D args[2]; @@ -1422,12 +1415,9 @@ static target_ulong h_register_process_table(PowerPC= CPU *cpu, spapr->patb_entry =3D cproc; /* Save new process table */ =20 /* Update the UPRT and GTSE bits in the LPCR for all cpus */ - CPU_FOREACH(cs) { - set_spr(cs, SPR_LPCR, - ((flags & (FLAG_RADIX | FLAG_HASH_PROC_TBL)) ? LPCR_UPRT := 0) | - ((flags & FLAG_GTSE) ? LPCR_GTSE : 0), - LPCR_UPRT | LPCR_GTSE); - } + set_all_lpcrs(((flags & (FLAG_RADIX | FLAG_HASH_PROC_TBL)) ? LPCR_UPRT= : 0) | + ((flags & FLAG_GTSE) ? LPCR_GTSE : 0), + LPCR_UPRT | LPCR_GTSE); =20 if (kvm_enabled()) { return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX, --=20 2.17.0 From nobody Wed Oct 29 09:06:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1525328657146101.65211927266557; Wed, 2 May 2018 23:24:17 -0700 (PDT) Received: from localhost ([::1]:54182 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fE7ey-0008O9-Fe for importer@patchew.org; Thu, 03 May 2018 02:24:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40961) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fE7cs-00074y-2Y for qemu-devel@nongnu.org; Thu, 03 May 2018 02:21:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fE7cq-0002On-9A for qemu-devel@nongnu.org; Thu, 03 May 2018 02:21:58 -0400 Received: from ozlabs.org ([203.11.71.1]:43627) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fE7cp-0002Nk-J0; Thu, 03 May 2018 02:21:56 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 40c4mZ4qsxz9s7c; Thu, 3 May 2018 16:21:50 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1525328510; bh=ZDK5eQMz1gawVKTVAupvYaWEVwUEwLUxBKSs9mNwS9o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cB+v0/XevFnzplil84So7DsFy6tTKsKVw/E00sTb+7o3F1IeHJt1PvmSt7b299dWb xOD1mhbDspFCNJ0TFoG6BT9PB+sYMA+GhkMwosWWRVnH1twVUtfwtN20J89tDGW37/ ZeuBimE83FDJs7n7ul3OYAjYjXjs3iVshqvcvjPc= From: David Gibson To: groug@kaod.org, clg@kaod.org Date: Thu, 3 May 2018 16:21:43 +1000 Message-Id: <20180503062145.17899-7-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180503062145.17899-1-david@gibson.dropbear.id.au> References: <20180503062145.17899-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PATCH 6/8] target/ppc: Delay initialization of LPCR_UPRT for secondary cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In cpu_ppc_set_papr() the UPRT and GTSE bits of the LPCR default value are initialized based on on ppc64_radix_guest(). Which seems reasonable, except that ppc64_radix_guest() is based on spapr->patb_entry which is only set up in spapr_machine_reset, called _after_ cpu_ppc_set_papr() for boot cpus. Well, and the fact that modifying the SPR default value for an instance rather than a class is kind of yucky. The initialization here is really only necessary or valid for hotplugged cpus; the base cpu initialization already sets a value that's good enough for the boot cpus until the guest uses an hcall to configure it's preferred MMU mode. So, move this initialization to the rtas_start_cpu() path, at which point ppc64_radix_guest() will have a sensible value, to make sure secondary cpus come up in an MMU mode matching the existing cpus. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/spapr_rtas.c | 12 ++++++++++++ target/ppc/translate_init.c | 16 ---------------- 2 files changed, 12 insertions(+), 16 deletions(-) diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index 840d198a8d..652233bdf1 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -47,6 +47,7 @@ #include "trace.h" #include "hw/ppc/fdt.h" #include "target/ppc/mmu-hash64.h" +#include "target/ppc/mmu-book3s-v3.h" =20 static void rtas_display_character(PowerPCCPU *cpu, sPAPRMachineState *spa= pr, uint32_t token, uint32_t nargs, @@ -165,6 +166,17 @@ static void rtas_start_cpu(PowerPCCPU *callcpu, sPAPRM= achineState *spapr, if (!pcc->interrupts_big_endian(callcpu)) { lpcr |=3D LPCR_ILE; } + if (env->mmu_model =3D=3D POWERPC_MMU_3_00) { + /* + * New cpus are expected to start in the same radix/hash mode + * as the existing CPUs + */ + if (ppc64_radix_guest(callcpu)) { + lpcr |=3D LPCR_UPRT | LPCR_GTSE; + } else { + lpcr &=3D ~(LPCR_UPRT | LPCR_GTSE); + } + } ppc_store_lpcr(newcpu, lpcr); =20 /* diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index 3fd380dad6..d92a84c622 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -8914,22 +8914,6 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHyp= ervisor *vhyp) lpcr->default_value &=3D ~LPCR_RMLS; lpcr->default_value |=3D 1ull << LPCR_RMLS_SHIFT; =20 - if (env->mmu_model =3D=3D POWERPC_MMU_3_00) { - /* By default we choose legacy mode and switch to new hash or radix - * when a register process table hcall is made. So disable process - * tables and guest translation shootdown by default - * - * Hot-plugged CPUs inherit from the guest radix setting under - * KVM but not under TCG. Update the default LPCR to keep new - * CPUs in sync when radix is enabled. - */ - if (ppc64_radix_guest(cpu)) { - lpcr->default_value |=3D LPCR_UPRT | LPCR_GTSE; - } else { - lpcr->default_value &=3D ~(LPCR_UPRT | LPCR_GTSE); - } - } - /* Only enable Power-saving mode Exit Cause exceptions on the boot * CPU. The RTAS command start-cpu will enable them on secondaries. */ --=20 2.17.0 From nobody Wed Oct 29 09:06:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1525328680795864.314603573385; Wed, 2 May 2018 23:24:40 -0700 (PDT) Received: from localhost ([::1]:54183 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fE7fT-0000N6-Um for importer@patchew.org; Thu, 03 May 2018 02:24:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41144) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fE7dM-0007cV-5h for qemu-devel@nongnu.org; Thu, 03 May 2018 02:22:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fE7dK-0002dz-9R for qemu-devel@nongnu.org; Thu, 03 May 2018 02:22:28 -0400 Received: from ozlabs.org ([203.11.71.1]:35373) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fE7dJ-0002bu-LY; Thu, 03 May 2018 02:22:26 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 40c4mZ46lpz9s7S; Thu, 3 May 2018 16:21:50 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1525328510; bh=6z37zXFFwpoqJMLLrZKWLLhY0jbHNz0VJOMpkueG03s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=m1HjV+Uy12zuFddbY7HTfx3q5pg0wMUpY2t6RF9LFLOqrPvcYp6ncvae790JCyBVf yLKRhAAXeTPv612f6f4xonun2aZ2AKAM+LzgvZZOUlKqQuPk91t2agwjZcFBMa6Bwt t9fVFOqcA5BxMlN9kIKMq3VFH4Ne3ZhMg7KL+6jM= From: David Gibson To: groug@kaod.org, clg@kaod.org Date: Thu, 3 May 2018 16:21:44 +1000 Message-Id: <20180503062145.17899-8-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180503062145.17899-1-david@gibson.dropbear.id.au> References: <20180503062145.17899-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PATCH 7/8] spapr: Move PAPR mode cpu setup fully to spapr code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" cpu_ppc_set_papr() does several things: 1) it sets up the virtual hypervisor interface 2) it prevents the cpu from ever entering hypervisor mode 3) it tells KVM that we're emulating a cpu in PAPR mode and 4) it configures the LPCR and AMOR (hypervisor privileged registers) so that TCG will behave correctly for PAPR guests, without attempting to emulate the cpu in hypervisor mode (1) & (2) make sense for any virtual hypervisor (if another one ever exists). (3) belongs more properly in the machine type specific to a PAPR guest, so move it to spapr_cpu_init(). While we're at it, remove an ugly test on kvm_enabled() by making kvmppc_set_papr() a safe no-op on non-KVM. (4) also belongs more properly in the machine type specific code. (4) is done by mangling the default values of the SPRs, so that they will be set correctly at reset time. Manipulating usually-static parameters of the cpu model like this is kind of ugly, especially since the values used really have more to do with the platform than the cpu. The spapr code already has places for PAPR specific initializations of register state in spapr_cpu_reset(), so move this handling there. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/spapr_cpu_core.c | 36 ++++++++++++++++++++++++++++--- target/ppc/cpu.h | 2 +- target/ppc/kvm.c | 4 ++++ target/ppc/translate_init.c | 42 +------------------------------------ 4 files changed, 39 insertions(+), 45 deletions(-) diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index a98c7b04c6..a52ddade5e 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -28,6 +28,7 @@ static void spapr_cpu_reset(void *opaque) CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); + target_ulong lpcr; =20 cpu_reset(cs); =20 @@ -43,13 +44,42 @@ static void spapr_cpu_reset(void *opaque) =20 env->spr[SPR_HIOR] =3D 0; =20 + lpcr =3D env->spr[SPR_LPCR]; + + /* Set emulated LPCR to not send interrupts to hypervisor. Note that + * under KVM, the actual HW LPCR will be set differently by KVM itself, + * the settings below ensure proper operations with TCG in absence of + * a real hypervisor. + * + * Clearing VPM0 will also cause us to use RMOR in mmu-hash64.c for + * real mode accesses, which thankfully defaults to 0 and isn't + * accessible in guest mode. + */ + lpcr &=3D ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV); + lpcr |=3D LPCR_LPES0 | LPCR_LPES1; + + /* Set RMLS to the max (ie, 16G) */ + lpcr &=3D ~LPCR_RMLS; + lpcr |=3D 1ull << LPCR_RMLS_SHIFT; + + /* Only enable Power-saving mode Exit Cause exceptions on the boot + * CPU. The RTAS command start-cpu will enable them on secondaries. + */ + if (cs =3D=3D first_cpu) { + lpcr |=3D pcc->lpcr_pm; + } + /* Disable Power-saving mode Exit Cause exceptions for the CPU. * This can cause issues when rebooting the guest if a secondary * is awaken */ if (cs !=3D first_cpu) { - env->spr[SPR_LPCR] &=3D ~pcc->lpcr_pm; + lpcr &=3D ~pcc->lpcr_pm; } =20 + ppc_store_lpcr(cpu, lpcr); + + /* Set a full AMOR so guest can use the AMR as it sees fit */ + env->spr[SPR_AMOR] =3D 0xffffffffffffffffull; } =20 void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_u= long r3) @@ -74,8 +104,8 @@ static void spapr_cpu_init(sPAPRMachineState *spapr, Pow= erPCCPU *cpu, /* Set time-base frequency to 512 MHz */ cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ); =20 - /* Enable PAPR mode in TCG or KVM */ - cpu_ppc_set_papr(cpu, PPC_VIRTUAL_HYPERVISOR(spapr)); + cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr)); + kvmppc_set_papr(cpu); =20 qemu_register_reset(spapr_cpu_reset, cpu); spapr_cpu_reset(cpu); diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 2f619f39d3..7ccd2f460e 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1332,7 +1332,7 @@ void store_booke_tcr (CPUPPCState *env, target_ulong = val); void store_booke_tsr (CPUPPCState *env, target_ulong val); void ppc_tlb_invalidate_all (CPUPPCState *env); void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr); -void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp); +void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp); #endif #endif =20 diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 6de59c5b21..28311a98e0 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -2090,6 +2090,10 @@ void kvmppc_set_papr(PowerPCCPU *cpu) CPUState *cs =3D CPU(cpu); int ret; =20 + if (!kvm_enabled()) { + return; + } + ret =3D kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_PAPR, 0); if (ret) { error_report("This vCPU type or KVM version does not support PAPR"= ); diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index d92a84c622..118631efbe 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -8882,13 +8882,9 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) } =20 #if !defined(CONFIG_USER_ONLY) -void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) +void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) { - PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); CPUPPCState *env =3D &cpu->env; - ppc_spr_t *lpcr =3D &env->spr_cb[SPR_LPCR]; - ppc_spr_t *amor =3D &env->spr_cb[SPR_AMOR]; - CPUState *cs =3D CPU(cpu); =20 cpu->vhyp =3D vhyp; =20 @@ -8897,42 +8893,6 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHyp= ervisor *vhyp) * hypervisor mode itself */ env->msr_mask &=3D ~MSR_HVB; - - /* Set emulated LPCR to not send interrupts to hypervisor. Note that - * under KVM, the actual HW LPCR will be set differently by KVM itself, - * the settings below ensure proper operations with TCG in absence of - * a real hypervisor. - * - * Clearing VPM0 will also cause us to use RMOR in mmu-hash64.c for - * real mode accesses, which thankfully defaults to 0 and isn't - * accessible in guest mode. - */ - lpcr->default_value &=3D ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV= ); - lpcr->default_value |=3D LPCR_LPES0 | LPCR_LPES1; - - /* Set RMLS to the max (ie, 16G) */ - lpcr->default_value &=3D ~LPCR_RMLS; - lpcr->default_value |=3D 1ull << LPCR_RMLS_SHIFT; - - /* Only enable Power-saving mode Exit Cause exceptions on the boot - * CPU. The RTAS command start-cpu will enable them on secondaries. - */ - if (cs =3D=3D first_cpu) { - lpcr->default_value |=3D pcc->lpcr_pm; - } - - /* We should be followed by a CPU reset but update the active value - * just in case... - */ - ppc_store_lpcr(cpu, lpcr->default_value); - - /* Set a full AMOR so guest can use the AMR as it sees fit */ - env->spr[SPR_AMOR] =3D amor->default_value =3D 0xffffffffffffffffull; - - /* Tell KVM that we're in PAPR mode */ - if (kvm_enabled()) { - kvmppc_set_papr(cpu); - } } =20 #endif /* !defined(CONFIG_USER_ONLY) */ --=20 2.17.0 From nobody Wed Oct 29 09:06:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152532865714957.593715792051626; Wed, 2 May 2018 23:24:17 -0700 (PDT) Received: from localhost ([::1]:54181 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fE7ey-0008NX-87 for importer@patchew.org; Thu, 03 May 2018 02:24:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40962) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fE7cs-00074z-2r for qemu-devel@nongnu.org; Thu, 03 May 2018 02:21:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fE7cq-0002Os-9j for qemu-devel@nongnu.org; Thu, 03 May 2018 02:21:58 -0400 Received: from ozlabs.org ([203.11.71.1]:52433) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fE7cp-0002Nj-K7; Thu, 03 May 2018 02:21:56 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 40c4mZ5rMhz9s7X; Thu, 3 May 2018 16:21:50 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1525328510; bh=i4ELIl7hpknpcdceDGInniFoBkrKQv+zVbkat9uYNHM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cWJ8kq+2503K5cA5hPmG7mcYy7Wc27MF8g/fzDYUOY/C3xUBCcrt1O/d3jIJ3HH5u eUnPCyfeuLtZ3dP+f2/IscdFruyEcrsdT2s0k6NfxPboPGaQtJjgHqcQIHMgBsRdSH JoDEx+V7BsKIMUNXUkmEcutiTvw6+WHyxhLDHMSM= From: David Gibson To: groug@kaod.org, clg@kaod.org Date: Thu, 3 May 2018 16:21:45 +1000 Message-Id: <20180503062145.17899-9-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180503062145.17899-1-david@gibson.dropbear.id.au> References: <20180503062145.17899-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PATCH 8/8] spapr: Clean up handling of LPCR power-saving exit bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" To prevent spurious wakeups on cpus that are supposed to be disabled, we need to clear the LPCR bits which control certain wakeup events. spapr_cpu_reset() has separate cases here for boot and non-boot (initially inactive) cpus. rtas_start_cpu() then turns the LPCR bits on when the non-boot cpus are activated. But explicit checks against first_cpu are not how we usually do things: instead spapr_cpu_reset() generally sets things up for non-boot (inactive) cpus, then spapr_machine_reset() and/or rtas_start_cpu() override as necessary. So, do that instead. Because the LPCR activation is identical for boot cpus and non-boot cpus just activated with rtas_start_cpu() we can put the code common in spapr_cpu_set_entry_state(). Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater Tested-by: C=C3=A9dric Le Goater --- hw/ppc/spapr_cpu_core.c | 22 +++++++--------------- hw/ppc/spapr_rtas.c | 2 +- 2 files changed, 8 insertions(+), 16 deletions(-) diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index a52ddade5e..f3e9b879b2 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -54,28 +54,17 @@ static void spapr_cpu_reset(void *opaque) * Clearing VPM0 will also cause us to use RMOR in mmu-hash64.c for * real mode accesses, which thankfully defaults to 0 and isn't * accessible in guest mode. + * + * Disable Power-saving mode Exit Cause exceptions for the CPU, so + * we don't get spurious wakups before an RTAS start-cpu call. */ - lpcr &=3D ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV); + lpcr &=3D ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm= ); lpcr |=3D LPCR_LPES0 | LPCR_LPES1; =20 /* Set RMLS to the max (ie, 16G) */ lpcr &=3D ~LPCR_RMLS; lpcr |=3D 1ull << LPCR_RMLS_SHIFT; =20 - /* Only enable Power-saving mode Exit Cause exceptions on the boot - * CPU. The RTAS command start-cpu will enable them on secondaries. - */ - if (cs =3D=3D first_cpu) { - lpcr |=3D pcc->lpcr_pm; - } - - /* Disable Power-saving mode Exit Cause exceptions for the CPU. - * This can cause issues when rebooting the guest if a secondary - * is awaken */ - if (cs !=3D first_cpu) { - lpcr &=3D ~pcc->lpcr_pm; - } - ppc_store_lpcr(cpu, lpcr); =20 /* Set a full AMOR so guest can use the AMR as it sees fit */ @@ -84,11 +73,14 @@ static void spapr_cpu_reset(void *opaque) =20 void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_u= long r3) { + PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); CPUPPCState *env =3D &cpu->env; =20 env->nip =3D nip; env->gpr[3] =3D r3; CPU(cpu)->halted =3D 0; + /* Enable Power-saving mode Exit Cause exceptions */ + ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm); } =20 static void spapr_cpu_destroy(PowerPCCPU *cpu) diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index 652233bdf1..7f9738daed 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -162,7 +162,7 @@ static void rtas_start_cpu(PowerPCCPU *callcpu, sPAPRMa= chineState *spapr, env->msr =3D (1ULL << MSR_SF) | (1ULL << MSR_ME); =20 /* Enable Power-saving mode Exit Cause exceptions for the new CPU */ - lpcr =3D env->spr[SPR_LPCR] | pcc->lpcr_pm; + lpcr =3D env->spr[SPR_LPCR]; if (!pcc->interrupts_big_endian(callcpu)) { lpcr |=3D LPCR_ILE; } --=20 2.17.0