From nobody Thu Oct 30 15:35:24 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1525300032031533.190482222593; Wed, 2 May 2018 15:27:12 -0700 (PDT) Received: from localhost ([::1]:52860 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fE0DP-0001CM-64 for importer@patchew.org; Wed, 02 May 2018 18:27:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58836) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fE02i-0000kf-G7 for qemu-devel@nongnu.org; Wed, 02 May 2018 18:16:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fE02g-0007w5-FB for qemu-devel@nongnu.org; Wed, 02 May 2018 18:16:08 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:34998) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fE02g-0007ve-A5 for qemu-devel@nongnu.org; Wed, 02 May 2018 18:16:06 -0400 Received: by mail-pg0-x244.google.com with SMTP id j11-v6so11635426pgf.2 for ; Wed, 02 May 2018 15:16:06 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id 65sm26170145pft.74.2018.05.02.15.16.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 02 May 2018 15:16:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4QcG9pnmYxuAv/iY+aAUQ08duv6GdfnD0qVmKawXzqg=; b=O6G1H5bwAy6nF1xzP92ziwnJEMyNGIxbdKwGR8DY3gAbzjAHG1agj0myOwkc+ZEOMX PaIP/AA5g8qEZPo3qz8GTTKE4alzlfWKILBNxuNbv/EemkCfgerRjrtUtYvcw+3ILuEF mIxKVEiyg21xFWxxTznC7xdKOpEBsFWki5FwE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4QcG9pnmYxuAv/iY+aAUQ08duv6GdfnD0qVmKawXzqg=; b=ugshnaHyqemmhW0Yliaz2rPc6RWFeIx7e9sbH4Ty8c3oNlUrzhC2c7PR277mMQyjeF H91poUDTTwu8h/kY9izcz3Ejlh1sTSwNFHJlYVqp/YS2fQ8kNmmvhI0aW+E21TcTsmnz 7/y9VylHJfC9k0l3vuQDOtKHhdIbqgphyRJMJxsosj2fn0NHfW48lUR/ABHb3T3gkpf9 c8YWFjF+qjj/B2M+f+wig7zlk0xsXPMna7L62eQbmfNe0F7WX/HWbyQPURzX1sUciJtv DT4SvxamDJm+nkLeVqtwo+fGBqJL8gK4swAK9R+jDaFXWIpu4R9IhnKYnPAbnsd++/n6 Fivg== X-Gm-Message-State: ALQs6tDmJVZrua3btbuBD06Z9j+JMfag5sHEyEqlq7KrHCyP0TQ3FAhs zutxtMAVNX0gjTjq+KRYEVL6gnTKjEo= X-Google-Smtp-Source: AB8JxZrsKMfOxXLBfKHEecod/9e8GezUiWIq0MuOCXOZkXlqtfKRgDM10+hI+wDtwfSoSuLXSPYs3w== X-Received: by 10.98.129.5 with SMTP id t5mr20762673pfd.215.1525299365040; Wed, 02 May 2018 15:16:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 2 May 2018 15:15:46 -0700 Message-Id: <20180502221552.3873-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180502221552.3873-1-richard.henderson@linaro.org> References: <20180502221552.3873-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v2 08/14] target/arm: Introduce and use read_fp_hreg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-a64.c | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e19d97e8f1..8c63d5e743 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -614,6 +614,14 @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg) return v; } =20 +static TCGv_i32 read_fp_hreg(DisasContext *s, int reg) +{ + TCGv_i32 v =3D tcg_temp_new_i32(); + + tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16)); + return v; +} + /* Clear the bits above an N-bit vector, for N =3D (is_q ? 128 : 64). * If SVE is not enabled, then there are only 128 bits in the vector. */ @@ -4644,11 +4652,9 @@ static void disas_fp_csel(DisasContext *s, uint32_t = insn) static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int r= n) { TCGv_ptr fpst =3D NULL; - TCGv_i32 tcg_op =3D tcg_temp_new_i32(); + TCGv_i32 tcg_op =3D read_fp_hreg(s, rn); TCGv_i32 tcg_res =3D tcg_temp_new_i32(); =20 - read_vec_element_i32(s, tcg_op, rn, 0, MO_16); - switch (opcode) { case 0x0: /* FMOV */ tcg_gen_mov_i32(tcg_res, tcg_op); @@ -7543,13 +7549,10 @@ static void disas_simd_scalar_three_reg_diff(DisasC= ontext *s, uint32_t insn) tcg_temp_free_i64(tcg_op2); tcg_temp_free_i64(tcg_res); } else { - TCGv_i32 tcg_op1 =3D tcg_temp_new_i32(); - TCGv_i32 tcg_op2 =3D tcg_temp_new_i32(); + TCGv_i32 tcg_op1 =3D read_fp_hreg(s, rn); + TCGv_i32 tcg_op2 =3D read_fp_hreg(s, rm); TCGv_i64 tcg_res =3D tcg_temp_new_i64(); =20 - read_vec_element_i32(s, tcg_op1, rn, 0, MO_16); - read_vec_element_i32(s, tcg_op2, rm, 0, MO_16); - gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2); gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_r= es); =20 @@ -8090,13 +8093,10 @@ static void disas_simd_scalar_three_reg_same_fp16(D= isasContext *s, =20 fpst =3D get_fpstatus_ptr(true); =20 - tcg_op1 =3D tcg_temp_new_i32(); - tcg_op2 =3D tcg_temp_new_i32(); + tcg_op1 =3D read_fp_hreg(s, rn); + tcg_op2 =3D read_fp_hreg(s, rm); tcg_res =3D tcg_temp_new_i32(); =20 - read_vec_element_i32(s, tcg_op1, rn, 0, MO_16); - read_vec_element_i32(s, tcg_op2, rm, 0, MO_16); - switch (fpopcode) { case 0x03: /* FMULX */ gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst); @@ -12015,11 +12015,9 @@ static void disas_simd_two_reg_misc_fp16(DisasCont= ext *s, uint32_t insn) } =20 if (is_scalar) { - TCGv_i32 tcg_op =3D tcg_temp_new_i32(); + TCGv_i32 tcg_op =3D read_fp_hreg(s, rn); TCGv_i32 tcg_res =3D tcg_temp_new_i32(); =20 - read_vec_element_i32(s, tcg_op, rn, 0, MO_16); - switch (fpop) { case 0x1a: /* FCVTNS */ case 0x1b: /* FCVTMS */ --=20 2.14.3