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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id 65sm26170145pft.74.2018.05.02.15.15.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 02 May 2018 15:15:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/7Is7JNJJAWMsuntBwVi2s5wQjfXgdNNCqqq9DMfcWs=; b=Dib89hnSudeq1lR9lqlhhXVKPx83azCNoCDwFPf98GK0UNgQ4Z4+VHEHoiLeY998kt +J8QsjiEzPL9mxKpSYN7RU46lzMn0Nkg453QDOZmLE6p2ktdHzgxJfECBZKzkmxjItpw AVu2WPLKgJP9XRyND5hUxRsU9Tr9MBYtnC5/U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/7Is7JNJJAWMsuntBwVi2s5wQjfXgdNNCqqq9DMfcWs=; b=JVvKmcDab4v5hIMzoz92yd+CBY+HehhUUkZAa2cE0x8AhKk7zz4e9FDmWXtNuuZqdv 1kNDF0nhSHHOJ/kKigH/O1XI1oTM7fuX8jqVj8qgnzknrhozyIvN9Kn0i/Jy7qz6ijxd /vtQkaPWxTEiMu8lHTHcGMtC8RdRY+d/wwB6/zX4uNxmjfLunTiIJvB9luJGcdakKXpl HBBYMW3DMa69dj8VopVG5/iYb8X+o7pHrQmh1mJHunVOsiIOEzeY5SpnOyXumEnytfKU ilpxIG8rsKV8mmqg6GdaPhPLnhmzbiDmBQGfZX0ztkdd8uF4143TH4XDxyVYIMm5FF7i 9PmQ== X-Gm-Message-State: ALQs6tD1WSjSqa/qiMAjLK98mHOgm38ivEP1MgsQNkY6O/TmbfQtgrNB o5O2UEqO0PiGJ3b/FBcxnSJHUBZ3BBU= X-Google-Smtp-Source: AB8JxZoVnVObeH7a+NjdecAP2p98ZF7FnLijmyoF1aUwfam4L/7QVQWpYoVBVGe2cwloQiXeMdSX1w== X-Received: by 2002:a65:6117:: with SMTP id z23-v6mr17103294pgu.72.1525299357362; Wed, 02 May 2018 15:15:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 2 May 2018 15:15:40 -0700 Message-Id: <20180502221552.3873-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180502221552.3873-1-richard.henderson@linaro.org> References: <20180502221552.3873-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v2 02/14] target/arm: Implement vector shifted FCVT for fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" While we have some of the scalar paths for FCVT for fp16, we failed to decode the fp16 version of these instructions. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v2: Use parens with (x << y) >> z. --- target/arm/translate-a64.c | 65 ++++++++++++++++++++++++++++++++----------= ---- 1 file changed, 46 insertions(+), 19 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 68ca445691..a64673575a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -7208,19 +7208,28 @@ static void handle_simd_shift_fpint_conv(DisasConte= xt *s, bool is_scalar, bool is_q, bool is_u, int immh, int immb, int rn, int r= d) { - bool is_double =3D extract32(immh, 3, 1); int immhb =3D immh << 3 | immb; - int fracbits =3D (is_double ? 128 : 64) - immhb; - int pass; + int pass, size, fracbits; TCGv_ptr tcg_fpstatus; TCGv_i32 tcg_rmode, tcg_shift; =20 - if (!extract32(immh, 2, 2)) { - unallocated_encoding(s); - return; - } - - if (!is_scalar && !is_q && is_double) { + if (immh & 0x8) { + size =3D MO_64; + if (!is_scalar && !is_q) { + unallocated_encoding(s); + return; + } + } else if (immh & 0x4) { + size =3D MO_32; + } else if (immh & 0x2) { + size =3D MO_16; + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + unallocated_encoding(s); + return; + } + } else { + /* Should have split out AdvSIMD modified immediate earlier. */ + assert(immh =3D=3D 1); unallocated_encoding(s); return; } @@ -7232,11 +7241,12 @@ static void handle_simd_shift_fpint_conv(DisasConte= xt *s, bool is_scalar, assert(!(is_scalar && is_q)); =20 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO)); - tcg_fpstatus =3D get_fpstatus_ptr(false); + tcg_fpstatus =3D get_fpstatus_ptr(size =3D=3D MO_16); gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); + fracbits =3D (16 << size) - immhb; tcg_shift =3D tcg_const_i32(fracbits); =20 - if (is_double) { + if (size =3D=3D MO_64) { int maxpass =3D is_scalar ? 1 : 2; =20 for (pass =3D 0; pass < maxpass; pass++) { @@ -7253,20 +7263,37 @@ static void handle_simd_shift_fpint_conv(DisasConte= xt *s, bool is_scalar, } clear_vec_high(s, is_q, rd); } else { - int maxpass =3D is_scalar ? 1 : is_q ? 4 : 2; + void (*fn)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); + int maxpass =3D is_scalar ? 1 : ((8 << is_q) >> size); + + switch (size) { + case MO_16: + if (is_u) { + fn =3D gen_helper_vfp_toulh; + } else { + fn =3D gen_helper_vfp_toslh; + } + break; + case MO_32: + if (is_u) { + fn =3D gen_helper_vfp_touls; + } else { + fn =3D gen_helper_vfp_tosls; + } + break; + default: + g_assert_not_reached(); + } + for (pass =3D 0; pass < maxpass; pass++) { TCGv_i32 tcg_op =3D tcg_temp_new_i32(); =20 - read_vec_element_i32(s, tcg_op, rn, pass, MO_32); - if (is_u) { - gen_helper_vfp_touls(tcg_op, tcg_op, tcg_shift, tcg_fpstat= us); - } else { - gen_helper_vfp_tosls(tcg_op, tcg_op, tcg_shift, tcg_fpstat= us); - } + read_vec_element_i32(s, tcg_op, rn, pass, size); + fn(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); if (is_scalar) { write_fp_sreg(s, rd, tcg_op); } else { - write_vec_element_i32(s, tcg_op, rd, pass, MO_32); + write_vec_element_i32(s, tcg_op, rd, pass, size); } tcg_temp_free_i32(tcg_op); } --=20 2.14.3