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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id 65sm26170145pft.74.2018.05.02.15.16.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 02 May 2018 15:16:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Qjy5KDciNnwaKwZSWdv3Ve9BMVD2CqGha4QSuIzajro=; b=Foz0SZTsRtXezzTitqGfd9EvbKbbstdiZ/GqNJAnnM3NTm/IYL0dETN5Hm0AAb+0Wt HgUooCugVqokRG0/YveMbEQhmiPANlSUXPeP7YbI+0LHKuZTvb9rUTTzq7kkagnFIi7l dNDe9Seqm2p9UPwJ7n6jaTOXcmxAvMYbCsCBM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Qjy5KDciNnwaKwZSWdv3Ve9BMVD2CqGha4QSuIzajro=; b=BuylXYnxEHWcvovNiES41uHnoq5y514gLi219LCq3NDOXwTkiW7zFKnryer5yGjn+d oYlvljf9el8gACwJ/fV+kZI009egXswRBvg2rsIDlZ1YjxXYX/LdBVqoxOWG7cx0pmnk fFbARAtfczH9n89lWnjrYGlsPil3+jPT+DPg+Ks+ePCDM+2V0qQvJYva6ep6pXPcrxah 5iaE6jRIGbMTIZ3bEG9odnwQynsMSY21dp6qWYjdp89bXEWHccvfI2UiohEs9pPkH9Ci G1i7d9IRM5wdWnFo+w6Igc5hOrUxiivYyDN7t+rbfdYJR501JlM5TcEsnSbYawPPlDoC UOlA== X-Gm-Message-State: ALQs6tC94Ms0Y33m8UrMly8kQ4/bSM308Ar5/z5RP/jnSzRou9m19jT6 eL79o5owUPVzKG+xN8ndPrcKLH1Q2Ok= X-Google-Smtp-Source: AB8JxZqNaJ0DtwmvV5wJPEUnvH8XLKYzXZ10C8uaMghiNk8FiNsKXj4HBFygmKsGgGxpfituCanYMw== X-Received: by 2002:a65:4e03:: with SMTP id r3-v6mr17674540pgt.121.1525299370415; Wed, 02 May 2018 15:16:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 2 May 2018 15:15:50 -0700 Message-Id: <20180502221552.3873-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180502221552.3873-1-richard.henderson@linaro.org> References: <20180502221552.3873-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v2 12/14] target/arm: Implement FCSEL for fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Alex Benn=C3=A9e These were missed out from the rest of the half-precision work. Cc: qemu-stable@nongnu.org Signed-off-by: Alex Benn=C3=A9e [rth: Fix erroneous check vs type] Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-a64.c | 31 +++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f0aca20771..1ea5185f14 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4666,15 +4666,34 @@ static void disas_fp_csel(DisasContext *s, uint32_t= insn) unsigned int mos, type, rm, cond, rn, rd; TCGv_i64 t_true, t_false, t_zero; DisasCompare64 c; + TCGMemOp sz; =20 mos =3D extract32(insn, 29, 3); - type =3D extract32(insn, 22, 2); /* 0 =3D single, 1 =3D double */ + type =3D extract32(insn, 22, 2); rm =3D extract32(insn, 16, 5); cond =3D extract32(insn, 12, 4); rn =3D extract32(insn, 5, 5); rd =3D extract32(insn, 0, 5); =20 - if (mos || type > 1) { + if (mos) { + unallocated_encoding(s); + return; + } + + switch(type) { + case 0: + sz =3D MO_32; + break; + case 1: + sz =3D MO_64; + break; + case 3: + sz =3D MO_16; + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + break; + } + /* fallthru */ + default: unallocated_encoding(s); return; } @@ -4683,11 +4702,11 @@ static void disas_fp_csel(DisasContext *s, uint32_t= insn) return; } =20 - /* Zero extend sreg inputs to 64 bits now. */ + /* Zero extend sreg & hreg inputs to 64 bits now. */ t_true =3D tcg_temp_new_i64(); t_false =3D tcg_temp_new_i64(); - read_vec_element(s, t_true, rn, 0, type ? MO_64 : MO_32); - read_vec_element(s, t_false, rm, 0, type ? MO_64 : MO_32); + read_vec_element(s, t_true, rn, 0, sz); + read_vec_element(s, t_false, rm, 0, sz); =20 a64_test_cc(&c, cond); t_zero =3D tcg_const_i64(0); @@ -4696,7 +4715,7 @@ static void disas_fp_csel(DisasContext *s, uint32_t i= nsn) tcg_temp_free_i64(t_false); a64_free_cc(&c); =20 - /* Note that sregs write back zeros to the high bits, + /* Note that sregs & hregs write back zeros to the high bits, and we've already done the zero-extension. */ write_fp_dreg(s, rd, t_true); tcg_temp_free_i64(t_true); --=20 2.14.3