From nobody Wed Oct 29 11:33:38 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1525165743771465.4315722655248; Tue, 1 May 2018 02:09:03 -0700 (PDT) Received: from localhost ([::1]:36741 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fDRHT-0001Zs-0M for importer@patchew.org; Tue, 01 May 2018 05:09:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46138) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fDR8X-0003Wu-41 for qemu-devel@nongnu.org; Tue, 01 May 2018 04:59:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fDR8V-0007rm-Os for qemu-devel@nongnu.org; Tue, 01 May 2018 04:59:49 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:41356) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fDR8V-0007mW-Gq for qemu-devel@nongnu.org; Tue, 01 May 2018 04:59:47 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fDR8P-0007M3-VR; Tue, 01 May 2018 09:59:41 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 1 May 2018 09:59:29 +0100 Message-Id: <20180501085939.6201-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180501085939.6201-1-peter.maydell@linaro.org> References: <20180501085939.6201-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [RFC PATCH v2 02/12] Make address_space_translate() take a MemTxAttrs argument X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Eric Auger , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" As part of plumbing MemTxAttrs down to the IOMMU translate method, add MemTxAttrs as an argument to address_space_translate(). Its callers either have an attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED. Signed-off-by: Peter Maydell --- include/exec/memory.h | 4 +++- accel/tcg/translate-all.c | 2 +- exec.c | 6 ++++-- hw/vfio/common.c | 3 ++- memory_ldst.inc.c | 18 +++++++++--------- target/riscv/helper.c | 2 +- 6 files changed, 20 insertions(+), 15 deletions(-) diff --git a/include/exec/memory.h b/include/exec/memory.h index e62965a0c8..f416d1e985 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -1909,6 +1909,7 @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSp= ace *as, hwaddr addr, * #MemoryRegion. * @len: pointer to length * @is_write: indicates the transfer direction + * @attrs: memory attributes */ MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat, @@ -1916,7 +1917,8 @@ MemoryRegion *flatview_translate(FlatView *fv, =20 static inline MemoryRegion *address_space_translate(AddressSpace *as, hwaddr addr, hwaddr *x= lat, - hwaddr *len, bool is_w= rite) + hwaddr *len, bool is_w= rite, + MemTxAttrs attrs) { return flatview_translate(address_space_to_flatview(as), addr, xlat, len, is_write); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index f04a922ef7..52f7bd59a9 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1679,7 +1679,7 @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr= addr, MemTxAttrs attrs) hwaddr l =3D 1; =20 rcu_read_lock(); - mr =3D address_space_translate(as, addr, &addr, &l, false); + mr =3D address_space_translate(as, addr, &addr, &l, false, attrs); if (!(memory_region_is_ram(mr) || memory_region_is_romd(mr))) { rcu_read_unlock(); diff --git a/exec.c b/exec.c index df35e6dd85..a0f27b7b8c 100644 --- a/exec.c +++ b/exec.c @@ -3287,7 +3287,8 @@ static inline void cpu_physical_memory_write_rom_inte= rnal(AddressSpace *as, rcu_read_lock(); while (len > 0) { l =3D len; - mr =3D address_space_translate(as, addr, &addr1, &l, true); + mr =3D address_space_translate(as, addr, &addr1, &l, true, + MEMTXATTRS_UNSPECIFIED); =20 if (!(memory_region_is_ram(mr) || memory_region_is_romd(mr))) { @@ -3716,7 +3717,8 @@ bool cpu_physical_memory_is_io(hwaddr phys_addr) =20 rcu_read_lock(); mr =3D address_space_translate(&address_space_memory, - phys_addr, &phys_addr, &l, false); + phys_addr, &phys_addr, &l, false, + MEMTXATTRS_UNSPECIFIED); =20 res =3D !(memory_region_is_ram(mr) || memory_region_is_romd(mr)); rcu_read_unlock(); diff --git a/hw/vfio/common.c b/hw/vfio/common.c index 07ffa0ba10..8e57265edf 100644 --- a/hw/vfio/common.c +++ b/hw/vfio/common.c @@ -324,7 +324,8 @@ static bool vfio_get_vaddr(IOMMUTLBEntry *iotlb, void *= *vaddr, */ mr =3D address_space_translate(&address_space_memory, iotlb->translated_addr, - &xlat, &len, writable); + &xlat, &len, writable, + MEMTXATTRS_UNSPECIFIED); if (!memory_region_is_ram(mr)) { error_report("iommu map to non memory area %"HWADDR_PRIx"", xlat); diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c index 5dbff9cef8..860ba31ac8 100644 --- a/memory_ldst.inc.c +++ b/memory_ldst.inc.c @@ -33,7 +33,7 @@ static inline uint32_t glue(address_space_ldl_internal, S= UFFIX)(ARG1_DECL, bool release_lock =3D false; =20 RCU_READ_LOCK(); - mr =3D TRANSLATE(addr, &addr1, &l, false); + mr =3D TRANSLATE(addr, &addr1, &l, false, attrs); if (l < 4 || !IS_DIRECT(mr, false)) { release_lock |=3D prepare_mmio_access(mr); =20 @@ -127,7 +127,7 @@ static inline uint64_t glue(address_space_ldq_internal,= SUFFIX)(ARG1_DECL, bool release_lock =3D false; =20 RCU_READ_LOCK(); - mr =3D TRANSLATE(addr, &addr1, &l, false); + mr =3D TRANSLATE(addr, &addr1, &l, false, attrs); if (l < 8 || !IS_DIRECT(mr, false)) { release_lock |=3D prepare_mmio_access(mr); =20 @@ -219,7 +219,7 @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL, bool release_lock =3D false; =20 RCU_READ_LOCK(); - mr =3D TRANSLATE(addr, &addr1, &l, false); + mr =3D TRANSLATE(addr, &addr1, &l, false, attrs); if (!IS_DIRECT(mr, false)) { release_lock |=3D prepare_mmio_access(mr); =20 @@ -261,7 +261,7 @@ static inline uint32_t glue(address_space_lduw_internal= , SUFFIX)(ARG1_DECL, bool release_lock =3D false; =20 RCU_READ_LOCK(); - mr =3D TRANSLATE(addr, &addr1, &l, false); + mr =3D TRANSLATE(addr, &addr1, &l, false, attrs); if (l < 2 || !IS_DIRECT(mr, false)) { release_lock |=3D prepare_mmio_access(mr); =20 @@ -356,7 +356,7 @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL, bool release_lock =3D false; =20 RCU_READ_LOCK(); - mr =3D TRANSLATE(addr, &addr1, &l, true); + mr =3D TRANSLATE(addr, &addr1, &l, true, attrs); if (l < 4 || !IS_DIRECT(mr, true)) { release_lock |=3D prepare_mmio_access(mr); =20 @@ -399,7 +399,7 @@ static inline void glue(address_space_stl_internal, SUF= FIX)(ARG1_DECL, bool release_lock =3D false; =20 RCU_READ_LOCK(); - mr =3D TRANSLATE(addr, &addr1, &l, true); + mr =3D TRANSLATE(addr, &addr1, &l, true, attrs); if (l < 4 || !IS_DIRECT(mr, true)) { release_lock |=3D prepare_mmio_access(mr); =20 @@ -489,7 +489,7 @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL, bool release_lock =3D false; =20 RCU_READ_LOCK(); - mr =3D TRANSLATE(addr, &addr1, &l, true); + mr =3D TRANSLATE(addr, &addr1, &l, true, attrs); if (!IS_DIRECT(mr, true)) { release_lock |=3D prepare_mmio_access(mr); r =3D memory_region_dispatch_write(mr, addr1, val, 1, attrs); @@ -528,7 +528,7 @@ static inline void glue(address_space_stw_internal, SUF= FIX)(ARG1_DECL, bool release_lock =3D false; =20 RCU_READ_LOCK(); - mr =3D TRANSLATE(addr, &addr1, &l, true); + mr =3D TRANSLATE(addr, &addr1, &l, true, attrs); if (l < 2 || !IS_DIRECT(mr, true)) { release_lock |=3D prepare_mmio_access(mr); =20 @@ -619,7 +619,7 @@ static void glue(address_space_stq_internal, SUFFIX)(AR= G1_DECL, bool release_lock =3D false; =20 RCU_READ_LOCK(); - mr =3D TRANSLATE(addr, &addr1, &l, true); + mr =3D TRANSLATE(addr, &addr1, &l, true, attrs); if (l < 8 || !IS_DIRECT(mr, true)) { release_lock |=3D prepare_mmio_access(mr); =20 diff --git a/target/riscv/helper.c b/target/riscv/helper.c index 02cbcea2b7..d7023ad78e 100644 --- a/target/riscv/helper.c +++ b/target/riscv/helper.c @@ -210,7 +210,7 @@ restart: MemoryRegion *mr; hwaddr l =3D sizeof(target_ulong), addr1; mr =3D address_space_translate(cs->as, pte_addr, - &addr1, &l, false); + &addr1, &l, false, MEMTXATTRS_UNSPECIFIED); if (memory_access_is_direct(mr, true)) { target_ulong *pte_pa =3D qemu_map_ram_ptr(mr->ram_block, addr1); --=20 2.17.0