From nobody Wed Oct 29 17:31:56 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1524823303445899.3692136093814; Fri, 27 Apr 2018 03:01:43 -0700 (PDT) Received: from localhost ([::1]:46920 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fC0CA-0004XL-Cz for importer@patchew.org; Fri, 27 Apr 2018 06:01:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60053) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBzaj-0002PP-7I for qemu-devel@nongnu.org; Fri, 27 Apr 2018 05:22:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fBzah-0002PV-BI for qemu-devel@nongnu.org; Fri, 27 Apr 2018 05:22:57 -0400 Received: from ozlabs.org ([203.11.71.1]:41443) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fBzag-0002Nl-N9; Fri, 27 Apr 2018 05:22:55 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 40XT2w5tqJz9sXw; Fri, 27 Apr 2018 19:21:41 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1524820904; bh=YPKdGyEUDeEtpAFDlu0M3wOsHnF+N4Wx/DaWc8mFjNk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CzM5roh/XJ9/QSgyZH4UYwz8vfLG3woDDsLqLvbkkYf2MMqV+TX51O2TnWOr90uoJ UrKxeKBU9+c8JLl4JvRwynO8D0u+IE93EapcZrq0HoADbEDteCbyWDabcYc+wghj3n acPjDxgLVdOmDXxKuUEu3PTQq701WQ7H0HmPgah4= From: David Gibson To: peter.maydell@linaro.org Date: Fri, 27 Apr 2018 19:21:20 +1000 Message-Id: <20180427092126.24812-44-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180427092126.24812-1-david@gibson.dropbear.id.au> References: <20180427092126.24812-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 43/49] target/ppc: Fold slb_nr into PPCHash64Options X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Gibson , qemu-ppc@nongnu.org, groug@kaod.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The env->slb_nr field gives the size of the SLB (Segment Lookaside Buffer). This is another static-after-initialization parameter of the specific version of the 64-bit hash MMU in the CPU. So, this patch folds the field into PPCHash64Options with the other hash MMU options. This is a bit more complicated that the things previously put in there, because slb_nr was foolishly included in the migration stream. So we need some of the usual dance to handle backwards compatible migration. Signed-off-by: David Gibson Reviewed-by: Greg Kurz --- hw/ppc/pnv.c | 2 +- hw/ppc/spapr.c | 11 ++++++++--- target/ppc/cpu.h | 3 ++- target/ppc/kvm.c | 2 +- target/ppc/machine.c | 23 ++++++++++++++++++++--- target/ppc/mmu-hash64.c | 15 +++++++++------ target/ppc/mmu-hash64.h | 1 + target/ppc/translate_init.c | 17 ++--------------- 8 files changed, 44 insertions(+), 30 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 0e49c5e9b8..0314881316 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -180,7 +180,7 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, voi= d *fdt) =20 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); - _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); + _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->= slb_size))); _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); =20 diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index abf38c62e8..8c2e3ccb89 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -547,8 +547,8 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *f= dt, int offset, =20 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); - _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); - _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); + _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_= size))); + _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->= slb_size))); _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); =20 @@ -3958,7 +3958,12 @@ DEFINE_SPAPR_MACHINE(2_13, "2.13", true); * pseries-2.12 */ #define SPAPR_COMPAT_2_12 \ - HW_COMPAT_2_12 + HW_COMPAT_2_12 \ + { \ + .driver =3D TYPE_POWERPC_CPU, \ + .property =3D "pre-2.13-migration", \ + .value =3D "on", \ + }, =20 static void spapr_machine_2_12_instance_options(MachineState *machine) { diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index c0c44fb91d..8c9e03f54d 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1025,7 +1025,6 @@ struct CPUPPCState { #if defined(TARGET_PPC64) /* PowerPC 64 SLB area */ ppc_slb_t slb[MAX_SLB_ENTRIES]; - int32_t slb_nr; /* tcg TLB needs flush (deferred slb inval instruction typically) */ #endif /* segment registers */ @@ -1216,6 +1215,8 @@ struct PowerPCCPU { uint64_t mig_insns_flags2; uint32_t mig_nb_BATs; bool pre_2_10_migration; + bool pre_2_13_migration; + int32_t mig_slb_nr; }; =20 static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env) diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 246b9eab2a..6de59c5b21 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -484,7 +484,7 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu) break; } } - env->slb_nr =3D smmu_info.slb_size; + cpu->hash64_opts->slb_size =3D smmu_info.slb_size; if (!(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) { cpu->hash64_opts->flags &=3D ~PPC_HASH64_1TSEG; } diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 0634cdb295..3d6434a006 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -18,6 +18,9 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int ve= rsion_id) unsigned int i, j; target_ulong sdr1; uint32_t fpscr; +#if defined(TARGET_PPC64) + int32_t slb_nr; +#endif target_ulong xer; =20 for (i =3D 0; i < 32; i++) @@ -49,7 +52,7 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int ve= rsion_id) qemu_get_sbe32s(f, &env->access_type); #if defined(TARGET_PPC64) qemu_get_betls(f, &env->spr[SPR_ASR]); - qemu_get_sbe32s(f, &env->slb_nr); + qemu_get_sbe32s(f, &slb_nr); #endif qemu_get_betls(f, &sdr1); for (i =3D 0; i < 32; i++) @@ -146,6 +149,15 @@ static bool cpu_pre_2_8_migration(void *opaque, int ve= rsion_id) return cpu->pre_2_8_migration; } =20 +#if defined(TARGET_PPC64) +static bool cpu_pre_2_13_migration(void *opaque, int version_id) +{ + PowerPCCPU *cpu =3D opaque; + + return cpu->pre_2_13_migration; +} +#endif + static int cpu_pre_save(void *opaque) { PowerPCCPU *cpu =3D opaque; @@ -203,6 +215,11 @@ static int cpu_pre_save(void *opaque) cpu->mig_insns_flags2 =3D env->insns_flags2 & insns_compat_mask2; cpu->mig_nb_BATs =3D env->nb_BATs; } + if (cpu->pre_2_13_migration) { + if (cpu->hash64_opts) { + cpu->mig_slb_nr =3D cpu->hash64_opts->slb_size; + } + } =20 return 0; } @@ -478,7 +495,7 @@ static int slb_post_load(void *opaque, int version_id) =20 /* We've pulled in the raw esid and vsid values from the migration * stream, but we need to recompute the page size pointers */ - for (i =3D 0; i < env->slb_nr; i++) { + for (i =3D 0; i < cpu->hash64_opts->slb_size; i++) { if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0)= { /* Migration source had bad values in its SLB */ return -1; @@ -495,7 +512,7 @@ static const VMStateDescription vmstate_slb =3D { .needed =3D slb_needed, .post_load =3D slb_post_load, .fields =3D (VMStateField[]) { - VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU, NULL), + VMSTATE_INT32_TEST(mig_slb_nr, PowerPCCPU, cpu_pre_2_13_migration), VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES), VMSTATE_END_OF_LIST() } diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index a5570c8774..7e0adecfd9 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -52,7 +52,7 @@ static ppc_slb_t *slb_lookup(PowerPCCPU *cpu, target_ulon= g eaddr) esid_256M =3D (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V; esid_1T =3D (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V; =20 - for (n =3D 0; n < env->slb_nr; n++) { + for (n =3D 0; n < cpu->hash64_opts->slb_size; n++) { ppc_slb_t *slb =3D &env->slb[n]; =20 LOG_SLB("%s: slot %d %016" PRIx64 " %016" @@ -80,7 +80,7 @@ void dump_slb(FILE *f, fprintf_function cpu_fprintf, Powe= rPCCPU *cpu) cpu_synchronize_state(CPU(cpu)); =20 cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n"); - for (i =3D 0; i < env->slb_nr; i++) { + for (i =3D 0; i < cpu->hash64_opts->slb_size; i++) { slbe =3D env->slb[i].esid; slbv =3D env->slb[i].vsid; if (slbe =3D=3D 0 && slbv =3D=3D 0) { @@ -93,10 +93,11 @@ void dump_slb(FILE *f, fprintf_function cpu_fprintf, Po= werPCCPU *cpu) =20 void helper_slbia(CPUPPCState *env) { + PowerPCCPU *cpu =3D ppc_env_get_cpu(env); int n; =20 /* XXX: Warning: slbia never invalidates the first segment */ - for (n =3D 1; n < env->slb_nr; n++) { + for (n =3D 1; n < cpu->hash64_opts->slb_size; n++) { ppc_slb_t *slb =3D &env->slb[n]; =20 if (slb->esid & SLB_ESID_V) { @@ -151,7 +152,7 @@ int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, const PPCHash64SegmentPageSizes *sps =3D NULL; int i; =20 - if (slot >=3D env->slb_nr) { + if (slot >=3D cpu->hash64_opts->slb_size) { return -1; /* Bad slot number */ } if (esid & ~(SLB_ESID_ESID | SLB_ESID_V)) { @@ -202,7 +203,7 @@ static int ppc_load_slb_esid(PowerPCCPU *cpu, target_ul= ong rb, int slot =3D rb & 0xfff; ppc_slb_t *slb =3D &env->slb[slot]; =20 - if (slot >=3D env->slb_nr) { + if (slot >=3D cpu->hash64_opts->slb_size) { return -1; } =20 @@ -217,7 +218,7 @@ static int ppc_load_slb_vsid(PowerPCCPU *cpu, target_ul= ong rb, int slot =3D rb & 0xfff; ppc_slb_t *slb =3D &env->slb[slot]; =20 - if (slot >=3D env->slb_nr) { + if (slot >=3D cpu->hash64_opts->slb_size) { return -1; } =20 @@ -1115,6 +1116,7 @@ void ppc_hash64_finalize(PowerPCCPU *cpu) =20 const PPCHash64Options ppc_hash64_opts_basic =3D { .flags =3D 0, + .slb_size =3D 64, .sps =3D { { .page_shift =3D 12, /* 4K */ .slb_enc =3D 0, @@ -1129,6 +1131,7 @@ const PPCHash64Options ppc_hash64_opts_basic =3D { =20 const PPCHash64Options ppc_hash64_opts_POWER7 =3D { .flags =3D PPC_HASH64_1TSEG | PPC_HASH64_AMR | PPC_HASH64_CI_LARGEPAGE, + .slb_size =3D 32, .sps =3D { { .page_shift =3D 12, /* 4K */ diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h index f1babb0afc..d5fc03441d 100644 --- a/target/ppc/mmu-hash64.h +++ b/target/ppc/mmu-hash64.h @@ -157,6 +157,7 @@ struct PPCHash64Options { #define PPC_HASH64_AMR 0x00002 #define PPC_HASH64_CI_LARGEPAGE 0x00004 unsigned flags; + unsigned slb_size; PPCHash64SegmentPageSizes sps[PPC_PAGE_SIZES_MAX_SZ]; }; =20 diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index a925cf5cd3..bb79d23b50 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -8195,9 +8195,6 @@ static void init_proc_970(CPUPPCState *env) gen_spr_970_dbg(env); =20 /* env variables */ -#if !defined(CONFIG_USER_ONLY) - env->slb_nr =3D 64; -#endif env->dcache_line_size =3D 128; env->icache_line_size =3D 128; =20 @@ -8272,9 +8269,6 @@ static void init_proc_power5plus(CPUPPCState *env) gen_spr_power5p_ear(env); =20 /* env variables */ -#if !defined(CONFIG_USER_ONLY) - env->slb_nr =3D 64; -#endif env->dcache_line_size =3D 128; env->icache_line_size =3D 128; =20 @@ -8389,9 +8383,6 @@ static void init_proc_POWER7(CPUPPCState *env) gen_spr_power7_book4(env); =20 /* env variables */ -#if !defined(CONFIG_USER_ONLY) - env->slb_nr =3D 32; -#endif env->dcache_line_size =3D 128; env->icache_line_size =3D 128; =20 @@ -8543,9 +8534,6 @@ static void init_proc_POWER8(CPUPPCState *env) gen_spr_power8_rpr(env); =20 /* env variables */ -#if !defined(CONFIG_USER_ONLY) - env->slb_nr =3D 32; -#endif env->dcache_line_size =3D 128; env->icache_line_size =3D 128; =20 @@ -8743,9 +8731,6 @@ static void init_proc_POWER9(CPUPPCState *env) KVM_REG_PPC_PSSCR, 0); =20 /* env variables */ -#if !defined(CONFIG_USER_ONLY) - env->slb_nr =3D 32; -#endif env->dcache_line_size =3D 128; env->icache_line_size =3D 128; =20 @@ -10486,6 +10471,8 @@ static Property ppc_cpu_properties[] =3D { DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, f= alse), DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration, false), + DEFINE_PROP_BOOL("pre-2.13-migration", PowerPCCPU, pre_2_13_migration, + false), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.14.3