From nobody Wed Oct 29 09:27:13 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1524822258043363.4148879913721; Fri, 27 Apr 2018 02:44:18 -0700 (PDT) Received: from localhost ([::1]:46798 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBzvK-0004Vc-5z for importer@patchew.org; Fri, 27 Apr 2018 05:44:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59502) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBzaB-0001nU-Fw for qemu-devel@nongnu.org; Fri, 27 Apr 2018 05:22:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fBza9-00027v-SJ for qemu-devel@nongnu.org; Fri, 27 Apr 2018 05:22:23 -0400 Received: from ozlabs.org ([203.11.71.1]:52693) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fBza9-00027H-7X; Fri, 27 Apr 2018 05:22:21 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 40XT2r2cFmz9s70; Fri, 27 Apr 2018 19:21:39 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1524820900; bh=SHXsnX2GsMQGMQVUBC16fqTbts0TRTpOBTiyC2gDc6o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CyET3h7d/3a9U+qZE3hNsDKm0m/YVHtTTKBJbronjXNs64MAhXmzuWZmSud+f912Q 0gtIbcR2DDOmegR79sSF15Jar8NAEN1q9FHhzlJLiKGhxw6p8Vls5itK0YSkN/wnXF edmh5BOW0gek8VGFAV5kY5y6Hznr4V0t9DQ2k7zY= From: David Gibson To: peter.maydell@linaro.org Date: Fri, 27 Apr 2018 19:21:16 +1000 Message-Id: <20180427092126.24812-40-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180427092126.24812-1-david@gibson.dropbear.id.au> References: <20180427092126.24812-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 39/49] target/ppc: Move 1T segment and AMR options to PPCHash64Options X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Gibson , qemu-ppc@nongnu.org, groug@kaod.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Currently env->mmu_model is a bit of an unholy mess of an enum of distinct MMU types, with various flag bits as well. This makes which bits of the field should be compared pretty confusing. Make a start on cleaning that up by moving two of the flags bits - POWERPC_MMU_1TSEG and POWERPC_MMU_AMR - which are specific to the 64-bit hash MMU into a new flags field in PPCHash64Options structure. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Greg Kurz --- hw/ppc/pnv.c | 3 ++- hw/ppc/spapr.c | 2 +- target/ppc/cpu-qom.h | 11 +++-------- target/ppc/kvm.c | 4 ++-- target/ppc/mmu-hash64.c | 6 ++++-- target/ppc/mmu-hash64.h | 8 ++++++++ 6 files changed, 20 insertions(+), 14 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 3220ef8f79..0e49c5e9b8 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -36,6 +36,7 @@ #include "monitor/monitor.h" #include "hw/intc/intc.h" #include "hw/ipmi/ipmi.h" +#include "target/ppc/mmu-hash64.h" =20 #include "hw/ppc/xics.h" #include "hw/ppc/pnv_xscom.h" @@ -187,7 +188,7 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, voi= d *fdt) _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); } =20 - if (env->mmu_model & POWERPC_MMU_1TSEG) { + if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", segs, sizeof(segs)))); } diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index a4b3722656..9c26dc37e1 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -557,7 +557,7 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *f= dt, int offset, _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); } =20 - if (env->mmu_model & POWERPC_MMU_1TSEG) { + if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", segs, sizeof(segs)))); } diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 3e5ef7375f..2bd58b2a84 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -68,22 +68,17 @@ enum powerpc_mmu_t { /* PowerPC 601 MMU model (specific BATs format) */ POWERPC_MMU_601 =3D 0x0000000A, #define POWERPC_MMU_64 0x00010000 -#define POWERPC_MMU_1TSEG 0x00020000 -#define POWERPC_MMU_AMR 0x00040000 #define POWERPC_MMU_V3 0x00100000 /* ISA V3.00 MMU Support */ /* 64 bits PowerPC MMU */ POWERPC_MMU_64B =3D POWERPC_MMU_64 | 0x00000001, /* Architecture 2.03 and later (has LPCR) */ POWERPC_MMU_2_03 =3D POWERPC_MMU_64 | 0x00000002, /* Architecture 2.06 variant */ - POWERPC_MMU_2_06 =3D POWERPC_MMU_64 | POWERPC_MMU_1TSEG - | POWERPC_MMU_AMR | 0x00000003, + POWERPC_MMU_2_06 =3D POWERPC_MMU_64 | 0x00000003, /* Architecture 2.07 variant */ - POWERPC_MMU_2_07 =3D POWERPC_MMU_64 | POWERPC_MMU_1TSEG - | POWERPC_MMU_AMR | 0x00000004, + POWERPC_MMU_2_07 =3D POWERPC_MMU_64 | 0x00000004, /* Architecture 3.00 variant */ - POWERPC_MMU_3_00 =3D POWERPC_MMU_64 | POWERPC_MMU_1TSEG - | POWERPC_MMU_AMR | POWERPC_MMU_V3 + POWERPC_MMU_3_00 =3D POWERPC_MMU_64 | POWERPC_MMU_V3 | 0x00000005, }; #define POWERPC_MMU_VER(x) ((x) & (POWERPC_MMU_64 | 0xFFFF)) diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index c67254acca..b53af75ecf 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -302,7 +302,7 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu, /* HV KVM has backing store size restrictions */ info->flags =3D KVM_PPC_PAGE_SIZES_REAL; =20 - if (env->mmu_model & POWERPC_MMU_1TSEG) { + if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { info->flags |=3D KVM_PPC_1T_SEGMENTS; } =20 @@ -482,7 +482,7 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu) } env->slb_nr =3D smmu_info.slb_size; if (!(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) { - env->mmu_model &=3D ~POWERPC_MMU_1TSEG; + cpu->hash64_opts->flags &=3D ~PPC_HASH64_1TSEG; } } =20 diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 2809c31170..c9ee55e1ea 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -160,7 +160,7 @@ int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, if (vsid & (SLB_VSID_B & ~SLB_VSID_B_1T)) { return -1; /* Bad segment size */ } - if ((vsid & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) { + if ((vsid & SLB_VSID_B) && !(ppc_hash64_has(cpu, PPC_HASH64_1TSEG))) { return -1; /* 1T segment on MMU that doesn't support it */ } =20 @@ -369,7 +369,7 @@ static int ppc_hash64_amr_prot(PowerPCCPU *cpu, ppc_has= h_pte64_t pte) int prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; =20 /* Only recent MMUs implement Virtual Page Class Key Protection */ - if (!(env->mmu_model & POWERPC_MMU_AMR)) { + if (!ppc_hash64_has(cpu, PPC_HASH64_AMR)) { return prot; } =20 @@ -1114,6 +1114,7 @@ void ppc_hash64_finalize(PowerPCCPU *cpu) } =20 const PPCHash64Options ppc_hash64_opts_basic =3D { + .flags =3D 0, .sps =3D { { .page_shift =3D 12, /* 4K */ .slb_enc =3D 0, @@ -1127,6 +1128,7 @@ const PPCHash64Options ppc_hash64_opts_basic =3D { }; =20 const PPCHash64Options ppc_hash64_opts_POWER7 =3D { + .flags =3D PPC_HASH64_1TSEG | PPC_HASH64_AMR, .sps =3D { { .page_shift =3D 12, /* 4K */ diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h index 341c1524c2..b2b5d25238 100644 --- a/target/ppc/mmu-hash64.h +++ b/target/ppc/mmu-hash64.h @@ -153,12 +153,20 @@ struct PPCHash64SegmentPageSizes { }; =20 struct PPCHash64Options { +#define PPC_HASH64_1TSEG 0x00001 +#define PPC_HASH64_AMR 0x00002 + unsigned flags; PPCHash64SegmentPageSizes sps[PPC_PAGE_SIZES_MAX_SZ]; }; =20 extern const PPCHash64Options ppc_hash64_opts_basic; extern const PPCHash64Options ppc_hash64_opts_POWER7; =20 +static inline bool ppc_hash64_has(PowerPCCPU *cpu, unsigned feature) +{ + return !!(cpu->hash64_opts->flags & feature); +} + #endif /* CONFIG_USER_ONLY */ =20 #if defined(CONFIG_USER_ONLY) || !defined(TARGET_PPC64) --=20 2.14.3