From nobody Wed Oct 29 20:34:58 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1524790152687403.4670733939579; Thu, 26 Apr 2018 17:49:12 -0700 (PDT) Received: from localhost ([::1]:45222 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBrZM-0002ON-Ig for importer@patchew.org; Thu, 26 Apr 2018 20:49:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51633) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBrE9-0001xe-Tj for qemu-devel@nongnu.org; Thu, 26 Apr 2018 20:27:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fBrE8-0004Qo-Ts for qemu-devel@nongnu.org; Thu, 26 Apr 2018 20:27:05 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:38627) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fBrE8-0004Pn-PK for qemu-devel@nongnu.org; Thu, 26 Apr 2018 20:27:04 -0400 Received: by mail-pg0-x242.google.com with SMTP id n9-v6so150132pgq.5 for ; Thu, 26 Apr 2018 17:27:04 -0700 (PDT) Received: from cloudburst.twiddle.net.com ([2605:e000:112b:41da:c94c:5ee7:de92:7d78]) by smtp.gmail.com with ESMTPSA id g76sm86338pfj.102.2018.04.26.17.27.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 26 Apr 2018 17:27:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FcnQaKOY5FiYcN1YZAPz8IfJW4izctQEpJ8H6gTzcVU=; b=bPOys9K5bvbyeZ5Jm5EXU9ej0n7y4YpE61DBD2Hya2qVOFw3UfRqkuH5+aqeczPqoq 7vgfXPbvToFLBOyH7IbAT2IptIW/y9T49oPuWkYBajzPEVO8GfAFDDdf85onDkVo6Xcb evYXjWVaep2YA0SM50AUfzFUllwmSkvpA4O3Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FcnQaKOY5FiYcN1YZAPz8IfJW4izctQEpJ8H6gTzcVU=; b=qzfNDDGjEQl3JdwoQFd5TdNeNpV1EdUT1ODftgEC6dfcl+ZfqqmnYHu5H9j+qyZSPh Dxw7ezsZBclGPiAdpBl4C3LGn8BdvAl0XqZj92B9kW9Do9c6sN3kF6aa1DVFhqc4Bo00 Kh5lsqkJAcyPaCEpR0wA9wLaaQ0xFreATepvjg0Kaa5Pic8xbWGrs5CukewQG5YKk9um RL3szE5Knezc7Blx9zjdgz23RozmMlmOXK4PBcMIjN6m8Fpl+8snSpIGO1av+tIgjqKI iH4mRRK874jGQOflIxjw/fdgtQFVPfftD4KwBlm4u0TMMAmw2fpKLcTfT4WXjRduVPx8 TG8g== X-Gm-Message-State: ALQs6tAVJVoxm53oKCuk5jJ86jafcbLkajjTuh04hLNhbGmgLRJTHwsi /qDgyOV7hA/FilL/yUGMs2MjR8G8d5o= X-Google-Smtp-Source: AB8JxZplvfH83L+3aLnMTvnCJy9O3qsp80+54C6n5UBvgu8j5S6Z8RsRmHqK449KuoCWHKUSJlZDEA== X-Received: by 2002:a63:6385:: with SMTP id x127-v6mr190438pgb.50.1524788823585; Thu, 26 Apr 2018 17:27:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 26 Apr 2018 14:26:44 -1000 Message-Id: <20180427002651.28356-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180427002651.28356-1-richard.henderson@linaro.org> References: <20180427002651.28356-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH 2/9] target/arm: Use new min/max expanders X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The generic expanders replace nearly identical code in the translator. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-a64.c | 46 ++++++++++++++----------------------------= ---- 1 file changed, 14 insertions(+), 32 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index bff4e13bf6..d916fea3a3 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -6021,15 +6021,18 @@ static void disas_simd_across_lanes(DisasContext *s= , uint32_t insn) tcg_gen_add_i64(tcg_res, tcg_res, tcg_elt); break; case 0x0a: /* SMAXV / UMAXV */ - tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE, - tcg_res, - tcg_res, tcg_elt, tcg_res, tcg_elt); + if (is_u) { + tcg_gen_umax_i64(tcg_res, tcg_res, tcg_elt); + } else { + tcg_gen_smax_i64(tcg_res, tcg_res, tcg_elt); + } break; case 0x1a: /* SMINV / UMINV */ - tcg_gen_movcond_i64(is_u ? TCG_COND_LEU : TCG_COND_LE, - tcg_res, - tcg_res, tcg_elt, tcg_res, tcg_elt); - break; + if (is_u) { + tcg_gen_umin_i64(tcg_res, tcg_res, tcg_elt); + } else { + tcg_gen_smin_i64(tcg_res, tcg_res, tcg_elt); + } break; default: g_assert_not_reached(); @@ -9931,27 +9934,6 @@ static void disas_simd_3same_logic(DisasContext *s, = uint32_t insn) } } =20 -/* Helper functions for 32 bit comparisons */ -static void gen_max_s32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2) -{ - tcg_gen_movcond_i32(TCG_COND_GE, res, op1, op2, op1, op2); -} - -static void gen_max_u32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2) -{ - tcg_gen_movcond_i32(TCG_COND_GEU, res, op1, op2, op1, op2); -} - -static void gen_min_s32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2) -{ - tcg_gen_movcond_i32(TCG_COND_LE, res, op1, op2, op1, op2); -} - -static void gen_min_u32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2) -{ - tcg_gen_movcond_i32(TCG_COND_LEU, res, op1, op2, op1, op2); -} - /* Pairwise op subgroup of C3.6.16. * * This is called directly or via the handle_3same_float for float pairwise @@ -10051,7 +10033,7 @@ static void handle_simd_3same_pair(DisasContext *s,= int is_q, int u, int opcode, static NeonGenTwoOpFn * const fns[3][2] =3D { { gen_helper_neon_pmax_s8, gen_helper_neon_pmax_u8 }, { gen_helper_neon_pmax_s16, gen_helper_neon_pmax_u16 }, - { gen_max_s32, gen_max_u32 }, + { tcg_gen_smax_i32, tcg_gen_umax_i32 }, }; genfn =3D fns[size][u]; break; @@ -10061,7 +10043,7 @@ static void handle_simd_3same_pair(DisasContext *s,= int is_q, int u, int opcode, static NeonGenTwoOpFn * const fns[3][2] =3D { { gen_helper_neon_pmin_s8, gen_helper_neon_pmin_u8 }, { gen_helper_neon_pmin_s16, gen_helper_neon_pmin_u16 }, - { gen_min_s32, gen_min_u32 }, + { tcg_gen_smin_i32, tcg_gen_umin_i32 }, }; genfn =3D fns[size][u]; break; @@ -10516,7 +10498,7 @@ static void disas_simd_3same_int(DisasContext *s, u= int32_t insn) static NeonGenTwoOpFn * const fns[3][2] =3D { { gen_helper_neon_max_s8, gen_helper_neon_max_u8 }, { gen_helper_neon_max_s16, gen_helper_neon_max_u16 }, - { gen_max_s32, gen_max_u32 }, + { tcg_gen_smax_i32, tcg_gen_umax_i32 }, }; genfn =3D fns[size][u]; break; @@ -10527,7 +10509,7 @@ static void disas_simd_3same_int(DisasContext *s, u= int32_t insn) static NeonGenTwoOpFn * const fns[3][2] =3D { { gen_helper_neon_min_s8, gen_helper_neon_min_u8 }, { gen_helper_neon_min_s16, gen_helper_neon_min_u16 }, - { gen_min_s32, gen_min_u32 }, + { tcg_gen_smin_i32, tcg_gen_umin_i32 }, }; genfn =3D fns[size][u]; break; --=20 2.14.3