From nobody Tue Feb 10 01:14:42 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1524740292832899.5616225742248; Thu, 26 Apr 2018 03:58:12 -0700 (PDT) Received: from localhost ([::1]:41470 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeZQ-00015K-4j for importer@patchew.org; Thu, 26 Apr 2018 06:56:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39745) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeR0-0002l8-IM for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fBeQy-0001Yp-BY for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:29 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:41150) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fBeQy-0001OF-4l for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:28 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fBeQr-00031y-Hj for qemu-devel@nongnu.org; Thu, 26 Apr 2018 11:47:21 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 26 Apr 2018 11:47:03 +0100 Message-Id: <20180426104715.21702-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180426104715.21702-1-peter.maydell@linaro.org> References: <20180426104715.21702-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 07/19] target/arm: Mask PMU register writes based on PMCR_EL0.N X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aaron Lindsay This is in preparation for enabling counters other than PMCCNTR Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Message-id: 1523997485-1905-5-git-send-email-alindsay@codeaurora.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 31 ++++++++++++++++++++++--------- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7bf4afa719..3238aacaa6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -52,11 +52,6 @@ typedef struct V8M_SAttributes { static void v8m_security_lookup(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_i= dx, V8M_SAttributes *sattrs); - -/* Definitions for the PMCCNTR and PMCR registers */ -#define PMCRD 0x8 -#define PMCRC 0x4 -#define PMCRE 0x1 #endif =20 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) @@ -906,6 +901,24 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { REGINFO_SENTINEL }; =20 +/* Definitions for the PMU registers */ +#define PMCRN_MASK 0xf800 +#define PMCRN_SHIFT 11 +#define PMCRD 0x8 +#define PMCRC 0x4 +#define PMCRE 0x1 + +static inline uint32_t pmu_num_counters(CPUARMState *env) +{ + return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT; +} + +/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ +static inline uint64_t pmu_counter_mask(CPUARMState *env) +{ + return (1 << 31) | ((1 << pmu_num_counters(env)) - 1); +} + static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *r= i, bool isread) { @@ -1113,14 +1126,14 @@ static void pmccfiltr_write(CPUARMState *env, const= ARMCPRegInfo *ri, static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - value &=3D (1 << 31); + value &=3D pmu_counter_mask(env); env->cp15.c9_pmcnten |=3D value; } =20 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - value &=3D (1 << 31); + value &=3D pmu_counter_mask(env); env->cp15.c9_pmcnten &=3D ~value; } =20 @@ -1168,14 +1181,14 @@ static void pmintenset_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, uint64_t value) { /* We have no event counters so only the C bit can be changed */ - value &=3D (1 << 31); + value &=3D pmu_counter_mask(env); env->cp15.c9_pminten |=3D value; } =20 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - value &=3D (1 << 31); + value &=3D pmu_counter_mask(env); env->cp15.c9_pminten &=3D ~value; } =20 --=20 2.17.0