From nobody Thu Dec 18 22:26:33 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1524740003489157.22664107470757; Thu, 26 Apr 2018 03:53:23 -0700 (PDT) Received: from localhost ([::1]:41452 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeWg-00070e-Nm for importer@patchew.org; Thu, 26 Apr 2018 06:53:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39693) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeQy-0002kf-4s for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fBeQx-0001XS-9z for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:28 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:41152) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fBeQx-0001Vb-2S for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:27 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fBeQv-00034U-RD for qemu-devel@nongnu.org; Thu, 26 Apr 2018 11:47:25 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 26 Apr 2018 11:47:09 +0100 Message-Id: <20180426104715.21702-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180426104715.21702-1-peter.maydell@linaro.org> References: <20180426104715.21702-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 13/19] target/arm: Make PMOVSCLR and PMUSERENR 64 bits wide X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aaron Lindsay This is a bug fix to ensure 64-bit reads of these registers don't read adjacent data. Signed-off-by: Aaron Lindsay Message-id: 1523997485-1905-13-git-send-email-alindsay@codeaurora.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 4 ++-- target/arm/helper.c | 5 +++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b9b47f4b22..44e6b77151 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -367,8 +367,8 @@ typedef struct CPUARMState { uint32_t c9_data; uint64_t c9_pmcr; /* performance monitor control register */ uint64_t c9_pmcnten; /* perf monitor counter enables */ - uint32_t c9_pmovsr; /* perf monitor overflow status */ - uint32_t c9_pmuserenr; /* perf monitor user enable */ + uint64_t c9_pmovsr; /* perf monitor overflow status */ + uint64_t c9_pmuserenr; /* perf monitor user enable */ uint64_t c9_pmselr; /* perf monitor counter selection register */ uint64_t c9_pminten; /* perf monitor interrupt enables */ union { /* Memory attribute redirection */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 85c289f3b9..52a88e0297 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1305,7 +1305,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcnten), .writefn =3D pmcntenclr_write }, { .name =3D "PMOVSR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 3, - .access =3D PL0_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_p= movsr), + .access =3D PL0_RW, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmovsr), .accessfn =3D pmreg_access, .writefn =3D pmovsr_write, .raw_writefn =3D raw_write }, @@ -1360,7 +1361,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .accessfn =3D pmreg_access_xevcntr }, { .name =3D "PMUSERENR", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 0, .access =3D PL0_R | PL1_RW, .accessfn =3D access_tpm, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmuserenr), + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmuserenr), .resetvalue =3D 0, .writefn =3D pmuserenr_write, .raw_writefn =3D raw_write }, { .name =3D "PMUSERENR_EL0", .state =3D ARM_CP_STATE_AA64, --=20 2.17.0