From nobody Thu Dec 18 22:21:22 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1524740454714331.10088245167856; Thu, 26 Apr 2018 04:00:54 -0700 (PDT) Received: from localhost ([::1]:41482 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBebx-00035Y-9R for importer@patchew.org; Thu, 26 Apr 2018 06:58:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39831) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeR1-0002lH-NV for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fBeR0-0001bR-Fp for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:31 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:41154) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fBeR0-0001XB-8d for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:30 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fBeQn-0002z2-6Z for qemu-devel@nongnu.org; Thu, 26 Apr 2018 11:47:17 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 26 Apr 2018 11:46:57 +0100 Message-Id: <20180426104715.21702-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180426104715.21702-1-peter.maydell@linaro.org> References: <20180426104715.21702-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 01/19] device_tree: Increase FDT_MAX_SIZE to 1 MiB X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Geert Uytterhoeven It is not uncommon for a contemporary FDT to be larger than 64 KiB, leading to failures loading the device tree from sysfs: qemu-system-aarch64: qemu_fdt_setprop: Couldn't set ...: FDT_ERR_NOSPACE Hence increase the limit to 1 MiB, like on PPC. For reference, the largest arm64 DTB created from the Linux sources is ca. 75 KiB large (100 KiB when built with symbols/fixup support). Cc: qemu-stable@nongnu.org Signed-off-by: Geert Uytterhoeven Message-id: 1523541337-23919-1-git-send-email-geert+renesas@glider.be Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- device_tree.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/device_tree.c b/device_tree.c index 19458b32bf..52c3358a55 100644 --- a/device_tree.c +++ b/device_tree.c @@ -29,7 +29,7 @@ =20 #include =20 -#define FDT_MAX_SIZE 0x10000 +#define FDT_MAX_SIZE 0x100000 =20 void *create_device_tree(int *sizep) { --=20 2.17.0 From nobody Thu Dec 18 22:21:22 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1524740928792729.1265083118299; Thu, 26 Apr 2018 04:08:48 -0700 (PDT) Received: from localhost ([::1]:41531 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBejf-00016r-VJ for importer@patchew.org; Thu, 26 Apr 2018 07:06:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39828) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeR1-0002lG-LC for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fBeR0-0001aw-7C for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:31 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:41150) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fBeQz-0001OF-UR for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:30 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fBeQn-0002zd-Sp for qemu-devel@nongnu.org; Thu, 26 Apr 2018 11:47:17 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 26 Apr 2018 11:46:58 +0100 Message-Id: <20180426104715.21702-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180426104715.21702-1-peter.maydell@linaro.org> References: <20180426104715.21702-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 02/19] arm: always start from first_cpu when registering loader cpu reset callback X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Igor Mammedov if arm_load_kernel() were passed non first_cpu, QEMU would end up with partially set do_cpu_reset() callback leaving some CPUs without it. Make sure that do_cpu_reset() is registered for all CPUs by enumerating CPUs from first_cpu. (In practice every board that we have was passing us the first CPU as the boot CPU, either directly or indirectly, so this wasn't causing incorrect behaviour.) Signed-off-by: Igor Mammedov Reviewed-by: Peter Maydell [PMM: added a note that this isn't a behaviour change] Signed-off-by: Peter Maydell --- hw/arm/boot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 26184bcd7c..9ae6ab2689 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -1188,7 +1188,7 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_inf= o *info) * actually loading a kernel, the handler is also responsible for * arranging that we start it correctly. */ - for (cs =3D CPU(cpu); cs; cs =3D CPU_NEXT(cs)) { + for (cs =3D first_cpu; cs; cs =3D CPU_NEXT(cs)) { qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); } } --=20 2.17.0 From nobody Thu Dec 18 22:21:22 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1524740617320715.0523405272377; Thu, 26 Apr 2018 04:03:37 -0700 (PDT) Received: from localhost ([::1]:41503 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeee-0005WL-FL for importer@patchew.org; Thu, 26 Apr 2018 07:01:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39817) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeR1-0002lE-9y for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fBeR0-0001ag-2X for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:31 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:41156) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fBeQz-0001Yu-Sb for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:30 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fBeQo-000306-K5 for qemu-devel@nongnu.org; Thu, 26 Apr 2018 11:47:18 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 26 Apr 2018 11:46:59 +0100 Message-Id: <20180426104715.21702-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180426104715.21702-1-peter.maydell@linaro.org> References: <20180426104715.21702-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 03/19] target/arm: Remove stale TODO comment X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Remove a stale TODO comment -- we have now made the arm_ldl_ptw() and arm_ldq_ptw() functions propagate physical memory read errors out to their callers. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20180419142151.9862-1-peter.maydell@linaro.org --- target/arm/helper.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b14fdab140..3ad0371aeb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8680,13 +8680,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARM= MMUIdx mmu_idx, return addr; } =20 -/* All loads done in the course of a page table walk go through here. - * TODO: rather than ignoring errors from physical memory reads (which - * are external aborts in ARM terminology) we should propagate this - * error out so that we can turn it into a Data Abort if this walk - * was being done for a CPU load/store or an address translation instructi= on - * (but not if it was for a debug access). - */ +/* All loads done in the course of a page table walk go through here. */ static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) { --=20 2.17.0 From nobody Thu Dec 18 22:21:22 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152474062637553.801034725001045; Thu, 26 Apr 2018 04:03:46 -0700 (PDT) Received: from localhost ([::1]:41504 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeek-0005ba-N2 for importer@patchew.org; Thu, 26 Apr 2018 07:01:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39795) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeR0-0002lD-Lm for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fBeQz-0001a5-IL for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:30 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:41154) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fBeQz-0001XB-BV for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:29 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fBeQp-00030a-Ay for qemu-devel@nongnu.org; Thu, 26 Apr 2018 11:47:19 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 26 Apr 2018 11:47:00 +0100 Message-Id: <20180426104715.21702-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180426104715.21702-1-peter.maydell@linaro.org> References: <20180426104715.21702-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 04/19] target/arm: Use v7m_stack_read() for reading the frame signature X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 In commit 95695effe8caa552b8f2 we changed the v7M/v8M stack pop code to use a new v7m_stack_read() function that checks whether the read should fail due to an MPU or bus abort. We missed one call though, the one which reads the signature word for the callee-saved register part of the frame. Correct the omission. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20180419142106.9694-1-peter.maydell@linaro.org --- target/arm/helper.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3ad0371aeb..0fa02c31e1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6913,7 +6913,6 @@ static bool v7m_push_stack(ARMCPU *cpu) static void do_v7m_exception_exit(ARMCPU *cpu) { CPUARMState *env =3D &cpu->env; - CPUState *cs =3D CPU(cpu); uint32_t excret; uint32_t xpsr; bool ufault =3D false; @@ -7112,9 +7111,11 @@ static void do_v7m_exception_exit(ARMCPU *cpu) ((excret & R_V7M_EXCRET_ES_MASK) =3D=3D 0 || (excret & R_V7M_EXCRET_DCRS_MASK) =3D=3D 0)) { uint32_t expected_sig =3D 0xfefa125b; - uint32_t actual_sig =3D ldl_phys(cs->as, frameptr); + uint32_t actual_sig; =20 - if (expected_sig !=3D actual_sig) { + pop_ok =3D v7m_stack_read(cpu, &actual_sig, frameptr, mmu_idx); + + if (pop_ok && expected_sig !=3D actual_sig) { /* Take a SecureFault on the current stack */ env->v7m.sfsr |=3D R_V7M_SFSR_INVIS_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, fal= se); @@ -7125,7 +7126,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) return; } =20 - pop_ok =3D + pop_ok =3D pop_ok && v7m_stack_read(cpu, &env->regs[4], frameptr + 0x8, mmu_idx= ) && v7m_stack_read(cpu, &env->regs[4], frameptr + 0x8, mmu_idx= ) && v7m_stack_read(cpu, &env->regs[5], frameptr + 0xc, mmu_idx= ) && --=20 2.17.0 From nobody Thu Dec 18 22:21:22 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1524740421459305.87178424289823; Thu, 26 Apr 2018 04:00:21 -0700 (PDT) Received: from localhost ([::1]:41481 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBebM-0002VV-It for importer@patchew.org; Thu, 26 Apr 2018 06:58:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39784) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeR0-0002lC-JJ for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fBeQz-0001Zm-CW for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:30 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:41150) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fBeQz-0001OF-2B for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:29 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fBeQq-000314-1j for qemu-devel@nongnu.org; Thu, 26 Apr 2018 11:47:20 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 26 Apr 2018 11:47:01 +0100 Message-Id: <20180426104715.21702-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180426104715.21702-1-peter.maydell@linaro.org> References: <20180426104715.21702-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 05/19] target/arm: Check PMCNTEN for whether PMCCNTR is enabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aaron Lindsay Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Message-id: 1523997485-1905-2-git-send-email-alindsay@codeaurora.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0fa02c31e1..1526724d64 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -994,7 +994,7 @@ static inline bool arm_ccnt_enabled(CPUARMState *env) { /* This does not support checking PMCCFILTR_EL0 register */ =20 - if (!(env->cp15.c9_pmcr & PMCRE)) { + if (!(env->cp15.c9_pmcr & PMCRE) || !(env->cp15.c9_pmcnten & (1 << 31)= )) { return false; } =20 --=20 2.17.0 From nobody Thu Dec 18 22:21:22 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1524740293803635.4985088018707; Thu, 26 Apr 2018 03:58:13 -0700 (PDT) Received: from localhost ([::1]:41471 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeZR-00016F-39 for importer@patchew.org; Thu, 26 Apr 2018 06:56:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39769) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeR0-0002l9-IH for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fBeQz-0001ZR-3S for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:30 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:41152) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fBeQy-0001Vb-SU for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:29 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fBeQq-00031X-R1 for qemu-devel@nongnu.org; Thu, 26 Apr 2018 11:47:20 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 26 Apr 2018 11:47:02 +0100 Message-Id: <20180426104715.21702-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180426104715.21702-1-peter.maydell@linaro.org> References: <20180426104715.21702-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 06/19] target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aaron Lindsay They share the same underlying state Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Message-id: 1523997485-1905-3-git-send-email-alindsay@codeaurora.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1526724d64..7bf4afa719 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1318,7 +1318,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmselr), .writefn =3D pmselr_write, .raw_writefn =3D raw_write, }, { .name =3D "PMCCNTR", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 =3D = 0, .opc2 =3D 0, - .access =3D PL0_RW, .resetvalue =3D 0, .type =3D ARM_CP_IO, + .access =3D PL0_RW, .resetvalue =3D 0, .type =3D ARM_CP_ALIAS | ARM_= CP_IO, .readfn =3D pmccntr_read, .writefn =3D pmccntr_write32, .accessfn =3D pmreg_access_ccntr }, { .name =3D "PMCCNTR_EL0", .state =3D ARM_CP_STATE_AA64, --=20 2.17.0 From nobody Thu Dec 18 22:21:22 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1524740292832899.5616225742248; Thu, 26 Apr 2018 03:58:12 -0700 (PDT) Received: from localhost ([::1]:41470 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeZQ-00015K-4j for importer@patchew.org; Thu, 26 Apr 2018 06:56:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39745) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeR0-0002l8-IM for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fBeQy-0001Yp-BY for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:29 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:41150) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fBeQy-0001OF-4l for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:28 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fBeQr-00031y-Hj for qemu-devel@nongnu.org; Thu, 26 Apr 2018 11:47:21 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 26 Apr 2018 11:47:03 +0100 Message-Id: <20180426104715.21702-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180426104715.21702-1-peter.maydell@linaro.org> References: <20180426104715.21702-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 07/19] target/arm: Mask PMU register writes based on PMCR_EL0.N X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aaron Lindsay This is in preparation for enabling counters other than PMCCNTR Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Message-id: 1523997485-1905-5-git-send-email-alindsay@codeaurora.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 31 ++++++++++++++++++++++--------- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7bf4afa719..3238aacaa6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -52,11 +52,6 @@ typedef struct V8M_SAttributes { static void v8m_security_lookup(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_i= dx, V8M_SAttributes *sattrs); - -/* Definitions for the PMCCNTR and PMCR registers */ -#define PMCRD 0x8 -#define PMCRC 0x4 -#define PMCRE 0x1 #endif =20 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) @@ -906,6 +901,24 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { REGINFO_SENTINEL }; =20 +/* Definitions for the PMU registers */ +#define PMCRN_MASK 0xf800 +#define PMCRN_SHIFT 11 +#define PMCRD 0x8 +#define PMCRC 0x4 +#define PMCRE 0x1 + +static inline uint32_t pmu_num_counters(CPUARMState *env) +{ + return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT; +} + +/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ +static inline uint64_t pmu_counter_mask(CPUARMState *env) +{ + return (1 << 31) | ((1 << pmu_num_counters(env)) - 1); +} + static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *r= i, bool isread) { @@ -1113,14 +1126,14 @@ static void pmccfiltr_write(CPUARMState *env, const= ARMCPRegInfo *ri, static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - value &=3D (1 << 31); + value &=3D pmu_counter_mask(env); env->cp15.c9_pmcnten |=3D value; } =20 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - value &=3D (1 << 31); + value &=3D pmu_counter_mask(env); env->cp15.c9_pmcnten &=3D ~value; } =20 @@ -1168,14 +1181,14 @@ static void pmintenset_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, uint64_t value) { /* We have no event counters so only the C bit can be changed */ - value &=3D (1 << 31); + value &=3D pmu_counter_mask(env); env->cp15.c9_pminten |=3D value; } =20 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - value &=3D (1 << 31); + value &=3D pmu_counter_mask(env); env->cp15.c9_pminten &=3D ~value; } =20 --=20 2.17.0 From nobody Thu Dec 18 22:21:22 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1524740577066827.828610877879; Thu, 26 Apr 2018 04:02:57 -0700 (PDT) Received: from localhost ([::1]:41495 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBedx-0004ry-8m for importer@patchew.org; Thu, 26 Apr 2018 07:00:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39729) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeR0-0002l7-IN for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fBeQy-0001Yc-6n for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:29 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:41152) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fBeQx-0001Vb-VV for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:28 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fBeQs-00032Q-9V for qemu-devel@nongnu.org; Thu, 26 Apr 2018 11:47:22 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 26 Apr 2018 11:47:04 +0100 Message-Id: <20180426104715.21702-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180426104715.21702-1-peter.maydell@linaro.org> References: <20180426104715.21702-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 08/19] target/arm: Fetch GICv3 state directly from CPUARMState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aaron Lindsay This eliminates the need for fetching it from el_change_hook_opaque, and allows for supporting multiple el_change_hooks without having to hack something together to find the registered opaque belonging to GICv3. Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Message-id: 1523997485-1905-6-git-send-email-alindsay@codeaurora.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 10 ---------- hw/intc/arm_gicv3_cpuif.c | 10 ++-------- 2 files changed, 2 insertions(+), 18 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 19a0c03f9b..6bd8ff5917 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2902,16 +2902,6 @@ static inline AddressSpace *arm_addressspace(CPUStat= e *cs, MemTxAttrs attrs) void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, void *opaque); =20 -/** - * arm_get_el_change_hook_opaque: - * Return the opaque data that will be used by the el_change_hook - * for this CPU. - */ -static inline void *arm_get_el_change_hook_opaque(ARMCPU *cpu) -{ - return cpu->el_change_hook_opaque; -} - /** * aa32_vfp_dreg: * Return a pointer to the Dn register within env in 32-bit mode. diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 26f5eeda94..cb9a3a542d 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -29,11 +29,7 @@ void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *= s) =20 static GICv3CPUState *icc_cs_from_env(CPUARMState *env) { - /* Given the CPU, find the right GICv3CPUState struct. - * Since we registered the CPU interface with the EL change hook as - * the opaque pointer, we can just directly get from the CPU to it. - */ - return arm_get_el_change_hook_opaque(arm_env_get_cpu(env)); + return env->gicv3state; } =20 static bool gicv3_use_ns_bank(CPUARMState *env) @@ -2615,9 +2611,7 @@ void gicv3_init_cpuif(GICv3State *s) * it might be with code translated by CPU 0 but run by CPU 1, in * which case we'd get the wrong value. * So instead we define the regs with no ri->opaque info, and - * get back to the GICv3CPUState from the ARMCPU by reading back - * the opaque pointer from the el_change_hook, which we're going - * to need to register anyway. + * get back to the GICv3CPUState from the CPUARMState. */ define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); if (arm_feature(&cpu->env, ARM_FEATURE_EL2) --=20 2.17.0 From nobody Thu Dec 18 22:21:22 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1524740460368946.8327679974904; Thu, 26 Apr 2018 04:01:00 -0700 (PDT) Received: from localhost ([::1]:41484 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBec7-0003Dw-Iz for importer@patchew.org; Thu, 26 Apr 2018 06:58:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39709) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeQy-0002l1-HJ for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fBeQx-0001Xl-F3 for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:28 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:41150) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fBeQx-0001OF-79 for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:27 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fBeQt-00032r-00 for qemu-devel@nongnu.org; Thu, 26 Apr 2018 11:47:23 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 26 Apr 2018 11:47:05 +0100 Message-Id: <20180426104715.21702-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180426104715.21702-1-peter.maydell@linaro.org> References: <20180426104715.21702-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 09/19] target/arm: Support multiple EL change hooks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aaron Lindsay Signed-off-by: Aaron Lindsay Message-id: 1523997485-1905-7-git-send-email-alindsay@codeaurora.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 20 ++++++++++---------- target/arm/internals.h | 7 ++++--- target/arm/cpu.c | 21 ++++++++++++++++----- 3 files changed, 30 insertions(+), 18 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6bd8ff5917..b3def5afad 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -632,12 +632,17 @@ typedef struct CPUARMState { } CPUARMState; =20 /** - * ARMELChangeHook: + * ARMELChangeHookFn: * type of a function which can be registered via arm_register_el_change_h= ook() * to get callbacks when the CPU changes its exception level or mode. */ -typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque); - +typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); +typedef struct ARMELChangeHook ARMELChangeHook; +struct ARMELChangeHook { + ARMELChangeHookFn *hook; + void *opaque; + QLIST_ENTRY(ARMELChangeHook) node; +}; =20 /* These values map onto the return values for * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ @@ -826,8 +831,7 @@ struct ARMCPU { */ bool cfgend; =20 - ARMELChangeHook *el_change_hook; - void *el_change_hook_opaque; + QLIST_HEAD(, ARMELChangeHook) el_change_hooks; =20 int32_t node_id; /* NUMA node this CPU belongs to */ =20 @@ -2894,12 +2898,8 @@ static inline AddressSpace *arm_addressspace(CPUStat= e *cs, MemTxAttrs attrs) * CPU changes exception level or mode. The hook function will be * passed a pointer to the ARMCPU and the opaque data pointer passed * to this function when the hook was registered. - * - * Note that we currently only support registering a single hook function, - * and will assert if this function is called twice. - * This facility is intended for the use of the GICv3 emulation. */ -void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, +void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void *opaque); =20 /** diff --git a/target/arm/internals.h b/target/arm/internals.h index 8ce944b7a0..6358c2ad5a 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -727,11 +727,12 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr= ); =20 -/* Call the EL change hook if one has been registered */ +/* Call any registered EL change hooks */ static inline void arm_call_el_change_hook(ARMCPU *cpu) { - if (cpu->el_change_hook) { - cpu->el_change_hook(cpu, cpu->el_change_hook_opaque); + ARMELChangeHook *hook, *next; + QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { + hook->hook(cpu, hook->opaque); } } =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 022d8c5787..1f689f6817 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -55,13 +55,15 @@ static bool arm_cpu_has_work(CPUState *cs) | CPU_INTERRUPT_EXITTB); } =20 -void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, +void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void *opaque) { - /* We currently only support registering a single hook function */ - assert(!cpu->el_change_hook); - cpu->el_change_hook =3D hook; - cpu->el_change_hook_opaque =3D opaque; + ARMELChangeHook *entry =3D g_new0(ARMELChangeHook, 1); + + entry->hook =3D hook; + entry->opaque =3D opaque; + + QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); } =20 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) @@ -552,6 +554,8 @@ static void arm_cpu_initfn(Object *obj) cpu->cp_regs =3D g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free); =20 + QLIST_INIT(&cpu->el_change_hooks); + #ifndef CONFIG_USER_ONLY /* Our inbound IRQ and FIQ lines */ if (kvm_enabled()) { @@ -713,7 +717,14 @@ static void arm_cpu_post_init(Object *obj) static void arm_cpu_finalizefn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMELChangeHook *hook, *next; + g_hash_table_destroy(cpu->cp_regs); + + QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { + QLIST_REMOVE(hook, node); + g_free(hook); + } } =20 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) --=20 2.17.0 From nobody Thu Dec 18 22:21:22 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1524740004547996.0140445894056; Thu, 26 Apr 2018 03:53:24 -0700 (PDT) Received: from localhost ([::1]:41453 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeWh-00071G-Nb for importer@patchew.org; Thu, 26 Apr 2018 06:53:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39662) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeQw-0002jf-Tn for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fBeQv-0001Vc-IO for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:26 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:41150) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fBeQv-0001OF-AS for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:25 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fBeQt-00033I-Mq for qemu-devel@nongnu.org; Thu, 26 Apr 2018 11:47:23 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 26 Apr 2018 11:47:06 +0100 Message-Id: <20180426104715.21702-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180426104715.21702-1-peter.maydell@linaro.org> References: <20180426104715.21702-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 10/19] target/arm: Add pre-EL change hooks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aaron Lindsay Because the design of the PMU requires that the counter values be converted between their delta and guest-visible forms for mode filtering, an additional hook which occurs before the EL is changed is necessary. Signed-off-by: Aaron Lindsay Message-id: 1523997485-1905-8-git-send-email-alindsay@codeaurora.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 22 +++++++++++++++++++--- target/arm/internals.h | 7 +++++++ target/arm/cpu.c | 16 ++++++++++++++++ target/arm/helper.c | 14 ++++++++------ target/arm/op_helper.c | 8 ++++++++ 5 files changed, 58 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b3def5afad..b9b47f4b22 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -831,6 +831,7 @@ struct ARMCPU { */ bool cfgend; =20 + QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; QLIST_HEAD(, ARMELChangeHook) el_change_hooks; =20 int32_t node_id; /* NUMA node this CPU belongs to */ @@ -2893,14 +2894,29 @@ static inline AddressSpace *arm_addressspace(CPUSta= te *cs, MemTxAttrs attrs) #endif =20 /** - * arm_register_el_change_hook: - * Register a hook function which will be called back whenever this + * arm_register_pre_el_change_hook: + * Register a hook function which will be called immediately before this * CPU changes exception level or mode. The hook function will be * passed a pointer to the ARMCPU and the opaque data pointer passed * to this function when the hook was registered. + * + * Note that if a pre-change hook is called, any registered post-change ho= oks + * are guaranteed to subsequently be called. */ -void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, +void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void *opaque); +/** + * arm_register_el_change_hook: + * Register a hook function which will be called immediately after this + * CPU changes exception level or mode. The hook function will be + * passed a pointer to the ARMCPU and the opaque data pointer passed + * to this function when the hook was registered. + * + * Note that any registered hooks registered here are guaranteed to be cal= led + * if pre-change hooks have been. + */ +void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void + *opaque); =20 /** * aa32_vfp_dreg: diff --git a/target/arm/internals.h b/target/arm/internals.h index 6358c2ad5a..dc9357766c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -728,6 +728,13 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwadd= r physaddr, MemTxResult response, uintptr_t retaddr= ); =20 /* Call any registered EL change hooks */ +static inline void arm_call_pre_el_change_hook(ARMCPU *cpu) +{ + ARMELChangeHook *hook, *next; + QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { + hook->hook(cpu, hook->opaque); + } +} static inline void arm_call_el_change_hook(ARMCPU *cpu) { ARMELChangeHook *hook, *next; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1f689f6817..d175c5e94f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -55,6 +55,17 @@ static bool arm_cpu_has_work(CPUState *cs) | CPU_INTERRUPT_EXITTB); } =20 +void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, + void *opaque) +{ + ARMELChangeHook *entry =3D g_new0(ARMELChangeHook, 1); + + entry->hook =3D hook; + entry->opaque =3D opaque; + + QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); +} + void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void *opaque) { @@ -554,6 +565,7 @@ static void arm_cpu_initfn(Object *obj) cpu->cp_regs =3D g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free); =20 + QLIST_INIT(&cpu->pre_el_change_hooks); QLIST_INIT(&cpu->el_change_hooks); =20 #ifndef CONFIG_USER_ONLY @@ -721,6 +733,10 @@ static void arm_cpu_finalizefn(Object *obj) =20 g_hash_table_destroy(cpu->cp_regs); =20 + QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { + QLIST_REMOVE(hook, node); + g_free(hook); + } QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { QLIST_REMOVE(hook, node); g_free(hook); diff --git a/target/arm/helper.c b/target/arm/helper.c index 3238aacaa6..81e88f255b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8249,6 +8249,14 @@ void arm_cpu_do_interrupt(CPUState *cs) return; } =20 + /* Hooks may change global state so BQL should be held, also the + * BQL needs to be held for any modification of + * cs->interrupt_request. + */ + g_assert(qemu_mutex_iothread_locked()); + + arm_call_pre_el_change_hook(cpu); + assert(!excp_is_internal(cs->exception_index)); if (arm_el_is_aa64(env, new_el)) { arm_cpu_do_interrupt_aarch64(cs); @@ -8256,12 +8264,6 @@ void arm_cpu_do_interrupt(CPUState *cs) arm_cpu_do_interrupt_aarch32(cs); } =20 - /* Hooks may change global state so BQL should be held, also the - * BQL needs to be held for any modification of - * cs->interrupt_request. - */ - g_assert(qemu_mutex_iothread_locked()); - arm_call_el_change_hook(cpu); =20 if (!kvm_enabled()) { diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 84f08bf815..f728f25e4b 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -511,6 +511,10 @@ void HELPER(cpsr_write)(CPUARMState *env, uint32_t val= , uint32_t mask) /* Write the CPSR for a 32-bit exception return */ void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val) { + qemu_mutex_lock_iothread(); + arm_call_pre_el_change_hook(arm_env_get_cpu(env)); + qemu_mutex_unlock_iothread(); + cpsr_write(env, val, CPSR_ERET_MASK, CPSRWriteExceptionReturn); =20 /* Generated code has already stored the new PC value, but @@ -1028,6 +1032,10 @@ void HELPER(exception_return)(CPUARMState *env) goto illegal_return; } =20 + qemu_mutex_lock_iothread(); + arm_call_pre_el_change_hook(arm_env_get_cpu(env)); + qemu_mutex_unlock_iothread(); + if (!return_to_aa64) { env->aarch64 =3D 0; /* We do a raw CPSR write because aarch64_sync_64_to_32() --=20 2.17.0 From nobody Thu Dec 18 22:21:22 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1524740301479747.9468114554952; Thu, 26 Apr 2018 03:58:21 -0700 (PDT) Received: from localhost ([::1]:41472 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeZY-0001DG-8A for importer@patchew.org; Thu, 26 Apr 2018 06:56:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39684) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeQx-0002kQ-UC for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fBeQw-0001Wy-Gy for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:27 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:41150) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fBeQw-0001OF-9M for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:26 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fBeQu-00033j-E6 for qemu-devel@nongnu.org; Thu, 26 Apr 2018 11:47:24 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 26 Apr 2018 11:47:07 +0100 Message-Id: <20180426104715.21702-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180426104715.21702-1-peter.maydell@linaro.org> References: <20180426104715.21702-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 11/19] target/arm: Allow EL change hooks to do IO X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aaron Lindsay During code generation, surround CPSR writes and exception returns which call the EL change hooks with gen_io_start/end. The immediate need is for the PMU to access the clock and icount during EL change to support mode filtering. Signed-off-by: Aaron Lindsay Message-id: 1523997485-1905-9-git-send-email-alindsay@codeaurora.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 6 ++++++ target/arm/translate.c | 12 ++++++++++++ 2 files changed, 18 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c91329249d..bff4e13bf6 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1930,7 +1930,13 @@ static void disas_uncond_b_reg(DisasContext *s, uint= 32_t insn) unallocated_encoding(s); return; } + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_exception_return(cpu_env); + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + gen_io_end(); + } /* Must exit loop to check un-masked IRQs */ s->base.is_jmp =3D DISAS_EXIT; return; diff --git a/target/arm/translate.c b/target/arm/translate.c index db1ce6510a..9bc2ce1a0b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4548,7 +4548,13 @@ static void gen_rfe(DisasContext *s, TCGv_i32 pc, TC= Gv_i32 cpsr) * appropriately depending on the new Thumb bit, so it must * be called after storing the new PC. */ + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_cpsr_write_eret(cpu_env, cpsr); + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + gen_io_end(); + } tcg_temp_free_i32(cpsr); /* Must exit loop to check un-masked IRQs */ s->base.is_jmp =3D DISAS_EXIT; @@ -9843,7 +9849,13 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) if (exc_return) { /* Restore CPSR from SPSR. */ tmp =3D load_cpu_field(spsr); + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_cpsr_write_eret(cpu_env, tmp); + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + gen_io_end(); + } tcg_temp_free_i32(tmp); /* Must exit loop to check un-masked IRQs */ s->base.is_jmp =3D DISAS_EXIT; --=20 2.17.0 From nobody Thu Dec 18 22:21:22 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1524740014770945.245219983832; Thu, 26 Apr 2018 03:53:34 -0700 (PDT) Received: from localhost ([::1]:41454 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeWs-0007BU-0S for importer@patchew.org; Thu, 26 Apr 2018 06:53:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39665) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeQx-0002jm-23 for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fBeQw-0001Wl-BH for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:27 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:41152) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fBeQw-0001Vb-4e for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:26 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fBeQv-00034D-40 for qemu-devel@nongnu.org; Thu, 26 Apr 2018 11:47:25 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 26 Apr 2018 11:47:08 +0100 Message-Id: <20180426104715.21702-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180426104715.21702-1-peter.maydell@linaro.org> References: <20180426104715.21702-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 12/19] target/arm: Fix bitmask for PMCCFILTR writes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aaron Lindsay It was shifted to the left one bit too few. Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Message-id: 1523997485-1905-10-git-send-email-alindsay@codeaurora.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 81e88f255b..85c289f3b9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1119,7 +1119,7 @@ static void pmccfiltr_write(CPUARMState *env, const A= RMCPRegInfo *ri, uint64_t value) { pmccntr_sync(env); - env->cp15.pmccfiltr_el0 =3D value & 0x7E000000; + env->cp15.pmccfiltr_el0 =3D value & 0xfc000000; pmccntr_sync(env); } =20 --=20 2.17.0 From nobody Thu Dec 18 22:21:22 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1524740003489157.22664107470757; Thu, 26 Apr 2018 03:53:23 -0700 (PDT) Received: from localhost ([::1]:41452 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeWg-00070e-Nm for importer@patchew.org; Thu, 26 Apr 2018 06:53:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39693) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeQy-0002kf-4s for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fBeQx-0001XS-9z for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:28 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:41152) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fBeQx-0001Vb-2S for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:27 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fBeQv-00034U-RD for qemu-devel@nongnu.org; Thu, 26 Apr 2018 11:47:25 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 26 Apr 2018 11:47:09 +0100 Message-Id: <20180426104715.21702-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180426104715.21702-1-peter.maydell@linaro.org> References: <20180426104715.21702-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 13/19] target/arm: Make PMOVSCLR and PMUSERENR 64 bits wide X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aaron Lindsay This is a bug fix to ensure 64-bit reads of these registers don't read adjacent data. Signed-off-by: Aaron Lindsay Message-id: 1523997485-1905-13-git-send-email-alindsay@codeaurora.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 4 ++-- target/arm/helper.c | 5 +++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b9b47f4b22..44e6b77151 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -367,8 +367,8 @@ typedef struct CPUARMState { uint32_t c9_data; uint64_t c9_pmcr; /* performance monitor control register */ uint64_t c9_pmcnten; /* perf monitor counter enables */ - uint32_t c9_pmovsr; /* perf monitor overflow status */ - uint32_t c9_pmuserenr; /* perf monitor user enable */ + uint64_t c9_pmovsr; /* perf monitor overflow status */ + uint64_t c9_pmuserenr; /* perf monitor user enable */ uint64_t c9_pmselr; /* perf monitor counter selection register */ uint64_t c9_pminten; /* perf monitor interrupt enables */ union { /* Memory attribute redirection */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 85c289f3b9..52a88e0297 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1305,7 +1305,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcnten), .writefn =3D pmcntenclr_write }, { .name =3D "PMOVSR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 3, - .access =3D PL0_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_p= movsr), + .access =3D PL0_RW, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmovsr), .accessfn =3D pmreg_access, .writefn =3D pmovsr_write, .raw_writefn =3D raw_write }, @@ -1360,7 +1361,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .accessfn =3D pmreg_access_xevcntr }, { .name =3D "PMUSERENR", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 0, .access =3D PL0_R | PL1_RW, .accessfn =3D access_tpm, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmuserenr), + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmuserenr), .resetvalue =3D 0, .writefn =3D pmuserenr_write, .raw_writefn =3D raw_write }, { .name =3D "PMUSERENR_EL0", .state =3D ARM_CP_STATE_AA64, --=20 2.17.0 From nobody Thu Dec 18 22:21:22 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152473979154936.53821241416688; Thu, 26 Apr 2018 03:49:51 -0700 (PDT) Received: from localhost ([::1]:41433 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeT5-00040f-9M for importer@patchew.org; Thu, 26 Apr 2018 06:49:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39717) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeR0-0002l6-I5 for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fBeQx-0001YE-P9 for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:28 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:41154) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fBeQx-0001XB-IE for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:27 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fBeQw-00034x-HM for qemu-devel@nongnu.org; Thu, 26 Apr 2018 11:47:26 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 26 Apr 2018 11:47:10 +0100 Message-Id: <20180426104715.21702-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180426104715.21702-1-peter.maydell@linaro.org> References: <20180426104715.21702-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 14/19] hw/arm/raspi: Don't bother setting default_cpu_type X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 In commit 210f47840dd62, we changed the bcm2836 SoC object to always create a CPU of the correct type for that SoC model. This makes the default_cpu_type settings in the MachineClass structs for the raspi2 and raspi3 boards redundant. We didn't change those at the time because it would have meant a temporary regression in a corner case of error handling if the user requested a non-existing CPU type. The -cpu parse handling changes in 2278b93941d42c3 mean that it no longer implicitly depends on default_cpu_type for this to work, so we can now delete the redundant default_cpu_type fields. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20180420155547.9497-1-peter.maydell@linaro.org --- hw/arm/raspi.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 955a7c4e80..66899c28dc 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -226,7 +226,6 @@ static void raspi2_machine_init(MachineClass *mc) mc->no_parallel =3D 1; mc->no_floppy =3D 1; mc->no_cdrom =3D 1; - mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a7"); mc->max_cpus =3D BCM283X_NCPUS; mc->min_cpus =3D BCM283X_NCPUS; mc->default_cpus =3D BCM283X_NCPUS; @@ -249,7 +248,6 @@ static void raspi3_machine_init(MachineClass *mc) mc->no_parallel =3D 1; mc->no_floppy =3D 1; mc->no_cdrom =3D 1; - mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a53"); mc->max_cpus =3D BCM283X_NCPUS; mc->min_cpus =3D BCM283X_NCPUS; mc->default_cpus =3D BCM283X_NCPUS; --=20 2.17.0 From nobody Thu Dec 18 22:21:22 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1524739965748690.9334386595792; Thu, 26 Apr 2018 03:52:45 -0700 (PDT) Received: from localhost ([::1]:41451 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeW0-0006SU-V7 for importer@patchew.org; Thu, 26 Apr 2018 06:52:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39774) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeR0-0002lB-IO for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fBeQy-0001Z0-Ji for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:30 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:41154) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fBeQy-0001XB-DU for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:28 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fBeQx-00035G-8v for qemu-devel@nongnu.org; Thu, 26 Apr 2018 11:47:27 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 26 Apr 2018 11:47:11 +0100 Message-Id: <20180426104715.21702-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180426104715.21702-1-peter.maydell@linaro.org> References: <20180426104715.21702-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 15/19] hw/arm/highbank: don't make sysram 'nomigrate' X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Currently we use memory_region_init_ram_nomigrate() to create the "highbank.sysram" memory region, and we don't manually register it with vmstate_register_ram(). This currently means that its contents are migrated but as a ram block whose name is the empty string; in future it may mean they are not migrated at all. Use memory_region_init_ram() instead. Note that this is a cross-version migration compatibility break for the "highbank" and "midway" machines. Signed-off-by: Peter Maydell Message-id: 20180420124835.7268-2-peter.maydell@linaro.org Reviewed-by: Michael Clark --- hw/arm/highbank.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index 1742cf6f6c..88326d1bfd 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -291,7 +291,7 @@ static void calxeda_init(MachineState *machine, enum cx= machines machine_id) memory_region_add_subregion(sysmem, 0, dram); =20 sysram =3D g_new(MemoryRegion, 1); - memory_region_init_ram_nomigrate(sysram, NULL, "highbank.sysram", 0x80= 00, + memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000, &error_fatal); memory_region_add_subregion(sysmem, 0xfff88000, sysram); if (bios_name !=3D NULL) { --=20 2.17.0 From nobody Thu Dec 18 22:21:22 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1524740453033856.4761861817061; Thu, 26 Apr 2018 04:00:53 -0700 (PDT) Received: from localhost ([::1]:41483 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBec0-000379-AD for importer@patchew.org; Thu, 26 Apr 2018 06:58:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39773) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeR0-0002lA-IK for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fBeQz-0001ZY-6s for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:30 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:41156) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fBeQy-0001Yu-Vo for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:29 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fBeQx-00035o-V1 for qemu-devel@nongnu.org; Thu, 26 Apr 2018 11:47:27 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 26 Apr 2018 11:47:12 +0100 Message-Id: <20180426104715.21702-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180426104715.21702-1-peter.maydell@linaro.org> References: <20180426104715.21702-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 16/19] hw/arm/aspeed: don't make 'boot_rom' region 'nomigrate' X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Currently we use memory_region_init_ram_nomigrate() to create the "aspeed.boot_rom" memory region, and we don't manually register it with vmstate_register_ram(). This currently means that its contents are migrated but as a ram block whose name is the empty string; in future it may mean they are not migrated at all. Use memory_region_init_ram() instead. Note that would be a cross-version migration compatibility break for the "palmetto-bmc", "ast2500-evb" and "romulus-bmc" machines, but migration is currently broken for them. Signed-off-by: Peter Maydell Reviewed-by: C=C3=A9dric Le Goater Tested-by: C=C3=A9dric Le Goater Message-id: 20180420124835.7268-3-peter.maydell@linaro.org --- hw/arm/aspeed.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 7088c907bd..aecb3c1e75 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -225,7 +225,7 @@ static void aspeed_board_init(MachineState *machine, * SoC and 128MB for the AST2500 SoC, which is twice as big as * needed by the flash modules of the Aspeed machines. */ - memory_region_init_rom_nomigrate(boot_rom, OBJECT(bmc), "aspeed.bo= ot_rom", + memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom", fl->size, &error_abort); memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, boot_rom); --=20 2.17.0 From nobody Thu Dec 18 22:21:22 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1524740143641934.9322962485222; Thu, 26 Apr 2018 03:55:43 -0700 (PDT) Received: from localhost ([::1]:41464 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeYn-0000Sy-Oq for importer@patchew.org; Thu, 26 Apr 2018 06:55:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39819) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeR1-0002lF-AX for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fBeQz-0001aY-Ve for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:31 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:41152) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fBeQz-0001Vb-Ov for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:29 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fBeQy-000369-L0 for qemu-devel@nongnu.org; Thu, 26 Apr 2018 11:47:28 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 26 Apr 2018 11:47:13 +0100 Message-Id: <20180426104715.21702-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180426104715.21702-1-peter.maydell@linaro.org> References: <20180426104715.21702-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 17/19] hw/arm/aspeed_soc: don't use vmstate_register_ram_global for SRAM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Currently we use vmstate_register_ram_global() for the SRAM; this is not a good idea for devices, because it means that you can only ever create one instance of the device, as the second instance would get a RAM block name clash. Instead, use memory_region_init_ram(), which automatically registers the RAM block with a local-to-the-device name. Note that this would be a cross-version migration compatibility break for the "palmetto-bmc", "ast2500-evb" and "romulus-bmc" machines, but migration is currently broken for them. Signed-off-by: Peter Maydell Reviewed-by: C=C3=A9dric Le Goater Tested-by: C=C3=A9dric Le Goater Message-id: 20180420124835.7268-4-peter.maydell@linaro.org --- hw/arm/aspeed_soc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 30d25f8b06..407f10d0d4 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -186,13 +186,12 @@ static void aspeed_soc_realize(DeviceState *dev, Erro= r **errp) } =20 /* SRAM */ - memory_region_init_ram_nomigrate(&s->sram, OBJECT(dev), "aspeed.sram", + memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", sc->info->sram_size, &err); if (err) { error_propagate(errp, err); return; } - vmstate_register_ram_global(&s->sram); memory_region_add_subregion(get_system_memory(), ASPEED_SOC_SRAM_BASE, &s->sram); =20 --=20 2.17.0 From nobody Thu Dec 18 22:21:22 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1524740766835454.0089149374645; Thu, 26 Apr 2018 04:06:06 -0700 (PDT) Received: from localhost ([::1]:41514 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeh0-0007RC-Ec for importer@patchew.org; Thu, 26 Apr 2018 07:04:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39835) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeR1-0002lS-Ra for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fBeR0-0001bd-KB for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:31 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:41158) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fBeR0-0001aI-Ci for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:30 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fBeQz-00036i-Cf for qemu-devel@nongnu.org; Thu, 26 Apr 2018 11:47:29 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 26 Apr 2018 11:47:14 +0100 Message-Id: <20180426104715.21702-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180426104715.21702-1-peter.maydell@linaro.org> References: <20180426104715.21702-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 18/19] timer/aspeed: fix vmstate version id X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: C=C3=A9dric Le Goater commit 1d3e65aa7ac5 ("hw/timer: Add value matching support to aspeed_timer") increased the vmstate version of aspeed.timer because the state had changed, but it also bumped the version of the VMSTATE_STRUCT_ARRAY under the aspeed.timerctrl which did not need to. Change back this version to fix migration. Signed-off-by: C=C3=A9dric Le Goater Message-id: 20180423101433.17759-1-clg@kaod.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/timer/aspeed_timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c index 50acbf530a..1e31e22b6f 100644 --- a/hw/timer/aspeed_timer.c +++ b/hw/timer/aspeed_timer.c @@ -504,7 +504,7 @@ static const VMStateDescription vmstate_aspeed_timer_st= ate =3D { VMSTATE_UINT32(ctrl, AspeedTimerCtrlState), VMSTATE_UINT32(ctrl2, AspeedTimerCtrlState), VMSTATE_STRUCT_ARRAY(timers, AspeedTimerCtrlState, - ASPEED_TIMER_NR_TIMERS, 2, vmstate_aspeed_tim= er, + ASPEED_TIMER_NR_TIMERS, 1, vmstate_aspeed_tim= er, AspeedTimer), VMSTATE_END_OF_LIST() } --=20 2.17.0 From nobody Thu Dec 18 22:21:22 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1524740807362682.7490227764071; Thu, 26 Apr 2018 04:06:47 -0700 (PDT) Received: from localhost ([::1]:41516 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBehf-0007zg-9I for importer@patchew.org; Thu, 26 Apr 2018 07:04:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39888) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBeR2-0002mR-MG for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fBeR1-0001d7-HR for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:32 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:41154) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fBeR1-0001XB-8N for qemu-devel@nongnu.org; Thu, 26 Apr 2018 06:47:31 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fBeR0-00037G-4o for qemu-devel@nongnu.org; Thu, 26 Apr 2018 11:47:30 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 26 Apr 2018 11:47:15 +0100 Message-Id: <20180426104715.21702-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180426104715.21702-1-peter.maydell@linaro.org> References: <20180426104715.21702-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 19/19] xilinx_spips: Correct SNOOP_NONE state when flushing the txfifo X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Sai Pavan Boddu SNOOP_NONE state handle is moved above in the if ladder, as it's same as SNOOP_STRIPPING during data cycles. Signed-off-by: Sai Pavan Boddu Reviewed-by: Francisco Iglesias Message-id: 1524119244-1240-1-git-send-email-saipava@xilinx.com Signed-off-by: Peter Maydell --- hw/ssi/xilinx_spips.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 426f971311..03f5faee4b 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -616,7 +616,8 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) if (fifo8_is_empty(&s->tx_fifo)) { xilinx_spips_update_ixr(s); return; - } else if (s->snoop_state =3D=3D SNOOP_STRIPING) { + } else if (s->snoop_state =3D=3D SNOOP_STRIPING || + s->snoop_state =3D=3D SNOOP_NONE) { for (i =3D 0; i < num_effective_busses(s); ++i) { tx_rx[i] =3D fifo8_pop(&s->tx_fifo); } --=20 2.17.0