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[76.173.164.138]) by smtp.gmail.com with ESMTPSA id z127sm27767966pfb.72.2018.04.24.18.23.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 24 Apr 2018 18:23:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8opmoPXOJ8uXBYz3POcElJbVpN+z1Cw+TI2+idGCP4k=; b=KWbUbQ778jV6KTtE3go6H8r8mV7AtmaAZ1pmhdyugAa7as+zO8BhHZqhZDN/neXusN fZTmpn69usYwBFl3tcHNeY0T/kKwwHQV3RqhQEgwAU5vNza8N23eV3wznczkWLoQL/rb UCR8fq/syJabN2h67rcp/I/+g/219pKPpbs44= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8opmoPXOJ8uXBYz3POcElJbVpN+z1Cw+TI2+idGCP4k=; b=aj5/Q8AChpKc6s0kGTjwvR2o6J1ZN5Rsg4wnHo3x80I9LR3ngMeby8CYQFqJCb4lhY oQiYgxc4X1y+5JW9/Wpr2LZs3BrKT4vOhe0Ed4kpqyBtbByNfiHZTa6yV6MpafoXUUXu OZ4dtLlr1KNDoKMOyHxvlG33Cqb/sXyMALtE2lR1B5vbZW6XbwcxQm/gYb3u3ea3W4TS ZghGoExp4fJ7LRVAIYwoJIlnDjS1dwee/g/RdEOQrhUEkYqoW+gqhdT68zGw5zO8xokY WuXlwWaz1XnXPuBslQEsUoszUCHrDqyTsN02L2LBPZ/E6aQs5sbZKV4szHxEBp1l00Bu da4Q== X-Gm-Message-State: ALQs6tAPDp3y0fZYiCmEccbqMQCGXOfB+NnOBihOGV6/d1fOCiacRYKx MwtFUljkQPfjWFwsSXXanWCCWrYvY6Q= X-Google-Smtp-Source: AIpwx4+ffX1iHOfku4ON3He7jDH+uNsjawXUVo9BpRQGo4NfcUL9k1xO+WNsm5t3/rxaxWbgixh5Zw== X-Received: by 10.99.176.8 with SMTP id h8mr21988232pgf.448.1524619401084; Tue, 24 Apr 2018 18:23:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 24 Apr 2018 15:22:59 -1000 Message-Id: <20180425012300.14698-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180425012300.14698-1-richard.henderson@linaro.org> References: <20180425012300.14698-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH 8/9] target/arm: Implement FP data-processing (2 source) for fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We missed all of the scalar fp16 binary operations. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/translate-a64.c | 73 ++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 73 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 794ede7222..11b90b7eb0 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -532,6 +532,14 @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg) return v; } =20 +static TCGv_i32 read_fp_hreg(DisasContext *s, int reg) +{ + TCGv_i32 v =3D tcg_temp_new_i32(); + + tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16)); + return v; +} + /* Clear the bits above an N-bit vector, for N =3D (is_q ? 128 : 64). * If SVE is not enabled, then there are only 128 bits in the vector. */ @@ -4968,6 +4976,61 @@ static void handle_fp_2src_double(DisasContext *s, i= nt opcode, tcg_temp_free_i64(tcg_res); } =20 +/* Floating-point data-processing (2 source) - half precision */ +static void handle_fp_2src_half(DisasContext *s, int opcode, + int rd, int rn, int rm) +{ + TCGv_i32 tcg_op1; + TCGv_i32 tcg_op2; + TCGv_i32 tcg_res; + TCGv_ptr fpst; + + tcg_res =3D tcg_temp_new_i32(); + fpst =3D get_fpstatus_ptr(true); + tcg_op1 =3D read_fp_hreg(s, rn); + tcg_op2 =3D read_fp_hreg(s, rm); + + switch (opcode) { + case 0x0: /* FMUL */ + gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x1: /* FDIV */ + gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x2: /* FADD */ + gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x3: /* FSUB */ + gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x4: /* FMAX */ + gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x5: /* FMIN */ + gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x6: /* FMAXNM */ + gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x7: /* FMINNM */ + gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x8: /* FNMUL */ + gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); + tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000); + break; + default: + g_assert_not_reached(); + } + + write_fp_sreg(s, rd, tcg_res); + + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(tcg_op1); + tcg_temp_free_i32(tcg_op2); + tcg_temp_free_i32(tcg_res); +} + /* Floating point data-processing (2 source) * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 * +---+---+---+-----------+------+---+------+--------+-----+------+------+ @@ -5000,6 +5063,16 @@ static void disas_fp_2src(DisasContext *s, uint32_t = insn) } handle_fp_2src_double(s, opcode, rd, rn, rm); break; + case 3: + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + unallocated_encoding(s); + return; + } + if (!fp_access_check(s)) { + return; + } + handle_fp_2src_half(s, opcode, rd, rn, rm); + break; default: unallocated_encoding(s); } --=20 2.14.3